A high-precision and low-power approximate shift multiplier for neural networks

Abstract

The present invention discloses a high-precision, low-power approximate shift multiplier for neural networks, comprising a multiplier approximation unit, a priority encoder, a barrel shifter, and an approximate adder unit. The multiplier approximation unit comprises a non-zero highest position zero module and a high-bit detection module. Based on the Mitchell principle, one of the input operands is approximated to its nearest power of 2 by the high-bit detection unit, the other input operand is extracted to its highest power using a priority encoder, and the second highest power is extracted using a non-zero highest position zero module. This design method significantly improves the accuracy and also completes the approximation of the input multiplier. The shifter is the core module used in this design. Compared with the multiplication operation, the shift operation consumes less power, so this design can significantly reduce power consumption. Finally, the result obtained by the shift is accumulated using an LOA-type approximate adder and the multiplication result is output. This design greatly reduces the power consumption of the design circuit while also improving the accuracy of the multiplier.

Description

Technical Field

[0001] The invention relates to a high-precision, low-power approximate shift multiplier, and belongs to the technical field of neural networks. Background Art

[0002] Convolutional neural networks, one of the most widely used techniques in machine learning, perform tasks like image classification through a large number of repeated convolution operations, continuously multiplying input image data with weight data and accumulating the products to produce the output. The development of convolutional neural networks shows that to solve more complex problems, the network size and number of layers of convolutional neural networks have increased rapidly. This surge in convolutional computations has led to increased computing power and storage requirements.

[0003] The core of convolutional computing is the multiplication-accumulation unit, which consists of a multiplier and an adder. The multiplication-accumulation operation is the main source of computing power. Therefore, an efficient multiplication-accumulation unit is very important for convolutional neural networks.

[0004] Traditional multipliers require three steps: generating partial products, compressing them, and finally accumulating the compressed products. This multiplier structure has complex logic and a large circuit area, making it inadequate for applications requiring high hardware resources.

[0005] Approximate circuits, as energy-efficient circuits used in fault-tolerant applications, improve the power consumption, latency, and area performance of integrated circuits by sacrificing some data accuracy. Extensive research on approximate computing has been conducted in both software and hardware, but these methods have proven to contain significant errors and produce unreliable results.

[0006] Highly computationally intensive applications such as multimedia processing and machine learning require fault-tolerant networks. These fault-tolerant applications are primarily centered around computational units, relying heavily on multiplication and addition operations. Therefore, optimizing the multiplier is crucial to improving computational efficiency and reducing overall power consumption. Therefore, we propose a high-precision, low-power approximate shift multiplier. Summary of the Invention

[0007] Technical problem: In order to solve the problems of power consumption and large errors in the existing technology, the present invention provides a high-precision, low-power approximate shift multiplier for neural networks, which can significantly reduce the computational power consumption of convolutional neural networks while effectively improving the accuracy.

[0008] Technical solution: A high-precision, low-power approximate shift multiplier for neural networks of the present invention comprises a multiplier approximation module, a priority encoder module, a barrel shifter module and an approximate adder module;

[0009] The multiplier approximation module of the approximate shift multiplier includes a non-zero highest position zero module, a non-zero highest position zero unit, and a high-bit detection module. The non-zero highest position zero module is used to set the non-zero highest position of the input operand to zero; the non-zero highest position zero unit sets the highest bit "1" of the input operand to zero, and then sends the zeroed operand to the priority encoder module to detect the index value of the non-zero second highest bit; the high-bit detection module approximates the input operand to the power closest to 2 to achieve approximate conversion of the input operand, and finally controls the barrel shifter module to shift through the priority encoder module to obtain the result of the remainder;

[0010] The priority encoder module includes a first priority encoder, a second priority encoder and a third priority encoder, which detects the non-zero highest bit and controls the barrel shifter module to perform a logical left shift, thereby achieving 2 k1 *r2,2 k2 *B, 2 k3 *B calculation; extracting the highest bit index value based on the outputs of the non-zero highest position zero module, the non-zero highest position zero unit, and the high-bit detection module to determine the required shift number; wherein k1, k2, and k3 correspond to the shift numbers controlled by the third, first, and second priority encoders, r2 is the remainder, B is one of the input operands, and * is a multiplication operation;

[0011] The barrel shifter module includes a first barrel shifter module, a second barrel shifter module, and a third barrel shifter module, and the number of bits shifted to the left is guided by k1, k2, and k3 extracted by the first priority encoder, the second priority encoder, and the third priority encoder;

[0012] The approximate adder module adopts an LOA-type approximate adder, that is, an approximate adder that uses an "OR" operation on the low bit, which converts the multiplication operation into a shift and addition operation, simplifies the operation, and reduces power consumption; the LOA-type approximate adder uses an "OR" operation on the low bit to sum the three parts obtained by the product term and performs an addition operation in the form of a high-bit precise operation.

[0013] The non-zero highest position zero module and the non-zero highest position zero unit in the multiplier approximation module are composed of fourteen OR gates, fourteen AND gates and a buffer. The non-zero highest position zero module sets the highest position of the input operand to zero through the AND gates, OR gates and buffer.

[0014] The non-zero highest position zero module and the non-zero highest position zero unit, when the input operand is 0110_1010, set the second highest position 1 to zero through the non-zero highest position zero module and the non-zero highest position zero unit, and keep the other bits unchanged, that is, the output is 0010_1010; its highest bit is controlled by the buffer, that is, the input is equal to the output, the output of the second highest bit is obtained by ANDing the highest bit and the second highest bit of the input data, and the other bits remain unchanged, so that the non-zero highest bit of the input operand can be set to zero.

[0015] The high-bit detection module consists of eighteen AND gates, three OR gates, and eleven NOT gates. The high-bit detection unit is used to approximate the input operand to the power of 2, and the output of the high-bit detection module is represented using a one-hot code. This design changes the error distribution pattern and improves accuracy.

[0016] The high-order detection module, when inputting an operand of 0111_1101, approximates the input operand to its closest power of 2, i.e., 1000_0000, thereby realizing approximate conversion of the operand. The output obtained by the approximate conversion of the high-order detection module is fed into the priority encoder module to extract the index value of the highest power of the input operand, thereby controlling the barrel shifter module to perform a shift operation.

[0017] The priority encoder module includes a first priority encoder, a second priority encoder and a third priority encoder, which detects the position of the non-zero highest bit of the input operand and the position when the highest bit is "1". According to the position of the value of the non-zero highest bit, through the logical judgment of the AND gate or the OR gate, it generates and outputs the corresponding shift number k1, k2, k3 of the position. The index value is used to control the first barrel shifter, the second barrel shifter and the third barrel shifter to perform a logical left shift.

[0018] The barrel shifter module receives the index values ​​k1, k2 and k3 generated by the first priority encoder, the second priority encoder and the third priority encoder, performs left shift operations on the input operands by k1, k2 and k3 bits according to the shift number provided by the priority encoder module, and sends the shifted results to the LOA type approximate adder module to perform approximate addition operations.

[0019] The approximate adder module divides the input 32-bit operand into two parts: a high-order 14-bit part and an 18-bit low-order part. The high-order part is calculated using a precise sub-adder, which is a ripple-carry adder, ensuring high-precision results. The approximate adder module uses an OR gate to calculate the 18-bit low-order part. When the most significant bit (the 17th bit) of the low-order parts of both operands is 1, an AND gate generates a carry signal to the high-order part, reducing the calculation error of the high-order sub-adder. Because the LOA-type adder of the approximate adder module uses an OR gate to calculate the low-order part, its circuit area is small and the latency is low, with the critical path determined by the precise sub-adder. Furthermore, the more bits are truncated, the faster the multiplier calculation speed.

[0020] Beneficial effects: Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0021] (1) Simple design logic. Most existing approximate multipliers perform calculations by generating partial products, which results in complex logic. The present invention uses a shift and accumulate method for multiplication, which results in simple calculation logic.

[0022] (2) Significant reduction in power consumption: The present invention uses a barrel shifter as the core unit of the approximate shift multiplier circuit, which significantly reduces the circuit power consumption by 58.44%.

[0023] (3) The calculation error of the present invention is within 1.8%, and the accuracy is significantly improved. The hardware resource consumption is small, and it is more suitable for fault-tolerant applications such as neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the working process of the approximate shift multiplier of the present invention,

[0025] Figure 2 This is the overall structural block diagram of the approximate shift multiplier of the present invention.

[0026] Figure 3 This is a flow chart of the calculation of the approximate shift multiplier of the present invention,

[0027] Figure 4 The non-zero highest position zero unit circuit structure diagram of the present invention,

[0028] Figure 5 The circuit structure diagram of the priority encoder of the present invention.

[0029] The figure includes: multiplier approximation module 1, priority encoder module 2, barrel shifter module 3, approximate adder module 4, non-zero highest position zero module 1.1, non-zero highest position zero unit 1.2, high-bit detection module 1.3, first priority encoder 2.1, second priority encoder 2.2, third priority encoder 2.3, first barrel shifter module 3.1, second barrel shifter module 3.2, and third barrel shifter module 3.3. DETAILED DESCRIPTION

[0030] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings:

[0031] The present invention provides a high-precision and low-power approximate shift multiplier for neural networks, such as Figure 1-2 The invention is inserted into a convolutional neural network hardware accelerator based on a systolic array, replacing the precise multiplier in the systolic array multiply-accumulate unit (MAC) for calculation. The approximate multiplier inputs are weights and external input data. The approximate shift multiplier circuit includes: a multiplier approximation unit 1, a priority encoder unit 2, a barrel shifter unit 3, and an approximate adder unit 4. The multiplier approximation unit 1 includes a non-zero highest position zero module 1.1, a non-zero highest position zero unit 1.2, and a high-bit detection module 1.3.

[0032] This circuit uses the non-zero highest bit zeroing module 1.1 and the non-zero highest bit zeroing unit 1.2 in the multiplier approximation unit 1 to set the non-zero highest bit and the non-zero second-highest bit of input operand A to zero. The high bit detection module 1.3 and the third priority encoder 2.3 in the multiplier approximation unit 1 extract the shift number k1. This value k1 controls the third barrel shifter 3.3 to shift the remainder r2 of input operand A left by k1 bits. Simultaneously, the first priority encoder 2.1 extracts the non-zero highest bit index k2 of input operand A. This value k2 controls the first barrel shifter 3.1 to shift input operand B left by k2 bits. Simultaneously, the non-zero highest bit zeroing unit 1.1 sets the highest bit of input operand A to zero. The second priority encoder 2.2 extracts the shift number k3 of its non-zero most significant bit. This value k3 controls the second barrel shifter 3.2 to shift input operand B left by k3 bits. The results of the three partial product terms are sent to the approximate adder module 4 for accumulation to obtain the final output result.

[0033] like Figure 4As shown, the core of the non-zero highest position zero unit in the multiplier approximation unit is fourteen OR gates, fourteen AND gates and a buffer. The buffer is used to set the highest position of the output to zero. For the case where the input data is 16 bits, Output

[15] is directly set to zero. The output of the second highest bit to the lowest bit is controlled by the OR gate and AND gate logic. For example, the output of the second highest bit, Output

[14] , is equal to the highest bit A

[15] of the input data and the second highest bit A

[14] performing a logical AND operation. The output of the next bit of the second highest bit, Output

[13] , is equal to the result of the OR operation of the highest bit A

[15] and the second highest bit A

[14] and A

[13] . And so on, until the logical operation of the lowest bit Output[0] is completed. The main function of this module is to set the non-zero highest position of the input data to zero.

[0034] The core of the high-bit detection module 1.3 in the multiplier approximation unit 1 is composed of eighteen AND gates, three OR gates, and eleven NOT gates. The high-bit detection module 1.3 approximates the input operand to its nearest power of two. This approximation can be too large or too small for different input operand sizes. The output of the high-bit detection module 1.3 is represented in the form of a one-hot code. This unit changes the error distribution pattern, effectively improving accuracy. The main function of the high-bit detection module 1.3 is to output the shift number k1 that is sent to the priority encoder module 2 to extract the non-zero most significant bit that is closest to the value of the input operand.

[0035] like Figure 5 As shown, the priority encoder module 2 is a circuit that compresses multi-bit binary inputs into a smaller number of outputs. Its output is a binary representation of the input from ordinal 0 to the most significant bit. It also allows for multiple input signals to be simultaneously input. The encoder encodes only the highest priority signal among the input signals, based on their priority order. In this circuit, the priority encoder module 2 detects whether the non-zero most significant bit of the output from the non-zero most significant bit zero module 1.1, the non-zero most significant bit zero unit 1.2, or the high bit detection module 1.3 is valid. If a non-zero most significant bit is detected, the priority encoder module 2 extracts the shift numbers k1, k2, and k3 of the non-zero most significant bit.

[0036] The barrel shifter module 3 consists of multiple 1-bit multiplexers. The first barrel shifter 3.1, the second barrel shifter 3.2, and the third barrel shifter 3.3 perform logical left shifts. A control signal S controls the number of bits shifted left, with D representing the binary number to be shifted. The shift numbers k1, k2, and k3 from the priority encoder module 2 serve as control signals, controlling the first barrel shifter 3.1, the second barrel shifter 3.2, and the third barrel shifter 3.3 to shift left by the corresponding number of bits.

[0037] The accumulation unit is a 32-bit LOA-type approximate adder. Its basic structure consists of a full adder, an AND gate, and an OR gate. The high-order bits use a precise sub-adder, a ripple-carry full adder, to ensure high-precision results. The low-order bits use an approximate adder, and an OR gate calculates the low-order portion. The result of this low-order portion has a minimal impact on overall computational accuracy. When the most significant bit of the low-order portion of both operands is 1, an AND gate generates a carry signal to the high-order bits, minimizing computational errors in the precise high-order sub-adder.

[0038] The multiplier includes a non-zero highest position zero module 1.1, a non-zero highest position zero unit 1.2, a high position detection module 1.3, a priority encoder module 2, a barrel shifter module 3, and an approximate adder module 4. All modules cooperate with each other to jointly complete the multiplication approximation calculation, including the following steps:

[0039] (1) The bit widths of input operands A and B are both 16.

[0040] (2) For the two input multipliers in step (1), A = n1 + n2 + r2, n1 = 2 k2 ,n2=2 k3 , B=m1+r1,m1=2 k1 , where the values ​​of k1, k2, and k3 are called the eigenvalues ​​of operands A and B, respectively, representing the effective bits of the operation. That is, A*B = (n1+n2)B+m1r2+r1r2. The term r1r2 is omitted here, which introduces a small error.

[0041] (3) In order to extract the remainder r2 of the input operand A, the highest bit and the second highest bit of the input operand A are set to zero using the non-zero highest bit zero module 1.1 and the non-zero highest bit zero unit 1.2.

[0042] (4) In order to extract the highest power term m1 of the input operand B, the high-order detection module 1.3 is used to convert the input operand B to its nearest power of 2, and the output of the high-order detection module 1.3, that is, the index value k1 of the position where its non-zero highest bit is 1, is extracted using the third priority encoder 2.3. The index value k1 is used to control the number of bits by which the input of the third barrel shifter 3.3, that is, the remainder term r2 of the input operand A obtained in step (3) is shifted to the left, thereby generating the partial product m1r2.

[0043] (5) In order to extract the highest power term n1 of the input operand A, the first priority encoder 2.1 is used to extract the shift number k2 of the input operand A whose highest non-zero bit is 1. The shift number k2 is used to control the number of bits to be shifted to the left by the first barrel shifter 3.1. At the same time, the input operand B in step (2) is input into the first barrel shifter 3.1 to generate the partial product 2 k2B.

[0044] (6) In order to extract the second highest power term n2 of the input operand A, the non-zero highest bit of the input operand A is set to zero by the non-zero highest bit zeroing unit 1.1. The non-zero most significant bit of the input operand A after being set to zero is the second highest bit of the input operand A before being set to zero. The second priority encoder 2.2 is used to extract the shift number k3 of the non-zero most significant bit of the input operand A. The index value k3 is used to control the number of bits to be shifted to the left by the second barrel shifter 3.2. At the same time, the input operand B in step (2) is input into the second barrel shifter 3.2, thereby generating the partial product 2. K3 B.

[0045] (7) In the final accumulation stage, the LOA type approximate adder is used to add the three partial product terms, namely 2 K2 B. 2 K3 B. m1r2 are accumulated. The high-order part uses a precise ripple carry adder, and the low-order part uses an LO-type approximate adder. It can be seen from the error distribution that the approximate adder can effectively improve the accuracy and finally output a 32-bit multiplication result.

[0046] For example:

[0047] Operand A = 16'b 1111_1110_0000_0001, operand B = 16'b 0111_1111_1111_1001, N = 16, and the result of multiplying operands A and B is 32'b 0111_1110_1111_1001_1000_1101_1111_1001 = 2,130,284,025.

[0048] Rewrite the input operand A according to the approximation strategy, that is, A = 2 15 +2 14 +r2, after calculation r2=16'b0011_1110_0000_0001, rewrite the input operand B, that is, B=2 15 +r1, after the input operand A passes through the non-zero highest position zero module 1.1 and the non-zero highest position zero module 1.2, the remainder r2 of the operand A is obtained as 16'b 0011_1110_0000_0001.

[0049] In order to extract the index value of the highest power of input operand B, input operand B is approximated to 16'b 1000_0000_0000_0000 by high bit detection unit 1.3, and the shift number k1=15 of its non-zero highest bit is extracted using third priority encoder 2.3. This index value is used to control the third barrel shifter 3.3 to shift the remainder r2 of input operand A to the left by 15 bits to obtain

[0050] m1r2=32'b0001_1111_0000_0000_1000_0000_0000_0000=520,126,464;

[0051] The input operand A is passed through the first priority encoder 2.1 to extract the shift number of its non-zero highest bit, that is, k2=15. K2 controls the input operand B of the first barrel shifter 3.1 to shift left by 15 bits, that is, 2 K2 B=32'b0011_1111_1111_1100_1000_0000_0000_0000=1,073,512,448

[0052] The input operand A is passed through the non-zero highest position zero unit 1.1 to set its non-zero most significant position to zero, and the second priority encoder 2.2 is used to extract the index value of the second highest position, that is, k3=14. K3 controls the input operand B of the second barrel shifter 3.2 to shift left by 14 bits, so as to obtain 2 k3 B=32'b0001_1111_1111_1110_0100_0000_0000_0000=536,756,224;

[0053] The three partial products are accumulated using an LOA approximate adder. The high 14 bits of the output of 32 are calculated using an exact adder, i.e., a ripple carry adder, and the low 18 bits are approximated using an OR gate. In this example, the output of the multiplier is 32'b0111_1110_1111_1010_1100_0000_0000_0000=2,130,362,368.

[0054] For input operand A = 16'b1111_1110_0000_0001 and operand B = 16'b0111_1111_1111_1001, the average relative error distance MRED = 3.6×10 -5 ,This indicator represents the accuracy, and its error is only 0.036%. The output value of the approximate multiplier is very different from the output value of the exact multiplier, which can be approximately ignored and is acceptable for convolutional neural networks.

[0055] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A high-precision, low-power approximate shift multiplier for neural networks, characterized by: The approximate shift multiplier comprises a multiplier approximation module (1), a priority encoder module (2), a barrel shifter module (3) and an approximate adder module (4); The multiplier approximation module (1) of the approximate shift multiplier comprises a non-zero highest position zero module (1.1), a non-zero highest position zero unit (1.2) and a high position detection module (1.3), wherein the non-zero highest position zero module (1.1) is used to set the non-zero highest position of the input operand to zero; the non-zero highest position zero unit (1.2) sets the highest position "1" of the input operand to zero, and then sends the zeroed operand to the priority encoder module (2) to detect the index value of the non-zero second highest position; the high position detection module (1.3) approximates the input operand to the power closest to 2, thereby realizing the approximate conversion of the input operand, and finally controls the barrel shifter module (3) to shift through the priority encoder module (2) to obtain the result of the remainder; The priority encoder module (2) includes a first priority encoder (2.1), a second priority encoder (2.2) and a third priority encoder (2.3), which detects the non-zero highest bit and controls the barrel shifter module (3) to perform a logical left shift, thereby achieving 2 k1 *r2,2 k2 *B, 2 k3 *B calculation; extracting the highest bit index value based on the output of the non-zero highest position zero module (1.1), the non-zero highest position zero unit (1.2) and the high bit detection module (1.3) to determine the required shift number; wherein k1, k2 and k3 correspond to the shift numbers controlled by the third, first and second priority encoders, r2 is the remainder, B is one of the input operands, and * is a multiplication operation; The barrel shifter module (3) comprises a first barrel shifter module (3.1), a second barrel shifter module (3.2), and a third barrel shifter module (3.3), and is configured to indicate the number of bits to be shifted to the left according to k1, k2, and k3 extracted by the first priority encoder (2.1), the second priority encoder (2.2), and the third priority encoder (2.3); The approximate adder module (4) adopts an LOA type approximate adder, that is, an approximate adder using an "OR" operation on the low bit, which converts the multiplication operation into a shift and addition operation, simplifies the operation, and reduces power consumption; the LOA type approximate adder uses an "OR" operation on the low bit to sum the three parts obtained by the product term, and performs an addition operation in the form of a high-bit precise operation.

2. The high-precision, low-power approximate shift multiplier for neural networks according to claim 1, characterized in that: The non-zero highest position zero module (1.1) and the non-zero highest position zero unit (1.2) in the multiplier approximation module (1) are composed of fourteen OR gates, fourteen AND gates and a buffer. The non-zero highest position zero module sets the highest position of the input operand to zero through the AND gates, OR gates and buffer.

3. The high-precision, low-power approximate shift multiplier for neural networks according to claim 2, characterized in that: The non-zero highest position zero module (1.1) and the non-zero highest position zero unit (1.2) are configured to set the second highest position 1 to zero when the input operand is 0110_1010, and the other bits remain unchanged, that is, the output is 0010_1010; the highest bit is controlled by a buffer, that is, the input is equal to the output, the output of the second highest bit is obtained by ANDing the highest bit and the second highest bit of the input data, and the other bits remain unchanged, so that the non-zero highest bit of the input operand can be set to zero.

4. The high-precision, low-power approximate shift multiplier for neural networks according to claim 1, characterized in that: The high-bit detection module (1.3) is composed of eighteen AND gates, three OR gates and eleven NOT gates. The high-bit detection unit is used to approximate the input operand to the power of 2, and the output of the high-bit detection module (1.3) is represented by a one-hot code. This design changes the error distribution pattern and improves accuracy.

5. The high-precision, low-power approximate shift multiplier for neural networks according to claim 4, characterized in that: The high-order detection module (1.3) has an input operand of 0111-1101. After passing through the high-order detection module (1.3), the input operand is approximated to its power of 2, that is, approximated to 1000-0000, thereby realizing approximate conversion of the operand. The output obtained by the approximate conversion of the high-order detection module (1.3) is sent to the priority encoder module (2) to extract the index value of the highest power of the input operand, so as to control the barrel shifter module (3) to perform a shift operation.

6. The high-precision, low-power approximate shift multiplier for neural networks according to claim 1, characterized in that: The priority encoder module (2) comprises a first priority encoder (2.1), a second priority encoder (2.2) and a third priority encoder (2.3), which detects the position of the non-zero highest bit of the input operand, detects the position when the highest bit is "1", and generates and outputs the shift numbers k1, k2, k3 corresponding to the position through logical judgment of an AND gate or an OR gate according to the position of the value of the non-zero highest bit. The index value is used to control the first barrel shifter (3.1), the second barrel shifter (3.2) and the third barrel shifter (3.3) to perform a logical left shift.

7. The high-precision, low-power approximate shift multiplier for neural networks according to claim 1, characterized in that: The barrel shifter module (3) receives index values ​​k1, k2 and k3 generated by the first priority encoder (2.1), the second priority encoder (2.2) and the third priority encoder (2.3), performs a left shift operation on the input operand by k1, k2 and k3 bits according to the shift number provided by the priority encoder module (2), and sends the shifted result to the LOA type approximate adder module (4) to perform an approximate addition operation.

8. The high-precision, low-power approximate shift multiplier for neural networks according to claim 1, characterized in that: The approximate adder module (4) divides the input 32-bit operand into two parts, a 14-bit high-order part and an 18-bit low-order part; wherein the high-order part is calculated by an accurate sub-adder, which is a ripple carry adder to ensure a high-precision result; The approximate adder module (4) uses an OR gate to calculate the 18 bits of the low-order part; when the most significant bit of the low-order parts of the two operands, i.e., the 17th bit, is both 1, an AND gate is used to generate a carry signal to the high-order part, thereby reducing the calculation error of the high-order sub-adder; since the LOA type adder of the approximate adder module (4) uses an OR gate to calculate the low-order part, its circuit area is small, the delay is low, the critical path is determined by the precise sub-adder, and the more bits are truncated, the faster the calculation speed of the multiplier.

Images