Thick film growth process of cladding layer on PLC wafer

Abstract

The present invention proposes a thick film growth process for the cladding layer on a PLC wafer, which is used to solve the technical problem that the thickness of the upper cladding layer grown by the existing process is too thin and cannot meet the actual performance requirements. The present invention proposes a thick film growth process for the cladding layer on a PLC wafer, which requires the upper cladding layer to be continuously grown and annealed for at least four times, and the thickness of the upper cladding layer meets the requirement of reaching more than 32μm, and increases the annealing step and annealing time, and the means of adjusting the flow rates of the two gases of doping borane and phosphine during the growth process to achieve the purpose of reducing the BOW value, so that the BOW value is less than 250μm; without using a cover plate to protect the chip, the upper cladding layer of the PLC wafer meets the requirements for protecting the waveguide from external force and impurity erosion, protects the core waveguide during the cutting and polishing process, reduces the loss of yield due to reasons such as collapse, and the thickness of the upper cladding layer increases, so that the cross-sectional area becomes larger, and in the later packaging process, the efficiency of connecting the chip with the optical fiber array can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of PLC wafers, and in particular to a cladding thick film growth process on a PLC wafer. Background Art

[0002] like Figure 1 As shown, the general PLC wafer growth process steps are as follows: 1) growing a core layer on a quartz substrate, 2) growing hard mask polysilicon, 3) PR photoresist coating, 4) PR pattern transfer, 5) hard mask etching, 6) removing photoresist, 7) core area etching, 8) removing the hard mask, and 9) covering the upper cladding layer.

[0003] In step 9), the upper cladding layer is made by growing BPSG (boron phospho-silicate glass) by plasma enhanced chemical vapor deposition (PECVD), which is a silicon oxide layer doped with phosphorus P and boron B. The chemical reaction formula is:

[0004] SiH4+2N2O=SiO2+2H2+2N2;

[0005] 2PH3+5N2O=P2O5+3H2+5N2;

[0006] B2H6+3N2O=B2O3+3H2+3N2.

[0007] After the upper cladding is completed, there will be an annealing process to make the film layer denser and eliminate unnecessary impurities. PECVD excites the gas in chemical vapor deposition to produce low-temperature plasma, enhance the chemical activity of the reactants, and thus prepare semiconductor thin film materials on the substrate. Compared with flame hydrolysis (FHD), it has the advantages of high growth accuracy, one-time molding, and stable process. In order to meet the wafer performance yield requirements, the upper cladding layer must meet the following three requirements:

[0008] 1. The refractive index meets the refractive index difference requirement (refractive index difference refers to the difference between the upper cladding layer and the core layer);

[0009] 2. The thickness must be above 20μm;

[0010] 3. The BOW (wafer bow) value of the entire wafer is less than 250μm.

[0011] The thicker the upper cladding, the stronger the protection for the waveguide, which can effectively isolate the influence of external force and impurities on the waveguide, but it will also bring the problem of large BOW value. The general process of generating the upper cladding of PLC wafer includes growing twice and annealing twice to reach a thickness of about 20μm. The Chinese patent application with application number 201710761724.1 discloses an upper cladding growth process for array waveguide grating wafer production. Through FHD, two depositions and two anneals are performed to obtain an upper cladding of 16-20 μm, which can effectively avoid the decomposition of components or uneven melting, obtain a suitable refractive index and reduce the TE / TM difference to a minimum, but also bring some defects. Due to the instability of the process, the control accuracy of the growth thickness is low, and it is a high-temperature process, and the wafer is easy to deform, so a more stable process is needed to more accurately control the growth thickness and doping control.

[0012] In addition, the cover plate is a layer of glass plate used to protect the chip after cutting and forming. The PLC wafer generally has a cover plate to further protect the chip's waveguide from external force and impurities. Some existing PLC wafers are required not to have a cover plate during the sales process due to application needs, and the upper cladding process thickness of the existing PLC wafer is relatively thin, just meeting the thickness requirements and achieving the performance yield requirements. Without using a cover plate to protect the chip, the upper cladding of the PLC wafer has very limited ability to protect the waveguide from external force and impurities. Summary of the invention

[0013] In view of the technical problem that the thickness of the upper cladding layer grown by the existing process is too thin and cannot meet the actual performance requirements, the present invention proposes a thick film growth process for the upper cladding layer of a PLC wafer. By changing the upper cladding layer growth process and the annealing process, the thickness of the upper cladding layer is increased, while meeting various requirements.

[0014] In order to achieve the above object, the technical solution of the present invention is implemented as follows: a thick film growth process of the upper cladding layer of a PLC wafer, continuously performing at least two growth and annealing steps to generate an upper cladding layer with a thickness of 32-40 μm.

[0015] Furthermore, the growth and annealing are performed continuously four times.

[0016] Furthermore, the growth adopts plasma vapor deposition method to generate the upper cladding layer; each growth obtains an upper cladding layer with a thickness of 8 to 10 μm.

[0017] Furthermore, the thickness of the upper cladding layer obtained by each growth is 10 μm.

[0018] Furthermore, in the first growth and the second growth, the gas ratio is borane:phosphine = (2~4): (4~6); in the third growth and the fourth growth, the gas ratio is borane:phosphine = (4~5): (5~7).

[0019] Furthermore, in the first growth and the second growth, the ratio of borane to phosphine is 3.5:4; in the third growth, the ratio of borane to phosphine is 4:5; and in the fourth growth, the ratio of borane to phosphine is 4.5:6.

[0020] Furthermore, the annealing is carried out in an annealing furnace for 6 to 10 hours at a high temperature, wherein the temperature range of the high temperature annealing is 800 to 1200°C.

[0021] Furthermore, the first annealing and the second annealing are performed by performing high temperature annealing at 900-1000° C. in an annealing furnace for 6-8 hours; the third annealing and the fourth annealing are performed by performing high temperature annealing at 1000-1050° C. in an annealing furnace for 8-10 hours.

[0022] Furthermore, a cooling step and annealing time are added in the third annealing and the fourth annealing, and the implementation method is: the annealing temperature is reduced by 80-100° C. and stabilized for 0.5-2 hours; and the cooling is continued in a cycle.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. The present invention requires that the upper cladding layer be grown at least four times, and the thickness of the upper cladding layer is at least 32 μm and at most 40 μm. In addition, during a single upper cladding layer growth process, the flow rates of the two gases, borane and phosphine, are adjusted to increase the fluidity of the film layer, so that the refractive index of the film layer meets the refractive index difference requirement and the BOW value is reduced, so that the BOW value can be less than 250 μm.

[0025] 2. The present invention performs annealing after each growth of the upper cladding layer, adjusts the annealing temperature and annealing time, and adjusts the annealing heating rate from fast to slow, so that the film layer is heated uniformly and does not deform significantly, and increases the annealing steps and annealing time, and adjusts the annealing cooling rate from fast to slow, so as to achieve staged control of cooling and reduce the cooling rate, thereby achieving the purpose of reducing the BOW value, so that the BOW value can be less than 250μm.

[0026] 3. The thick film upper cladding process of the present invention increases the thickness of the upper cladding without significantly increasing the BOW value. The thickness of the upper cladding reaches a minimum of 32 μm and a maximum of 40 μm, which is much larger than the existing upper cladding thickness of 20 μm. Therefore, without using a cover plate to protect the chip, the upper cladding of the PLC wafer can meet the use requirements in protecting the waveguide from external force and impurities, and can further meet the needs of some PLC wafers in practical applications. In addition, the core waveguide can be more effectively protected during the subsequent cutting, grinding and polishing process of the PLC wafer, thereby reducing the loss of yield due to chipping and other reasons.

[0027] 4. The thickness of the upper cladding layer of the present invention is increased, so that the vertical cross-sectional area of ​​the upper cladding layer becomes larger, and in the later packaging process of the PLC wafer, the efficiency of connecting the chip with the FA (fiber array) can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 Schematic diagram of the general PLC wafer growth process.

[0030] Figure 2 This is a microscope photo of the PLC chip made in the present invention.

[0031] Figure 3 It is a schematic diagram of the structure of the upper cladding layer obtained by the present invention.

[0032] Figure 4 Schematic diagram of the structure of the upper cladding layer obtained by a general upper cladding process. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Example 1

[0035] A thick film growth process for a PLC wafer cladding layer, wherein at least four growth and annealing steps are performed continuously to obtain Figure 3 The PLC wafer with a grown thick upper cladding layer is shown. The upper cladding layer is formed by plasma vapor deposition to generate an upper cladding layer with a thickness of 32 to 40 μm. The upper cladding layer is annealed after each growth, and a high-temperature annealing is performed in an annealing furnace for 6 to 10 hours. The temperature range of the high-temperature annealing is 800 to 1200°C.

[0036] It is worth noting that, in the present embodiment, the flow rates of borane and phosphine gases are adjusted before each growth of the upper cladding layer. The flow rates of borane and phosphine gases are adjusted before the last two upper cladding layer growths so that the film thickness meets the requirements and, at the same time, the BOW value is reduced to meet the refractive index difference requirements. The flow rates of borane and phosphine gases are adjusted before the remaining single upper cladding layer growths so that the film layer fluidity is increased and the refractive index of the film layer meets the refractive index difference requirements.

[0037] It is worth noting that, in this embodiment, the annealing temperature needs to be controlled for each annealing after the upper cladding layer grows. The last two annealings are first heated up slowly, and then manually controlled during the slow cooling. The annealing steps and annealing time are increased, and the cooling rate is adjusted from fast to slow to achieve staged control of cooling and reduce the cooling rate, so as to achieve the purpose of reducing the BOW value. For the remaining single annealings, the heating rate needs to be adjusted from fast to slow during heating, so that the film layer is heated evenly and does not deform too much, and the temperature is cooled naturally and slowly during cooling.

[0038] Specifically, in this embodiment, four growth and annealing steps are performed continuously to generate an upper cladding layer with a thickness of 32-40 μm. The specific implementation process is as follows:

[0039] 1) First, the first growth process is carried out to grow an 8~10μm upper cladding layer using a plasma vapor deposition method. The flow rates of borane and phosphine gases in the process are adjusted to increase the fluidity of the film layer and make the refractive index of the film layer meet the refractive index difference requirements.

[0040] It is worth noting that, in this embodiment, the gas ratio in the first growth is borane:phosphine = (2-4): (4-6).

[0041] 2) Place it in an annealing furnace for 6 to 8 hours at 900 to 1000°C high temperature annealing, and adjust the heating rate from fast to slow so that the film layer is heated evenly and does not deform significantly.

[0042] 3) Take it out from the annealing furnace and grow a second 8~10μm upper cladding layer using the same method as step 1).

[0043] It is worth noting that, in this embodiment, the gas ratio in the second growth is borane:phosphine = (2-4): (4-6).

[0044] 4) Place in annealing furnace for 6~8 hours, 900~1000℃ high temperature annealing, the method is the same as step 2).

[0045] 5) Take out the film from the annealing furnace and grow the 8~10μm upper cladding layer for the third time. Adjust the flow rate of the two gases of borane and phosphine in the process to make the film thickness meet the requirements. At the same time, reduce the BOW value to meet the refractive index difference requirements.

[0046] It is worth noting that, in this embodiment, the gas ratio in the third growth is borane:phosphine = (4-5): (5-7).

[0047] 6) Place it in the annealing furnace for high-temperature annealing at 1000~1050℃ for 8~10 hours, increase the annealing steps and annealing time, and adjust the cooling rate from fast to slow to achieve staged control of cooling and reduce the cooling rate to achieve the purpose of reducing the BOW value.

[0048] It is worth noting that, in this embodiment, the implementation method of the cooling step is: the annealing temperature is reduced by 80-100° C., stabilized for 0.5-2 hours; and the cooling is continued in a cycle.

[0049] 7) Take it out from the annealing furnace and grow the 8~10μm upper cladding layer for the fourth time, using the same method as step 5).

[0050] It is worth noting that, in this embodiment, the gas ratio in the fourth growth is borane:phosphine = (4-5): (5-7).

[0051] 8) Place in annealing furnace and perform high temperature annealing at 1000~1050℃ for 8~10 hours, the method is the same as step 6).

[0052] 9) Get Figure 3 PLC wafer with grown thick film upper cladding layer shown.

[0053] Example 2

[0054] A thick film growth process for the upper cladding layer of a PLC wafer. In this embodiment, four consecutive growth and annealing steps are performed to generate an upper cladding layer with a thickness of 40 μm. The steps are as follows:

[0055] 1) First, the first growth process is carried out to grow a 10μm upper cladding layer using a plasma vapor deposition method. The flow rates of borane and phosphine gases in the process are adjusted to increase the fluidity of the film layer and make the refractive index of the film layer meet the refractive index difference requirements.

[0056] It is worth noting that, in this embodiment, the gas ratio in the first growth is borane:phosphine=3.5:4.

[0057] 2) Place it in the annealing furnace for 8 hours at 1000℃ high temperature annealing, adjust the heating rate from fast to slow so that the film layer is heated evenly and does not deform too much. After annealing, cool it down naturally and slowly.

[0058] 3) Take it out from the annealing furnace and grow a 10μm upper cladding layer for the second time, using the same method as step 1).

[0059] It is worth noting that, in this embodiment, the gas ratio in the second growth is borane:phosphine=3.5:4.

[0060] 4) Place in annealing furnace for 8 hours at 1000℃ high temperature annealing, the method is the same as step 2).

[0061] 5) Take out the film from the annealing furnace and grow the 10μm upper cladding layer for the third time. The flow rates of the two gases, borane and phosphine, in the process were adjusted to make the film thickness meet the requirements. At the same time, reducing the BOW value can also meet the refractive index difference requirements.

[0062] It is worth noting that, in this embodiment, the gas ratio in the third growth is borane:phosphine=4:5.

[0063] 6) Place in annealing furnace for high temperature annealing at 1050℃ for 10 hours. First, slowly heat up, then cool down after annealing. Increase annealing steps and annealing time, and adjust the cooling rate from fast to slow to achieve staged control of cooling and reduce the cooling rate, so as to achieve the purpose of reducing BOW value.

[0064] It is worth noting that the cooling steps added in step 6) are as follows: first, the temperature is reduced from 1050°C to 900°C and stabilized for 1 hour; second, the temperature is further reduced from 900°C to 800°C and stabilized for 2 hours; finally, the temperature is continued to be reduced, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0065] 7) Take out from the annealing furnace and grow a 10μm upper cladding layer for the fourth time, using the same method as step 5).

[0066] It is worth noting that, in this embodiment, the gas ratio in the fourth growth is borane:phosphine=4:5.

[0067] 8) Place in annealing furnace and perform high temperature annealing at 1050℃ for 10 hours.

[0068] It is worth noting that the cooling steps added in step 8) are as follows: first, the temperature is reduced from 1050°C to 1000°C and stabilized for 1 hour; second, the temperature is reduced from 1000°C to 900°C and stabilized for 1 hour; third, the temperature is reduced from 900°C to 800°C and stabilized for 1 hour; finally, the temperature is continued to be reduced, the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0069] 9) Get Figure 3 PLC wafer with grown thick film upper cladding layer shown.

[0070] Example 3

[0071] A thick film growth process for the upper cladding layer of a PLC wafer. In this embodiment, four consecutive growth and annealing steps are performed to generate an upper cladding layer with a thickness of 40 μm. The steps are as follows:

[0072] 1) First, the first growth process is carried out to grow a 10μm upper cladding layer using a plasma vapor deposition method. The flow rates of borane and phosphine gases in the process are adjusted to increase the fluidity of the film layer and make the refractive index of the film layer meet the refractive index difference requirements.

[0073] It is worth noting that, in this embodiment, the gas ratio in the first growth is borane:phosphine=2.5:7.

[0074] 2) Place it in the annealing furnace for 8 hours at 1000℃ high temperature annealing, adjust the heating rate from fast to slow so that the film layer is heated evenly and does not deform too much. After annealing, cool it down naturally and slowly.

[0075] 3) Take it out from the annealing furnace and grow a 10μm upper cladding layer for the second time, using the same method as step 1).

[0076] It is worth noting that, in this embodiment, the gas ratio in the second growth is borane:phosphine=2.5:7.

[0077] 4) Place in annealing furnace for 8 hours at 1000℃ high temperature annealing, the method is the same as step 2).

[0078] 5) Take out the film from the annealing furnace and grow the 10μm upper cladding layer for the third time. The flow rates of the two gases, borane and phosphine, in the process were adjusted to make the film thickness meet the requirements. At the same time, reducing the BOW value can also meet the refractive index difference requirements.

[0079] It is worth noting that, in this embodiment, the gas ratio in the third growth is borane:phosphine=1.5:1.4.

[0080] 6) Place in annealing furnace for high temperature annealing at 1020℃ for 10 hours. First, slowly heat up, then cool down after annealing. Increase annealing steps and annealing time, and adjust the cooling rate from fast to slow to achieve staged control of cooling and reduce the cooling rate, so as to achieve the purpose of reducing BOW value.

[0081] It is worth noting that the cooling steps added in step 6) are as follows: first, the temperature is reduced from 1020°C to 900°C and stabilized for 1 hour; secondly, the temperature is further reduced from 900°C to 800°C and stabilized for 2 hours; finally, the temperature is continued to be reduced, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0082] 7) Take out from the annealing furnace and grow a 10μm upper cladding layer for the fourth time, using the same method as step 5).

[0083] It is worth noting that, in this embodiment, the gas ratio in the fourth growth is borane:phosphine=5.5:7.

[0084] 8) Place in annealing furnace and perform high temperature annealing at 1050℃ for 10 hours.

[0085] It is worth noting that the cooling steps added in step 8) are as follows: first, the temperature is reduced from 1050°C to 1000°C and stabilized for 0.5 hours; secondly, the temperature is reduced from 1000°C to 900°C and stabilized for 1 hour; thirdly, the temperature is reduced from 900°C to 800°C and stabilized for 1 hour; finally, the temperature is continued to be reduced, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0086] 9) Get Figure 3 PLC wafer with grown thick film upper cladding layer shown.

[0087] Example 4

[0088] A thick film growth process for a PLC wafer upper cladding layer, which continuously performs four growth and annealing steps to generate an upper cladding layer with a thickness of 32 μm, comprises the following steps:

[0089] 1) First, the first growth process is carried out to grow an 8μm upper cladding layer using a plasma vapor deposition method. The flow rates of borane and phosphine gases in the process are adjusted to increase the fluidity of the film layer and make the refractive index of the film layer meet the refractive index difference requirements.

[0090] It is worth noting that, in this embodiment, the gas ratio in the first growth is borane:phosphine=1.5:3.

[0091] 2) Place it in an annealing furnace for high-temperature annealing at 900℃ for 6 hours, and adjust the heating rate from fast to slow so that the film layer is heated evenly and does not deform significantly. After annealing, cool it down naturally and slowly.

[0092] 3) Take it out from the annealing furnace and grow a second 8μm upper cladding layer using the same method as step 1).

[0093] It is worth noting that, in this embodiment, the gas ratio in the second growth is borane:phosphine=1.5:3.

[0094] 4) Place in annealing furnace for high temperature annealing at 900℃ for 6 hours, the method is the same as step 2).

[0095] 5) Take out the film from the annealing furnace and grow the 8μm upper cladding layer for the third time. The flow rates of the two gases, borane and phosphine, in the process were adjusted to make the film thickness meet the requirements. At the same time, reducing the BOW value can also meet the refractive index difference requirements.

[0096] It is worth noting that, in this embodiment, the gas ratio in the third growth is borane:phosphine=4:7.

[0097] 6) Place it in the annealing furnace for high-temperature annealing at 1000℃ for 8 hours. First, slowly heat it up, then cool it down after annealing. Increase the annealing steps and annealing time, and adjust the cooling rate from fast to slow to achieve staged control of cooling and reduce the cooling rate, so as to achieve the purpose of reducing the BOW value.

[0098] It is worth noting that the cooling steps added in step 6) are as follows: first, the temperature is reduced from 1000°C to 900°C and stabilized for 0.5 hours; second, the temperature is further reduced from 900°C to 800°C and stabilized for 1 hour; finally, the temperature is continued to be reduced, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0099] 7) Take out from the annealing furnace and grow the 8μm upper cladding layer for the fourth time, using the same method as step 5).

[0100] It is worth noting that, in this embodiment, the gas ratio in the fourth growth is borane:phosphine=4:7.

[0101] 8) Place in annealing furnace and perform high temperature annealing at 1000℃ for 8 hours.

[0102] It is worth noting that the cooling steps added in step 8) are as follows: first, the temperature is cooled from 1000°C to 900°C and stabilized for 0.5 hours; second, the temperature is cooled from 900°C to 800°C and stabilized for 1 hour; finally, the temperature is further cooled, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0103] 9) Get Figure 3 PLC wafer with grown thick film upper cladding layer shown.

[0104] Example 5

[0105] A thick film growth process for a PLC wafer upper cladding layer, which continuously performs four growth and annealing steps to generate an upper cladding layer with a thickness of 32 μm, comprises the following steps:

[0106] 1) First, the first growth process is carried out to grow an 8μm upper cladding layer using a plasma vapor deposition method. The flow rates of borane and phosphine gases in the process are adjusted to increase the fluidity of the film layer and make the refractive index of the film layer meet the refractive index difference requirements.

[0107] It is worth noting that in this embodiment, the gas ratio in the first growth is borane:phosphine = 1:1.5

[0108] 2) Place it in an annealing furnace for high-temperature annealing at 900℃ for 6 hours, and adjust the heating rate from fast to slow so that the film layer is heated evenly and does not deform significantly. After annealing, cool it down naturally and slowly.

[0109] 3) Take it out from the annealing furnace and grow a second 8μm upper cladding layer using the same method as step 1).

[0110] It is worth noting that, in this embodiment, the gas ratio in the second growth is borane:phosphine=1:1.5.

[0111] 4) Place in annealing furnace for high temperature annealing at 900℃ for 6 hours, the method is the same as step 2).

[0112] 5) Take out the film from the annealing furnace and grow the 8μm upper cladding layer for the third time. The flow rates of the two gases, borane and phosphine, in the process were adjusted to make the film thickness meet the requirements. At the same time, reducing the BOW value can also meet the refractive index difference requirements.

[0113] It is worth noting that, in this embodiment, the gas ratio in the third growth is borane:phosphine=4:7.

[0114] 6) Place it in the annealing furnace for high-temperature annealing at 1000℃ for 8 hours. First, slowly heat it up, then cool it down after annealing. Increase the annealing steps and annealing time, and adjust the cooling rate from fast to slow to achieve staged control of cooling and reduce the cooling rate, so as to achieve the purpose of reducing the BOW value.

[0115] It is worth noting that the cooling steps added in step 6) are as follows: first, the temperature is reduced from 1000°C to 900°C and stabilized for 0.5 hours; second, the temperature is further reduced from 900°C to 800°C and stabilized for 1 hour; finally, the temperature is continued to be reduced, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0116] 7) Take out from the annealing furnace and grow the 8μm upper cladding layer for the fourth time, using the same method as step 5).

[0117] It is worth noting that, in this embodiment, the gas ratio in the fourth growth is borane:phosphine=4:7.

[0118] 8) Place in annealing furnace and perform high temperature annealing at 1000℃ for 8 hours.

[0119] It is worth noting that the cooling steps added in step 8) are as follows: first, the temperature is cooled from 1000°C to 900°C and stabilized for 0.5 hours; second, the temperature is cooled from 900°C to 800°C and stabilized for 1 hour; finally, the temperature is further cooled, and the temperature for further cooling is selected from 80~100°C, and the stabilization time is selected from 0.5~2 hours.

[0120] 9) Get Figure 3 PLC wafer with grown thick film upper cladding layer shown.

[0121] It is worth noting that the present invention can also perform five consecutive growth and annealing processes on the PLC wafer to grow the upper cladding thick film to prepare the PLC wafer. The thickness of the upper cladding grown each time is 6~8μm, and the upper cladding with a thickness of 32~40μm is generated, which can meet the requirements of the upper cladding. However, after testing, the performance of the PLC wafer prepared by growing and annealing the upper cladding thick film for five consecutive times is reduced compared with the PLC wafer prepared by growing and annealing the upper cladding thick film for four consecutive times in Examples 1 to 5, and as the number of consecutive growth and annealing increases, the performance of the PLC wafer continues to decline. Therefore, in the present invention, growing and annealing the upper cladding thick film for four consecutive times is the optimal number of consecutive growth and annealing times for the upper cladding thick film.

[0122] Experimental example

[0123] After the production was completed, the BOW value, reflow condition and performance yield of the upper cladding layer produced in Examples 1 to 5 were measured. The results showed that after the upper cladding thick film process, the wafer did not have abnormal phenomena such as film cracking after annealing, the BOW value was less than 230μm, and the performance met the requirements. Figure 2 As shown in the microscope photo after the process is completed, there is no film cracking phenomenon. The core waveguide obtained by the thick film process of the present invention and the general coating process are respectively as shown in FIG. Figure 3 and Figure 4 As shown, by comparison, the upper cladding layer of the present invention is doubled in thickness.

[0124] It is worth mentioning that the setting of data in the above-mentioned embodiments 1 to 5 of the present invention mainly considers the following three aspects: 1. The key difficulty of the thick film process of the present invention is the influence of the BOW value (the degree of curvature of the wafer) and the influence of the wafer film cracking. The film layer does not crack after the wafer is annealed. The BOW value after the wafer is annealed must be less than 250um to meet the performance requirements; 2. Using the processes of the first and second layers to make the third and fourth layers will definitely lead to a larger BOW value and film cracking. The thicker the growth, the greater the difficulty. Therefore, it is necessary to set an appropriate thickness and growth process for each growth; 3. The refractive index is closely related to the refractive index difference of the chip design, and is also closely related to the number of chip channels and the chip size. The types of PLC wafer chips are different, and the requirements for the refractive index are also different. Therefore, it is not a fixed value, as long as the refractive index satisfies the refractive index difference.

[0125] Table 1 BOW value measurement results

[0126]

[0127] By using a stress measuring instrument, three groups of PLC wafers with normal upper cladding and three groups of PLC wafers prepared by the thick film growth process of the upper cladding of the PLC wafer of the present invention after adding 20um upper cladding were subjected to bending measurement experiments. The BOW value directly reflects the degree of bending of the wafer. The larger the value, the worse it is, indicating that the wafer is more curved. As can be seen from Table 1, on the basis of satisfying the requirement of increasing the thickness of the upper cladding by 20um and the refractive index satisfying the refractive index difference, the BOW value of the PLC wafer prepared by the present invention is less than 250μm, and even less than 230μm, which can meet the wafer performance yield requirements.

[0128] Table 2 Wafer performance yield table

[0129]

[0130] By using a chip testing machine, the yield rates of three groups of PLC wafers after adding a 20um upper cladding layer prepared by the PLC wafer upper cladding thick film growth process of the present invention were measured. The higher the total yield rate, the better. T-grade products are the best, U-grade is the second, and P-grade is average. It can be seen from Table 2 that the total yield rates of the PLC wafers obtained by the thick film process of the present invention are all above 95%, which can meet the index requirements of the product yield rate.

[0131] In summary, experiments have shown that the upper cladding of the PLC wafer prepared by the PLC wafer upper cladding thick film growth process of the present invention can simultaneously meet the following requirements: 1. The refractive index meets the refractive index difference requirement; 2. The thickness must reach 32μm or more; 3. The BOW value of the entire wafer is less than 250μm, which can ensure the wafer yield on the basis of meeting the actual performance requirements, and the wafer prepared by the present invention does not require a cover plate to provide strong protection for the waveguide, meeting the needs of customers, and in the later packaging process, can improve the efficiency of the connection between the chip and the FA (fiber array), and more effectively protect the core waveguide in the subsequent cutting and polishing process, reducing the loss of yield caused by reasons such as collapse.

[0132] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A process for growing a thick film of a cladding layer on a PLC wafer, characterized in that: Four consecutive growth and annealing steps were performed to produce an upper cladding layer with a thickness of 32 to 40 μm; In the first and second growths, the gas ratio is borane:phosphine = 2~4:4~6; in the third and fourth growths, the gas ratio is borane:phosphine = 4~5:5~7; The first annealing and the second annealing are performed by annealing at 900-1000°C for 6-8 hours in an annealing furnace; the third annealing and the fourth annealing are performed by annealing at 1000-1050°C for 8-10 hours in an annealing furnace; In the third annealing and the fourth annealing, a cooling step and an annealing time are added. The implementation method is: the annealing temperature is reduced by 80-100°C and stabilized for 0.5-2 hours; and the cooling is continued in a cycle.

2. The PLC wafer cladding thick film growth process according to claim 1, characterized in that: The growth adopts plasma vapor deposition method to generate the upper cladding layer; each growth obtains an upper cladding layer with a thickness of 8 to 10 μm.

3. The PLC wafer cladding thick film growth process according to claim 1 or 2, characterized in that: The thickness of the upper cladding layer obtained each time is 10 μm.

4. The PLC wafer cladding thick film growth process according to claim 3, characterized in that: In the first growth and the second growth, the ratio of borane to phosphine is 3.5:4; in the third growth, the ratio of borane to phosphine is 4:5; and in the fourth growth, the ratio of borane to phosphine is 4.5:6.

Images