Manufacturing and measurement system for semiconductor structures

Abstract

A system for manufacturing and measuring a plurality of semiconductor structures is provided. The system includes a processing chamber and a measurement element. The processing chamber is configured to perform operations of forming a first fin array on a block of a die of a wafer and forming a second fin array on the first fin array. The measurement element is configured to perform a pattern wafer geometry measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array and is further configured to determine a condition of the wafer as a function of the displacement.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 508,961 and 17 / 510,786 (i.e., priority dates of “October 22, 2021” and “October 26, 2021”), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a system for manufacturing and measuring a plurality of semiconductor structures. In particular, the present disclosure relates to a system for manufacturing and measuring a plurality of semiconductor structures on a wafer. BACKGROUND

[0003] According to Moore’s law, the density of elements in a semiconductor structure is rapidly increasing, and the size of the elements is rapidly shrinking. Therefore, the alignment problem caused by the shrinking elements becomes more and more important. In some conventional methods, the alignment is checked offline. Moreover, the accuracy of the conventional measurement cannot adapt to the size of the shrinking elements. Therefore, when the position of the elements at the predetermined position is manufactured, the wafer can not work properly, and the above situation can not be known until the manufacturing is completed. Therefore, when the wafer has a plurality of elements that are misaligned to cause the wafer to be unable to be manufactured as a product, the manufacturing resources and the time cost of the wafer are wasted. Moreover, the production of the wafer is reduced.

[0004] The foregoing “background” description is for the purpose of generally presenting the technical field and does not necessarily delineate the present disclosure. The foregoing background is not to be taken as an admission that the “background” is prior art to the present disclosure, that the “background” is part of the common general knowledge of those skilled in the art, or that the “background” is related to solving any of the problems that are solved by the present disclosure. Any discussion of the references states what their authors assert, and the applicants reserve the right to challenge the accuracy and pertinence of the references. SUMMARY

[0005] An embodiment of the present disclosure provides a method for manufacturing and measuring a plurality of semiconductor structures. The method includes the following steps: receiving a wafer, the wafer having a plurality of dies; respectively forming the plurality of semiconductor structures in a plurality of blocks of each die, wherein each semiconductor structure has a first fin array and a second fin array, the second fin array being above the first fin array; performing a pattern wafer geometry measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and determining a status of the wafer according to the displacement.

[0006] In some embodiments, the step of respectively forming the plurality of semiconductor structures in a plurality of blocks of each die includes: forming the first fin array in each block; and forming the second fin array on the first fin array.

[0007] In some embodiments, both the first fin array and the second fin array have N fins, where N is a positive integer. The first fin of the first fin array corresponds to the first fin of the second fin array. The displacement between the first fin of the first fin array and the first fin of the second fin array is defined from a top view of the semiconductor structure.

[0008] In some embodiments, the step of forming the first fin array in each block comprises: forming a first layer; etching the first layer to form the first fin array; and planarizing the first layer to expose an upper surface of the first fin array.

[0009] In some embodiments, the step of forming the second fin array on the first fin array comprises: forming a second layer on the first fin array; etching the second layer to form the second fin array; and planarizing the second layer to expose an upper surface of the second fin array.

[0010] In some embodiments, the step of performing a pattern wafer geometry measurement on the wafer to obtain the displacement between a first fin of the first fin array and a first fin of the second fin array comprises: obtaining a first overlap ratio of the first fin of the first fin array and the first fin of the second fin array; obtaining a second overlap ratio of an Nth fin of the first fin array and an Nth fin of the second fin array; obtaining a center overlap ratio of an Ath fin of the first fin array and an Ath fin of the second fin array; and obtaining the displacement from the first overlap ratio, the second overlap ratio, and the center overlap ratio. When N is an odd number, then A equals (N+1)2, and when N is an even number, then A equals N / 2.

[0011] In some embodiments, the step of obtaining the displacement from the first overlap ratio, the second overlap ratio, and the center overlap ratio comprises: subtracting the first overlap ratio from the center overlap ratio to obtain a first magnification; subtracting the second overlap ratio from the center overlap ratio to obtain a second magnification; and obtaining the displacement from the first magnification and the second magnification.

[0012] In some embodiments, the first magnification is substantially equal to the second magnification.

[0013] In some embodiments, the step of obtaining the displacement from the first magnification and the second magnification comprises: obtaining an average magnification by averaging the first magnification and the second magnification; and obtaining the displacement in a lookup table, wherein the lookup table is configured to store a correspondence between the displacement and the average magnification.

[0014] In some embodiments, the state of the wafer is determined to be a fail state when the displacement is greater than a threshold value, and the state of the wafer is determined to be a pass state when the displacement is not greater than the threshold value. In some embodiments, the threshold value is about 1.5 nm.

[0015] In some embodiments, the method further comprises removing the wafer from a batch of wafers when the state of the wafer is the fail state, and retaining the wafer in the batch of wafers when the state of the wafer is the pass state.

[0016] In some embodiments, the threshold value is about 1.5 nm.

[0017] Another embodiment of the disclosure provides a manufacturing and measurement system. The system includes a processing chamber; and a measurement element. The processing chamber is configured to perform a plurality of operations including forming a first fin array in a block of a die of a wafer, and forming a second fin array on the first fin array. The measurement element is configured to perform a pattern wafer geometry measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array, and is further configured to determine a state of the wafer as a function of the displacement.

[0018] In some embodiments, the displacement is defined from a top view of the wafer.

[0019] In some embodiments, the first fin array and the second fin array have N fins, where N is a positive integer. The measurement element is further configured to measure a first overlap ratio of the first fin of the first fin array and the first fin of the second fin array, measure a second overlap ratio of an Nth fin of the first fin array and an Nth fin of the second fin array, and measure a center overlap ratio of an A th fin of the first fin array and an A th fin of the second fin array. When N is an odd integer, A is equal to (N+1) / 2, and when N is an even integer, A is equal to N / 2.

[0020] In some embodiments, the measurement element is further configured to obtain a first magnification by subtracting the first overlap ratio from the center overlap ratio, obtain a second magnification by subtracting the second overlap ratio from the center overlap ratio, and obtain the displacement as a function of the first magnification and the second magnification.

[0021] In some embodiments, the measurement element is further configured to obtain an average magnification by averaging the first magnification and the second magnification. The measurement element includes a lookup table configured to store a correspondence of the displacement and the average magnification, and is further configured to obtain the displacement as a function of the lookup table.

[0022] In some embodiments, when the displacement is greater than a threshold value, then the status of the die is determined to be a fail status. When the displacement is not greater than the threshold value, then the status of the die is determined to be a pass status.

[0023] In some embodiments, when the status of the wafer is a fail status, the processing chamber is configured to remove the wafer from a batch of wafers.

[0024] In some embodiments, when the status of the wafer is a pass status, the processing chamber is configured to retain the wafer in a batch of wafers.

[0025] The foregoing has outlined rather broadly the technical features and advantages of the technology of the disclosure in order that the detailed description of the disclosure that follows can be understood. Additional technical features and advantages of the disclosure will be described in the detailed description of the disclosure that follows. Such being the case, it should be noted that the detailed description of the disclosure describes and discloses only the preferred embodiments. In view of the foregoing, it will be understood that the concepts and technologies disclosed herein can be utilized without modification or with a modification to design or construct other structures or processes that can achieve the same results as the disclosure. It should also be noted that such equivalent constructions do not depart from the spirit and scope of the disclosure as defined in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] The disclosure will be more fully understood and appreciated by referring to the following detailed description taken in conjunction with the following drawings of which:

[0027] Figure 1 is a structural schematic diagram illustrating a manufacturing system of some embodiments of the disclosure.

[0028] Figure 2 is a structural schematic diagram illustrating a wafer of some embodiments of the disclosure.

[0029] Figure 3 is a structural block diagram illustrating a die of some embodiments of the disclosure.

[0030] Figure 4 is a structural schematic diagram illustrating a block from a top view of the wafer of some embodiments of the disclosure.

[0031] Figure 5 is a structural schematic diagram illustrating a block from a cross-sectional view of the wafer of some embodiments of the disclosure.

[0032] Figure 6 is a structural schematic diagram illustrating a block from a cross-sectional view of the wafer of some other embodiments of the disclosure.

[0033] Figure 7is a structural schematic illustrating a block viewed from a cross-section of the wafer for some alternative embodiments of the present disclosure.

[0034] Figure 8 is a structural schematic illustrating a block viewed from a cross-section of the wafer for some embodiments of the present disclosure as shown in Figure 6 .

[0035] Figure 9 is a structural schematic illustrating a block viewed from a cross-section of the wafer for some embodiments of the present disclosure as shown in Figure 7 .

[0036] Figure 10 is a flow schematic illustrating a method of fabricating a semiconductor structure on a wafer and performing a pattern wafer geometry (PWG) measurement for some embodiments of the present disclosure.

[0037] Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 is a detailed flow schematic illustrating a method as shown in Figure 10 for some embodiments of the present disclosure.

[0038] Figure 17 , Figure 18 , Figure 19 is a structural schematic illustrating a semiconductor structure as described in Figure 12 for some embodiments of the present disclosure.

[0039] Figure 20 and Figure 21 is a structural schematic illustrating a semiconductor structure as described in Figure 13 for some embodiments of the present disclosure.

[0040] wherein the reference numerals are explained as follows:

[0041] 10: fabrication system

[0042] 100: processing chamber

[0043] 200: measurement element

[0044] 210: look-up table

[0045] A1: first fin array

[0046] A2: second fin array

[0047] B: batch of wafers

[0048] BA: block

[0049] D: die

[0050] d: width

[0051] d1: displacement

[0052] d2: displacement

[0053] d(N-1): displacement

[0054] dN: displacement

[0055] F11, F12 ~ F1N: fin

[0056] F21, F22 ~ F2N: fin

[0057] FAIL: fail state

[0058] L1: first layer

[0059] L2: second layer

[0060] M10: method

[0061] PASS: pass state

[0062] S101: step

[0063] S102: step

[0064] S103: step

[0065] S104: step

[0066] S105: step

[0067] S106: step

[0068] S107: step

[0069] S111: step

[0070] S112: step

[0071] S121: step

[0072] S122: step

[0073] S123: step

[0074] S131: step

[0075] S132: step

[0076] S133: step

[0077] S141: step

[0078] S142: step

[0079] S143: step

[0080] S144: step

[0081] S151 : step

[0082] S152: step

[0083] S153: step

[0084] S161 : step

[0085] S162: step

[0086] SS: semiconductor structure

[0087] W: wafer

[0088] X: directional axis

[0089] Y: directional axis

[0090] Z: directional axis DETAILED DESCRIPTION

[0091] A number of embodiments (or examples) of the present disclosure are now described using specific language. It should be understood that such embodiments are not intended to limit the scope of the present disclosure. Any alterations and / or modifications to the described embodiments, and any further applications of the principles described herein are contemplated as falling within the scope of the present disclosure. Element numbers can be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same element number.

[0092] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and sections, these elements, components, regions, layers and sections should not be limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, terms discussed below as the first element, component, region, layer or section can be called the second element, component, region, layer or section without departing from the teachings of the present inventive concept.

[0093] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0094] Figure 1 is a structural schematic diagram illustrating a manufacturing system 10 of some embodiments of the present disclosure. The manufacturing system 10 is configured to process a batch of wafers B and also to inspect each wafer W in the batch of wafers B to determine a status of each wafer W. For example, the manufacturing system 10 performs a plurality of semiconductor processes on the batch of wafers B and measures a physical feature (e.g., a dimension of a particular structure) on each wafer W to determine the status of the wafer W in accordance with the measurement.

[0095] The manufacturing system 10 includes a processing chamber 100 and a measurement element 200, and the measurement element 200 is coupled to the processing chamber 100. The processing chamber 100 is configured to perform a plurality of semiconductor processes on the wafer W to form a semiconductor structure SS on each wafer W. The measurement element 200 is configured to perform a measurement on each wafer W to determine the status of the wafer W.

[0096] In some embodiments, the processing chamber 100 fabricates a plurality of fin arrays in two layers on the wafer W. The measurement element 200 measures an overlay ratio between the fin arrays in the two layers of the top view of the wafer W, thereby generating a magnification representing a displacement between the fin arrays in the two layers.

[0097] In some embodiments, the measurement performed by the measurement element 200 is a pattern wafer geometry (PWG) measurement. In some embodiments, the measurement element 200 includes a memory that stores a lookup table 210. The lookup table 210 stores a correspondence between a magnification and a displacement. In some embodiments, each correspondence recorded in the lookup table 210 records a displacement and a magnification. For example, the measurement element 200 looks up the correspondence that includes the generated magnification, and then the measurement element 200 is able to know the displacement associated with the magnification in accordance with the correspondence in the lookup table 210. Thus, when the measurement element 200 obtains the magnification in accordance with the overlay ratio, the displacement can be obtained in accordance with the lookup table 210.

[0098] In some embodiments, the manufacturing system 10 determines the next process for the wafer W in accordance with the status of the wafer W. For example, the wafer W can be determined to be removed from the lot B, or can be determined to be processed by the next process.

[0099] Referring to Figure 2 . Figure 2 is a structural diagram illustrating a wafer W in accordance with some embodiments of the present disclosure. In some embodiments, the lot B includes more than one wafer W, and each wafer W undergoes the same semiconductor process and the same measurement.

[0100] In Figure 2 , the wafer W is a top view of the wafer W. An X-axis and a Y-axis are shown to represent the orientation of the wafer W. In some embodiments, the wafer W is a semiconductor wafer, for example, a silicon wafer. The wafer W includes a plurality of dies D. In some embodiments, the dies D are identical. The number and location of the dies D in the wafer W are shown for illustrative purposes as Figure 2 Various different numbers and locations of the dies D in the wafer W are within the scope of the present disclosure. For example, the wafer W can have other dies D disposed around the edge of the wafer W.

[0101] Referring to Figure 3 . Figure 3 is a structural block diagram illustrating a die D in accordance with some embodiments of the present disclosure. The die D is divided into a plurality of banks BA. In some embodiments, the banks BA have the same semiconductor structure SS after the semiconductor process is performed in the processing chamber 100. In some embodiments, the banks BA have the same semiconductor structure SS after the measurement is performed in the metrology tool 200. Figure 3 In , nine banks are shown in the die D, however, the present disclosure is not limited thereto.

[0102] In some embodiments, the semiconductor structure SS on the die D includes a plurality of fins configured as a plurality of fin arrays. In some embodiments, each edge of the bank BA is defined by a fin array in the semiconductor structure SS. In other words, the fins on the die D are grouped into a number of arrays, and each array represents a bank BA in the die D. In other words, each bank BA has a fin array that is separated from a fin array in another bank BA.

[0103] Referring to Figure 4 and Figure 5 . Figure 4 is a structural diagram illustrating a bank BA from a top view of the wafer W in accordance with some embodiments of the present disclosure. Figure 5 is a structural diagram illustrating a bank BA from a cross-sectional view of the wafer W in accordance with some embodiments of the present disclosure. In Figure 4In the diagram, block BA is drawn on the XY plane. Figure 5 In the diagram, block BA is drawn on the XZ plane.

[0104] like Figure 5 As shown, a cross-sectional view of wafer W reveals a semiconductor structure SS having a first layer L1 and a second layer L2. The first layer L1 is disposed on wafer W, and the second layer L2 is disposed on the first layer L1. The semiconductor structure SS also includes a first fin array A1 in the first layer L1 and a second fin array A2 in the second layer L2. The first fin array A1 includes a plurality of fins, labeled F11, F12 to F1N, and the second fin array A2 includes a plurality of fins, labeled F21, F22 to F2N. In some embodiments, the number of fins in the first fin array A1 is N, and the number of fins in the second fin array A2 is N. N is an integer. In other words, the first fin array A1 and the second fin array A2 include the same number of fins.

[0105] In some embodiments, a first fin F11 of the first fin array A1 corresponds to a first fin F21 of the second fin array A2. Similarly, a second fin F12 to an Nth fin F1N of the first fin array A1 corresponds to a second fin F12 to an Nth fin F2N of the second fin array A2, respectively. Figure 5 In the first fin array A2, the first fin F21 is disposed on and contacts the first fin F11 of the first fin array A1. Similarly, the second fins F22 to the Nth fin F2N of the second fin array A2 are disposed on and contacts the second fins F12 to the Nth fin of the first fin array A1, respectively.

[0106] In some embodiments, the first fins F11 to the Nth fin F1N of the first fin array A1 are respectively identical to the first fins F11 to the Nth fin F2N of the second fin array A2. The first fins F11 to the Nth fin F1N of the first fin array A1 overlap with the first fins F11 to the Nth fin F2N of the second fin array A2. Therefore, as... Figure 4 As shown, only the second fin array A2 can be seen from the top view of wafer W.

[0107] The first layer L1 and the second layer L2 are formed sequentially on the wafer W. In some embodiments, the first layer L1 is formed to have a planar upper surface, and the second layer L2 is formed on the planar upper surface of the first layer L1. However, in other embodiments, the first layer L1 and the wafer W undergo stress caused by the processes when the first fin array A1 is formed. For example, a thermal process can cause stress in the first layer L1 and the first fin array A1, and the stress can deform the first fin array A1 and the first layer L1. Because the materials of the first layer L1 and the first fin array A1 are different from the wafer W, a heterojunction is formed between the first layer L1 and the wafer W. The stress causes different strains in the different materials. Thus, due to the heterojunction, the first fin array A1 in the first layer L1 is deformed, and as shown in Figure 6 and Figure 7 the first layer L1 cannot have a planar upper surface. Thus, the second layer L2 cannot be formed on the planar upper surface of the first layer L1.

[0108] Reference is made to Figure 6 . Figure 6 is a structural diagram illustrating a block BA viewed from a cross-section of the wafer W according to some embodiments of the present disclosure. As shown in Figure 6 the first fin array A1 in the first layer L1 is deformed. In some embodiments, the first fin F11, the second fin F12, the (N-1)th fin F1(N-1), and the Nth fin F1N of the first fin array A1 are deformed compared to the first fin array A1 as shown in Figure 5 .

[0109] In some embodiments, the first fin array A1 is symmetric. The first fin F11 is symmetric to the Nth fin F1N, and the second fin F12 is symmetric to the (N-1)th fin F1(N-1). Thus, the following description will take the first fin F11 and the second fin F12 as examples, and the description of the (N-1)th fin and the Nth fin will not be repeated.

[0110] The fins of the first fin array A1 extend generally along the Z-axis direction from the wafer W. Due to the deformation, the stress deforms the edges of the first fin array A1. Portions of the first fin F11 and the second fin F12 are tilted away from the first fin array A1 (e.g., toward the negative Z-axis direction), and the first fin F11 is more deformed than the second fin F12. As shown in Figure 6 the first fin F11 and the second fin F12 are deformed, but the present disclosure is not limited thereto. In other embodiments, more than two fins on the edges of the first fin array A1 are deformed by the stress.

[0111] The first fins F21 and the second fins F22 correspond to the first fins F11 and the second fins F12. In Figure 6 , the stress deforms the first fins F11 and the second fins F12 to lower the respective upper surfaces of the first fins F11 and the second fins F12 than other fins of the first fin array A1 in the Z axis. Thus, when the second layer L2 and the second fin array A2 are formed on the deformed first fin array A1, the first fins F21 and the second fins F22 are extended deeper (towards the negative X axis direction) than other fins of the second fin array. Further, because of the deformation, the positions of the first fins F11 and the first fins F21 are not aligned. Similarly, because of the deformation, the positions of the second fins F12 and the second fins F22 are not aligned. Thus, a displacement dl, a displacement d2, a displacement s(N-1), and a displacement dN representing the deformation are shown in Figure 6 .

[0112] Please refer to Figure 7 . Figure 7 is a structural schematic diagram illustrating a block BA viewed from a cross section of the wafer W of some embodiments of the present disclosure. As shown in Figure 7 , the first fin array A1 in a first layer L1 is deformed. In some embodiments, the first fins F11 and the second fins F12 of the first fin array A1 are deformed compared to the first fins F11 and the second fins F12 as shown in Figure 5 .

[0113] The fins of the first fin array A1 extend from the wafer W substantially along the Z axis. Because of the deformation, the stress deforms the edges of the first fin array A1. The upper portions of the first fins F11 and the second fins F12 are tilted towards the first fin array A1 (e.g. towards the X axis direction), and the first fins F11 are more deformed than the second fins F12. As shown in Figure 7 , only the deformed first fins F11 and the second fins F12 are drawn, but the present disclosure is not limited thereto. In another embodiment, more than two fins on the edges of the first fin array A1 are deformed by the stress.

[0114] Similar to the embodiments in Figure 6 , in Figure 7In the example shown in FIG. 1, the upper surfaces of the first fins F11 and the second fins F12 are lower than the other fins of the first fin array Al in the Z-axis. When the second layer L2 and the second fin array A2 are formed on the deformed first fin array Al, the first fins F21 and the second fins F22 extend deeper (in the direction of the negative Z-axis) than the other fins of the second fin array A2. Furthermore, because of the deformation, the positions of the first fins F11 and the first fins F21 are not aligned. Similarly, because of the deformation, the positions of the second fins F12 and the second fins F22 are not aligned. Accordingly, the displacements dl, d2, d(N-1), and dN representing the deformation are shown in Figure 7 .

[0115] Please refer to Figure 8 . Figure 8 is a structural schematic diagram illustrating a block BA as viewed from a cross-section of the wafer W in some embodiments of the present disclosure. As described in Figure 6 , the positions of the first fins F11 and the first fins F21 are not aligned, and the positions of the second fins F21 and the second fins F22 are not aligned. Compared to the block BA as shown in Figure 6 , the side of the first fin F11 and the side of the second fin F12 do not overlap with the first fin F21 and the second fin F22, respectively. Accordingly, the sides of the first fin F11 and the second fin F12 can be seen from the top view of the wafer W as shown in Figure 4 . Figure 8

[0116] The displacement dl represents a length of the side of the first fin F11 that does not overlap with the first fin F21 along the X-axis, and the displacement d2 represents a length of the side of the second fin F12 that does not overlap with the second fin F22 along the X-axis. Similarly, the displacement dN represents a length of the side of the Nth fin F1N that does not overlap with the first fin F2N along the X-axis, and the displacement d(N-1) represents a length of the side of the (N-1)th fin F2(N-1) that does not overlap with the (N-1)th fin F2(N-1) along the X-axis. Furthermore, a width d represents a width of the fins in the first fin array Al and the second fin array A2. In some embodiments, the displacement dl is greater than the displacement d2, and the displacement dN is greater than the displacement D(N-1).

[0117] ​In some embodiments, the displacements dl, d2, d(N-1), and dN are approximately a few nanometers. However, in the prior art, the measurement apparatus cannot have a measurement resolution down to the nanometer level. Therefore, the displacements dl-dN cannot be directly measured by the measurement element 200. In contrast to the prior art, the present application uses the measurement element 200 to perform the PWG measurement, and the displacements dl-dN can be obtained by converting the measurement results of the PWG measurement. Details of the steps to obtain the displacements dl-dN are described below.

[0118] The measurement element 200 is configured to measure the overlap ratios of the first fin array Al and the second fin array A2 by performing the PWG measurement. In some embodiments, the measurement element 200 measures the overlap ratio Rl of the first fin Fl l and the first fin F21, the overlap ratio RN of the Nth fin FlN and the Nth fin F2N, and the center overlap ratio RA of the Ath fin FlA and the Ath fin F2A. When N is an odd number, A is equal to (N+l) / 2. When N is an even number, A is equal to N / 2. The overlap ratio Rl can be expressed as (d-dl) / d. Similarly, the overlap ratio RN can be expressed as (d-dN) / d. In some embodiments, the Ath fin FlA completely overlaps with the Ath fin F2A. Therefore, the center overlap ratio RA is approximately equal to 0. In some embodiments, the overlap ratio Rl is equal to the overlap ratio RN.

[0119] After obtaining the overlap ratios Rl, RN, and RA, the measurement element 200 obtains a magnification Ml associated with the displacement dl and a magnification MN associated with the displacement dN. The magnification Ml can be obtained by subtracting the overlap ratio Rl from the center overlap ratio RA, and the magnification MN is obtained by subtracting the overlap ratio RN from the center overlap ratio RA. In some embodiments, the magnification Ml is approximately equal to the magnification MN.

[0120] After obtaining the magnification Ml and the magnification MN, the measurement element 200 is able to obtain the displacement dl and the displacement dN by finding the corresponding relationship associated with the magnification Ml and the magnification MN in the lookup table 210. In some embodiments, the measurement element 200 is further configured to average the magnification Ml and the magnification MN to obtain an average magnification Mavg. The measurement element 200 finds a corresponding relationship associated with the average magnification Mavg in the lookup table 210, and further obtains an average displacement davg according to the corresponding relationship.

[0121] Measuring element 200 determines the state of wafer W based on displacement d1, displacement dN, and / or average displacement davg. When displacement d1, displacement dN, and / or average displacement davg exceed a critical value, measuring element 200 determines that the state of wafer W is a FAIL (Failure to Meet) state. In this case, a FAIL state indicates that the deformation of the first fin array A1 in the first layer L1 of wafer W exceeds the manufacturing tolerance, causing displacement d1, displacement dN, and / or average displacement davg to exceed the critical value. Therefore, wafer W will be removed from the batch of wafers B, and wafer W will not be processed in subsequent processes.

[0122] Conversely, when the displacements d1, dN, and average displacement davg do not exceed the critical values, the measuring element 200 determines that the state of wafer W is a pass state. In this case, the pass state indicates that the deformation of the first fin array A1 in the first layer L1 of wafer W is within the manufacturing tolerance, such that the displacements d1, dN, and average displacement davg do not exceed the critical values. Therefore, wafer W will remain in this batch of wafers B, and wafer W will be processed in subsequent processes.

[0123] Compared to Figure 4 The embodiments shown are in Figure 6 and Figure 8 In this embodiment, the position of the first fin F11 in the first layer L1 is deviated from its original position in the negative X-axis direction, and the position of the Nth fin F1N in the first layer L1 is also deviated from its original position in the X-axis direction. In this embodiment, the first fin array A1 in the first layer L1 may experience a tensile stress, and the edges of the first fin array A1 (e.g., the first fin F11 and the Nth fin F1N) extend outward from the first fin array A1.

[0124] Please refer to Figure 9 . Figure 9 This is a structural schematic diagram illustrating a cross-sectional view of the wafer W, representing some embodiments of this disclosure. Figure 7 The block BA is shown. (For example...) Figure 7 As stated, the positions of the first fin F11 and the first fin F21 are not aligned, and the positions of the second fin F12 and the second fin F22 are not aligned. Compared to... Figure 4 In the block BA shown, one side of the first fin F11 and one side of the second fin F12 do not overlap with the first fin F21 and the second fin F22, respectively. Therefore, the aforementioned sides of the first fin F11 and the second fin F12 can be seen from... Figure 9 The top of the wafer W shown in the figure can be seen.

[0125] Similar to Figure 8In the illustrated embodiment, displacement d1 represents the length by which the side of the first fin F11 does not overlap with the first fin F21 along the X-axis, and displacement d2 represents the length by which the side of the second fin F12 does not overlap with the second fin F22 along the X-axis. Similarly, displacement dN represents the length by which the side of the Nth fin F1N does not overlap with the second fin F2N along the X-axis, and displacement d(N-1) represents the length by which the side of the (N-1)th fin F1(N-1) does not overlap with the second fin F2(N-1) along the X-axis. Furthermore, a width d represents the width of the fins in the first fin array A1 and the second fin array A2. In some embodiments, displacement d1 is greater than displacement d2, and displacement dN is greater than displacement d(N-1).

[0126] In some embodiments, displacements d1, d2, d(N-1), and dN are approximately a few nanometers.

[0127] Compared to Figure 4 The embodiments shown are in Figure 7 and Figure 9 In this embodiment, the position of the first fin F11 in the first layer L1 deviates from its original position in the X-axis direction, and the position of the Nth fin F1N in the first layer L1 deviates from its original position in the negative X-axis direction. In this embodiment, the first fin array A1 in the first layer L1 may experience a compressive stress, and the edges of the first fin array A1 (e.g., the first fin F11 and the Nth fin F1N) are compressed inward to the center of the first fin array A1.

[0128] The measuring element 200 is configured to measure the overlap ratios R1, RN, and RA of the first fin array A1 and the second fin array A2 by performing PWG measurements. The measuring element 200 is also configured to obtain magnifications M1, MN, and / or average magnification Mavg based on the overlap ratios R1, RN, and RA, so as to obtain displacements d1, dN, and / or average displacement davg associated with the magnifications M1, MN, and Mavg according to lookup table 210. The steps described above are similar to those described below. Figure 6 and Figure 8 The steps described above will not be repeated here. Therefore, the details of the steps for displacement d1, displacement dN, and average displacement davg will not be repeated in this document.

[0129] Please refer to Figure 10 . Figure 10 This is a flowchart illustrating a method M10 for fabricating a semiconductor structure SS on a wafer W and performing patterned wafer geometry (PWG) measurements according to some embodiments of this disclosure. Method M10 includes steps S101, S102, S103, S104, S105, S106, and S107.

[0130] In step S101, a wafer W is received, and the wafer W has a plurality of dies D. In step S102, a plurality of semiconductor structures SS is formed in each die D. Each semiconductor structure SS includes a first fin array Al and a second fin array A2, and the second fin array A2 is disposed above the first fin array Al. In step S103, a PWG measurement is performed on the wafer W to obtain a displacement dl between a first fin Fl 1 of the first fin array Al and a first fin F21 of the second fin array A2. In step S104, a status of the wafer W is determined according to the displacement dl. In step S105, when the status of the wafer W is a fail status FAIL, the wafer W is removed from the lot of wafers B. In step S106, when the status of the wafer W is a pass status PASS, the wafer W is retained in the lot of wafers B. In step S107, a next process is performed on the wafer W, which has the pass status PASS in the lot of wafers B. In some embodiments, the next process is a lithography process. In other embodiments, the next process is an etching process.

[0131] Referring to Figure 11 . Figure 11 is a flow diagram illustrating steps S102 of some embodiments of the disclosure. Figure 10 Steps S102 include steps S111 and S112.

[0132] In step S111, the first fin array Al is formed in each block BA. In step S112, the second fin array A2 is formed on the first fin array Al.

[0133] Referring to Figure 12 . Figure 12 is a flow diagram illustrating steps S111 of some embodiments of the disclosure. Figure 11 Steps S111 include steps S121, S122, and S123. Referring to Figure 17 , Figure 18 and Figure 19 . Figures 17 to 19 is a structure diagram illustrating a semiconductor structure SS in different manufacturing steps of some embodiments of the disclosure.

[0134] In step S121, as shown in Figure 17 , a first layer L1 is formed on the wafer W. The first layer L1 can be deposited on the wafer W by performing chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition. In step S122, as shown in Figure 18As shown, the first layer L1 is etched to form the first fin array A1. In some embodiments, the fabrication technique for the first fin array A1 may include depositing material of the first fin array A1 into multiple etched vacancies in the first layer L1. In step S123, as... Figure 19 As shown, the first layer L1 is planarized to expose the upper surface of the first fin array A1.

[0135] Please refer to Figure 13 . Figure 13 This is a flowchart illustrating some implementations of this disclosure, for example. Figure 11 The step S112 is shown. Step S112 includes steps S131, S132, and S133. Please also refer to... Figure 20 , Figure 21 and Figure 5 . Figure 20 and Figure 21 This is a schematic diagram illustrating the semiconductor structure SS in different manufacturing steps of some embodiments of this disclosure.

[0136] In step S131, as Figure 20 As shown, the second layer L2 is formed on the first fin array A1. The second layer L2 can be deposited on the wafer W by performing chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods. In step S132, as... Figure 21 As shown, the second layer L2 is etched to form the second fin array A2. In some embodiments, the fabrication technique for the second fin array A2 may include depositing material of the second fin array A2 into multiple etched cavities in the second layer L2. In step S133, as... Figure 5 As shown, the second layer L2 is planarized to expose the upper surface of the second fin array A2.

[0137] Please refer to Figure 14 . Figure 14 This is a flowchart illustrating some implementations of this disclosure, for example. Figure 11 The step S103 is shown. Step S103 includes steps S141, S142, S143 and S144.

[0138] In step S141, the overlap ratio R1 of the first fin F11 of the first fin array A1 and the Nth fin F21 of the second fin array A2 is obtained. In step S142, the overlap ratio RN of the Nth fin F1N of the first fin array A1 and the Nth fin F2N of the second fin array A2 is obtained. In step S143, the center overlap ratio RA of the fin F1A of the first fin array A1 and the fin F2A of the second fin array A2 is obtained. In step S144, the displacement d1 is obtained based on the overlap ratios R1, RN, and RA.

[0139] Referring to Figure 15 . Figure 15 is a flowchart illustrating some embodiments of the present disclosure, such as Figure 14 Step S144 includes steps S151, S152, and S153.

[0140] In step S151, magnification M1 is obtained by subtracting overlap ratio R1 from center overlap ratio RA. In step S152, magnification MN is obtained by subtracting overlap ratio RN from center overlap ratio RA. In some embodiments, displacement dl is obtained according to magnifications M1 and MN.

[0141] Referring to Figure 16 . Figure 16 is a flowchart illustrating some embodiments of the present disclosure, such as Figure 15 Step S153 includes steps S161 and S162.

[0142] In step S161, average magnification Mavg is obtained by averaging magnifications M1 and MN. In step S162, displacement dl and / or average displacement davg is obtained from lookup table 210.

[0143] In some embodiments, step S161 is omitted from method M10. Average displacement davg is obtained by using magnification M1 to find a correspondence in lookup table 210. In some embodiments, magnification M1 is approximately equal to average magnification Mavg, and displacement dl is approximately equal to average displacement davg.

[0144] An embodiment of the present disclosure provides a method of manufacturing and measuring a plurality of semiconductor structures. The method includes the following steps: receiving a wafer, the wafer having a plurality of dies; forming the plurality of semiconductor structures in a plurality of blocks of each die, respectively, wherein each semiconductor structure has a first fin array and a second fin array, the second fin array being above the first fin array; performing a pattern wafer geometry measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and determining a status of the wafer according to the displacement.

[0145] Another embodiment of the disclosure provides a manufacturing and measurement system. The system includes a processing chamber; and a measurement element. The processing chamber is configured to perform a plurality of operations including: forming a first fin array in a block of a die of a wafer; and forming a second fin array on the first fin array. The measurement element is configured to perform a pattern wafer geometry measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array, and is further configured to determine a condition of the wafer as a function of the displacement.

[0146] While the disclosure and the best mode thereof have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes can be performed in a different order, and the processes described can be modified or omitted, or other processes can be added.

[0147] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized. Accordingly, the present claims are intended to cover all processes, machines, manufacture, compositions of matter, means, methods, or steps, substantially as set forth in the disclosure and including such alterations, modifications and changes in the process, machine, manufacture, composition of matter, means, methods, or steps that would be readily apparent to one of ordinary skill in the art and that are not expressly disclosed, but that include structures, materials, or components for accomplishing substantially the same function or achieving substantially the same result.

Claims

1. A system for manufacturing and measuring a semiconductor structure, comprising: a processing chamber; and a measurement element; wherein the processing chamber is configured to perform a plurality of operations, including: forming a first fin array in a block of a die of a wafer, wherein the first fin array has a plurality of fins including a first fin to an Nth fin separated from each other, wherein N is a positive integer; and forming a second fin array on the first fin array, wherein the second fin array has a plurality of fins including a first fin to an Nth fin separated from each other, wherein the plurality of fins of the first fin array and the plurality of fins of the second fin array are respectively aligned when the second fin array is overlaid on the first fin array; wherein the measurement element is configured to perform a pattern wafer geometry measurement on the wafer when a top of the first fin and the Nth fin of the first fin array is tilted away from the first fin array to obtain a displacement between the first fin of the first fin array and the first fin of the second fin array by a nanometer degree of the pattern wafer geometry, to obtain a displacement between the Nth fin of the first fin array and the Nth fin of the second fin array by the nanometer degree of the pattern wafer geometry, and further configured to determine a status of the wafer according to the displacement.

2. The system of claim 1, wherein the displacement is defined from a top view of the wafer.

3. The system of claim 1, wherein the measurement element is further configured to: measure a first overlap ratio of the first fin of the first fin array and the first fin of the second fin array; measure a second overlap ratio of the Nth fin of the first fin array and the Nth fin of the second fin array; and measure a center overlap ratio of an A th fin of the first fin array and an A th fin of the second fin array; wherein A is equal to (N+1) / 2 when N is an odd integer, and A is equal to N / 2 when N is an even integer.

4. The system of claim 3, wherein the measurement element is further configured to: obtain a first magnification by subtracting the first overlap ratio from the center overlap ratio; obtain a second magnification by subtracting the second overlap ratio from the center overlap ratio; and obtain the displacement according to the first magnification and the second magnification.

5. The system of claim 4, wherein the measurement element is further configured to: obtain an average magnification by averaging the first magnification and the second magnification; wherein the measurement element includes a lookup table configured to store a correspondence of the displacement and the average magnification, the measurement element is further configured to obtain the displacement according to the lookup table.

6. The system of claim 1, wherein the status of the die is determined to be a fail status when the displacement is greater than a threshold value, and the status of the die is determined to be a pass status when the displacement is not greater than the threshold value.

7. The system of claim 6, wherein the processing chamber is configured to remove the wafer from a batch of wafers when the status of the wafer is a fail status. ​ 8. The system of claim 6, wherein when the status of the wafer is a pass status, the processing chamber is configured to retain the wafer in a batch of wafers.

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