Wafer fixtures, wafer structures, and wafer fabrication methods

Abstract

A wafer fixture includes a bottom wall and an annular sidewall. The bottom wall has a bearing surface, and the annular sidewall is connected to the periphery of the bottom wall, including at least two steps. The two steps include a first step and a second step. The first step connects the bearing surface and the second step, and the first step protrudes towards the center of the bottom wall relative to the second step. The annular sidewall surrounds the center. Furthermore, a wafer structure and a wafer processing method are also mentioned. The wafer fixture, wafer structure, and wafer processing method of the present invention can avoid wafer deformation and damage and solve the problem of wafer incompatibility with equipment.

Description

Technical Field

[0001] This invention relates to a fixture, a structure including the fixture, and a processing method thereof, and more particularly to a wafer fixture, a wafer structure including the wafer fixture, and a wafer processing method thereof. Background Technology

[0002] Silicon carbide is very expensive, so thinning of silicon carbide wafers is crucial to saving costs by manufacturing multiple wafers. However, thinner silicon carbide wafers are prone to warping and deformation, leading to poor yields, and are also easily broken during transportation and processing. Furthermore, wafers of certain sizes (such as 6-inch wafers) may not conform to the specifications of subsequent process equipment (such as epitaxial wafers), resulting in wafer-equipment incompatibility issues. Summary of the Invention

[0003] This invention relates to a wafer fixture, wafer structure, and wafer processing method, which can avoid wafer deformation and damage and solve the problem of wafer incompatibility with the equipment.

[0004] According to an embodiment of the present invention, a wafer fixture includes a bottom wall and an annular sidewall. The bottom wall has a bearing surface, and the annular sidewall is connected to the periphery of the bottom wall, the annular sidewall including at least two steps. The two steps include a first step and a second step. The first step is connected between the bearing surface and the second step, and the first step protrudes toward the center of the bottom wall relative to the second step. The annular sidewall surrounds the center.

[0005] In a wafer fixture according to an embodiment of the present invention, an annular sidewall surrounds a receiving space on the bottom wall. The receiving space includes a first subspace and a second subspace. The first subspace corresponds to a first step, and the second subspace corresponds to a second step. The size of the second subspace in a first direction parallel to the protruding direction of the first step toward the center is greater than the size of the first subspace in the first direction.

[0006] In a wafer fixture according to an embodiment of the present invention, the dimension of the first subspace in a second direction perpendicular to the first direction is smaller than the thickness of the wafer, and the sum of the dimensions of the first subspace and the second subspace in the second direction is greater than or equal to the thickness of the wafer.

[0007] In the wafer fixture according to an embodiment of the present invention, the hardness of the bottom wall and the annular sidewall is less than the hardness of the wafer.

[0008] In the wafer fixture according to an embodiment of the present invention, the bearing surface includes a bottom surface and an inclined surface, the inclined surface being connected between the bottom surface and the first step and inclined to the bottom surface.

[0009] According to an embodiment of the present invention, a wafer structure includes a wafer fixture and a wafer. The wafer fixture includes a bottom wall and an annular sidewall. The bottom wall has a bearing surface. The annular sidewall is connected to the periphery of the bottom wall, wherein the annular sidewall includes at least two steps, the at least two steps including a first step and a second step, the first step being connected between the bearing surface and the second step, the first step protruding relative to the second step toward the center of the bottom wall, and the annular sidewall surrounding the center. The wafer is supported on the bearing surface, wherein the side edges of the first step and the second step face the wafer, and the periphery of the wafer contacts the side edge of the first step and is spaced apart from the side edge of the second step.

[0010] In the wafer structure according to an embodiment of the present invention, an annular sidewall surrounds a receiving space on the bottom wall. The receiving space includes a first subspace and a second subspace. The first subspace corresponds to a first step, and the second subspace corresponds to a second step. The size of the second subspace in a first direction parallel to the protruding direction of the first step toward the center is greater than the size of the first subspace in the first direction.

[0011] In the wafer structure according to an embodiment of the present invention, the dimension of the first subspace in the second direction perpendicular to the first direction is smaller than the thickness of the wafer, and the sum of the dimensions of the first subspace and the second subspace in the second direction is greater than or equal to the thickness of the wafer.

[0012] In the wafer structure according to an embodiment of the present invention, the hardness of the bottom wall and the annular sidewall is less than the hardness of the wafer.

[0013] In the wafer structure according to an embodiment of the present invention, the bearing surface includes a bottom surface and an inclined surface, the inclined surface being connected between the bottom surface and the first step and inclined to the bottom surface.

[0014] According to an embodiment of the present invention, a wafer fabrication method includes the following steps: Providing a wafer fixture, wherein the wafer fixture includes a bottom wall and an annular sidewall, the bottom wall having a bearing surface, and the annular sidewall including at least two steps, the at least two steps including a first step and a second step, the first step being connected between the bearing surface and the second step, the first step protruding toward the center of the bottom wall relative to the second step, and the annular sidewall surrounding the center. Bonding a wafer to the bearing surface, wherein the periphery of the wafer contacts the first step and is spaced from the second step. Epitaxially depositing the wafer. Separating the wafer from the wafer fixture.

[0015] In a wafer processing method according to an embodiment of the present invention, the step of bonding the wafer to a carrier surface includes bonding the wafer to the carrier surface by means of a hot pressing process or an oxide layer bonding process.

[0016] In a wafer processing method according to an embodiment of the present invention, the step of separating the wafer from the wafer fixture includes: cutting the wafer fixture to remove the second-stage portion and at least a portion of the first-stage portion, forming an adhesive layer on the epitaxial wafer, and removing a portion of the wafer and the wafer fixture by a grinding process or a laser process.

[0017] In a wafer fabrication method according to an embodiment of the present invention, the step of bonding the wafer to a carrier surface includes bonding the wafer to the carrier surface by means of an oxide layer bonding process, and the step of separating the wafer from a wafer fixture includes removing the oxide layer between the wafer and the wafer fixture. The above-described fabrication method further includes thinning the wafer after separating it from the wafer fixture.

[0018] In a wafer processing method according to an embodiment of the present invention, the step of separating the wafer from the wafer fixture includes separating a portion of the wafer from the wafer fixture by means of a laser process. The above-described processing method further includes removing another portion of the wafer remaining on the wafer fixture after separating a portion of the wafer from the wafer fixture.

[0019] Based on the above, the wafer fixture of the present invention provides a stable support for the wafer to prevent wafer warping and resulting poor yield, and to prevent wafer breakage during transport and processing. Furthermore, the first step of the annular sidewall protrudes towards the center of the bottom wall relative to the second step. This creates a gap between the wafer and the second step when the wafer is placed on the bottom wall and surrounded by the first step, acting as a buffer space to reduce the probability of wafer breakage due to impact. Additionally, during wafer epitaxy, this gap prevents the wafer and wafer fixture from connecting through the epitaxial layer after the epitaxial operation, thereby preventing difficulty in separating the wafer from the wafer fixture and / or edge breakage when separating from the wafer fixture. Moreover, the wafer fixture and the wafer together constitute a wafer structure, the size of which (i.e., the size of the wafer fixture, for example, 8 inches) is larger than the size of the wafer itself (for example, 6 inches). Therefore, even if the specifications of the process equipment (such as epitaxial wafer equipment) (e.g., the specifications corresponding to an 8-inch wafer) are incompatible with the size of the wafer itself, the wafer structure formed by the wafer fixture and the wafer can still be compatible with the specifications of the process equipment. Attached Figure Description

[0020] Figure 1 This is a cross-sectional schematic diagram of a wafer structure according to an embodiment of the present invention;

[0021] Figure 2 yes Figure 1 A top view of the wafer structure;

[0022] Figure 3 This is a partial schematic diagram of a wafer structure according to another embodiment of the present invention;

[0023] Figures 4A to 4GThis is a flowchart of a wafer fabrication method according to an embodiment of the present invention;

[0024] Figures 5A to 5B This diagram illustrates a partial flow of a wafer fabrication method according to another embodiment of the present invention. Detailed Implementation

[0025] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0026] Figure 1 This is a cross-sectional schematic diagram of a wafer structure according to an embodiment of the present invention. Figure 2 yes Figure 1 A top-view diagram of the wafer structure. Please refer to... Figure 1 and Figure 2 The wafer structure 100 of this embodiment includes a wafer fixture 110 and a wafer 120. The wafer fixture 110 includes a bottom wall 112 and an annular sidewall 114. The bottom wall 112 has a bearing surface 112a, which supports the wafer 120, and the wafer 120 is bonded to the bearing surface 112a. The annular sidewall 114 is connected to the periphery of the bottom wall 112 and surrounds the center C (indicated by) of the bottom wall 112. Figure 1 ).

[0027] The annular sidewall 114 includes at least two steps (shown as a first step 1141 and a second step 1142). The first step 1141 connects the bearing surface 112a of the bottom wall 112 and the second step 1142, and the first step 1141 protrudes towards the center C of the bottom wall 112 relative to the second step 1142. One side edge 1141a of the first step 1141 and one side edge 1142a of the second step 1142 face the wafer 120, and the periphery of the wafer 120 contacts the side edge 1141a of the first step 1141 and has a distance G from the side edge 1142a of the second step 1142. That is, the second step 1142 does not contact the wafer 120. In other embodiments, the annular sidewall 114 may include a greater number of steps, which is not a limitation of the present invention.

[0028] More specifically, the annular sidewall 114 surrounds a receiving space S on the bottom wall 112, the receiving space S including a first subspace S1 and a second subspace S2. The first subspace S1 corresponds to the first step 1141, the second subspace S2 corresponds to the second step 1142, and the dimension D3 of the second subspace S2 in a first direction V1 parallel to the projection direction of the first step 1141 toward the center C is greater than the dimension D2 of the first subspace S1 in the first direction V1. The dimension H1 of the first subspace S1 in a second direction V2 perpendicular to the first direction V1 is less than the thickness T of the wafer 120, and the sum of the dimensions of the first subspace S1 and the second subspace S2 in the second direction V2 (denoted as dimension H2) is greater than or equal to the thickness T of the wafer 120. Thus, the wafer 120 can be completely housed in the receiving space S, and a gap G can be formed between the wafer 120 and the second step 1142 as described above. In this embodiment, the difference between the dimension D3 of the second subspace S2 in the first direction V1 and the dimension D2 of the first subspace S1 in the first direction V1 is, for example, greater than or equal to 0.4 mm.

[0029] With the above configuration, the wafer fixture 110 stably supports the wafer 120, thus preventing the wafer 120 from warping and resulting in poor yield, and also preventing the wafer 120 from breaking during transportation and processing. Furthermore, the first step 1141 of the annular sidewall 114 protrudes towards the center C of the bottom wall 112 relative to the second step 1142, as described above, creating a gap G between the wafer 120 and the second step. This gap G acts as a buffer space, reducing the probability of the wafer 120 breaking due to impact.

[0030] On the other hand, in this embodiment, the wafer fixture 110 and the wafer 120 together constitute the wafer structure 100 as described above. The size D1 of this wafer structure 100 (i.e., the size of the wafer fixture 110, for example, 8 inches) is larger than the size D2 of the wafer 120 itself (for example, 6 inches). Accordingly, even if the specifications of the process equipment (such as an epitaxial wafer equipment) (such as the specifications corresponding to an 8-inch wafer) are incompatible with the size of the wafer itself, the wafer structure 100 constituted by the wafer fixture 110 and the wafer 120 can still be compatible with the specifications of the process equipment.

[0031] In this embodiment, the side 1141a of the first step 1141 is perpendicular to the first direction V1 (i.e., the direction in which the first step 1141 protrudes toward the center C) to properly surround and hold the wafer 120. Furthermore, the side 1142a of the second step 1142 is perpendicular to the first direction V1 (i.e., the direction in which the first step 1141 protrudes toward the center C) to prevent the side 1142a of the second step 1142 from tilting too close to the wafer 120.

[0032] Figure 3This is a partial schematic diagram of a wafer structure according to another embodiment of the present invention. Figure 3 The illustrated embodiments and Figure 1 The difference in the illustrated embodiment is that, Figure 3 In the wafer jig 110, the bearing surface 112a of the bottom wall 112 includes a bottom surface 112a1 and an inclined surface 112a2. The inclined surface 112a2 connects the bottom surface 112a1 and the first step 1141 and is inclined to the bottom surface 112a1. The inclined surface 112a2 is used to contact the outer edge of the bottom of the wafer 120, so that the bearing surface 112a fits more closely to the chamfer at the outer edge of the bottom of the wafer 120, thereby more stably supporting the wafer 120 and increasing the protective force of the wafer jig 110 on the wafer 120, preventing the wafer 120 from warping during subsequent epitaxy. In detail, the inclined surface 112a2 can be as follows: Figure 3 The diagram shows a flat surface. In other embodiments, the inclined surface 112a2 can also be formed as an arc surface to correspond to the chamfer shape at the bottom outer edge of the wafer 120, so that the inclined surface 112a2 can fit the wafer 120 more closely.

[0033] In this embodiment, the bottom wall 112 and the annular sidewall 114 of the wafer jig 110 are integrally formed. This allows the wafer jig 110 to be easily manufactured from the same base material, simplifying its manufacturing process. Furthermore, the integrally formed bottom wall 112 and annular sidewall 114 provide good structural strength.

[0034] In the foregoing embodiments, the wafer fixture 110 can be made of materials with lower hardness than the wafer 120, such as silicon or sapphire. This ensures that the hardness of the bottom wall 112 and the annular sidewall 114 is lower than that of the wafer 120, thus preventing the wafer 120 from being scratched by the bottom wall 112 and the annular sidewall 114. The processing method for the wafer 120 will be described below.

[0035] Figures 4A to 4G This is a flowchart of a wafer fabrication method according to an embodiment of the present invention. First, as... Figure 4A Provided as shown Figure 1 The wafer fixture 110 is shown. Next, as... Figure 4B As shown, wafer 120 is bonded to carrier surface 112a via an oxide layer bonding process, such that the periphery of wafer 120 contacts the first step portion 1141 and has a spacing G with the second step portion 1142. Since wafer 120 is bonded to carrier surface 112a via an oxide layer bonding process, an oxide bonding layer 50 is formed between wafer 120 and carrier surface 112a. Figure 1 For the sake of brevity, the oxide bonding layer 50 is omitted from the drawing. In other embodiments, the oxide bonding process may be replaced by a hot-pressing process or other processes.

[0036] Then, as Figure 4CThe epitaxial layer 60 is formed by epitaxy of wafer 120 using metal-organic chemical vapor deposition (MOCVD) or other suitable epitaxial processes. During the epitaxy of wafer 120, the spacing G between wafer 120 and the second-stage portion 1142 prevents wafer 120 from being connected to wafer fixture 110 through epitaxial layer 60 after the epitaxial operation is completed, thereby avoiding difficulty in separating wafer 120 from wafer fixture 110 and / or breakage of the edge of wafer 120 when separated from wafer fixture 110. The method of separating wafer 120 from wafer fixture 110 is as follows.

[0037] like Figure 4D The wafer cutting fixture 110 shown is used to remove the second-stage portion 1142 and the first-stage portion 1141, and as follows: Figure 4E As shown, an adhesive layer 70 is formed on the epitaxial wafer 120. This adhesive layer 70 is related to subsequent processes of the wafer 120, which will not be described in detail here. Next, as... Figures 4F to 4G The image shows the removal of a portion of wafer 120 and wafer fixture 110 using a laser process. Figure 4F The laser LB emitted by the laser source 10 is used to cut the wafer 120. This completes the separation of the wafer 120 from the wafer fixture 110. In other embodiments, a grinding process can be used instead of the laser process to remove portions of the wafer 120 and the wafer fixture 110.

[0038] In the above process, the wafer jig 110 is cut and / or ground and cannot be recycled. If the wafer jig 110 is to be recycled, instead of separating the wafer 120 from the wafer jig 110 by cutting and / or grinding the wafer jig 110, an acidic solution can be used to remove the oxide bonding layer 50 between the wafer 120 and the wafer jig 110, allowing the wafer 120 to detach from the wafer jig 110. Then, the wafer 120 can be thinned to the required thickness by grinding. Alternatively, the wafer 120 can be directly cut with a laser without cutting the wafer jig 110 to separate the wafer 120 from the wafer jig 110, as explained below.

[0039] Figures 5A to 5B This diagram illustrates a partial flow of a wafer fabrication method according to another embodiment of the present invention. During the process up to... Figure 4C After the process shown has been completed and the adhesive layer 70 has been formed, it can be used as follows: Figures 5A to 5B As shown, a portion of the wafer 120 is separated from the wafer fixture 110 using a laser process. Figure 5A The laser LB' emitted by the laser source 20 is used to cut the wafer 120 without cutting the wafer fixture 110. Then, the remaining portion of the wafer 120 and the oxide bonding layer 50 on the wafer fixture 110 are removed, so that the wafer fixture 110 can be recycled and reused.

[0040] In summary, the wafer fixture of the present invention provides a stable support for the wafer to prevent warping and resulting poor yield, and also to prevent wafer breakage during transport and processing. Furthermore, the first step of the annular sidewall protrudes towards the center of the bottom wall relative to the second step. This creates a gap between the wafer and the second step when the wafer is placed on the bottom wall and surrounded by the first step, acting as a buffer space to reduce the probability of wafer breakage due to impact. Additionally, during wafer epitaxy, this gap prevents the wafer and wafer fixture from connecting through the epitaxial layer after the epitaxial operation, thereby preventing difficulty in separating the wafer from the wafer fixture and / or edge breakage during separation. Moreover, the wafer fixture and the wafer together constitute a wafer structure, the size of which (i.e., the size of the wafer fixture, for example, 8 inches) is larger than the size of the wafer itself (for example, 6 inches). Therefore, even if the specifications of the process equipment (such as epitaxial wafer equipment) (e.g., the specifications corresponding to an 8-inch wafer) are incompatible with the size of the wafer itself, the wafer structure formed by the wafer fixture and the wafer can still be compatible with the specifications of the process equipment.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer fixture for carrying a wafer in an epitaxial wafer fabrication process, characterized in that, The wafer holder comprises: a bottom wall having a bearing surface; and a ring-shaped side wall connected to a periphery of the bottom wall, wherein the ring-shaped side wall comprises at least two steps, the at least two steps comprising a first step and a second step, the first step being connected between the bearing surface and the second step, the first step protruding toward a center of the bottom wall relative to the second step, the ring-shaped side wall surrounding the center, the bearing surface comprises a bottom surface and an inclined surface, the inclined surface being connected between the bottom surface and the first step and being inclined to the bottom surface.

2. The wafer jig of claim 1, wherein The ring-shaped side wall surrounds a receiving space on the bottom wall, the receiving space comprising a first sub-space and a second sub-space, the first sub-space corresponding to the first step, the second sub-space corresponding to the second step, a dimension of the second sub-space in a first direction parallel to a protruding direction of the first step toward the center is greater than a dimension of the first sub-space in the first direction.

3. The wafer jig of claim 2, wherein A dimension of the first sub-space in a second direction perpendicular to the first direction is less than a thickness of the wafer, a sum of the dimensions of the first sub-space and the second sub-space in the second direction is greater than or equal to the thickness of the wafer.

4. The wafer jig of claim 1, wherein A hardness of the bottom wall and the ring-shaped side wall is less than a hardness of the wafer.

5. A wafer structure, characterized by The wafer holder comprises: a wafer holder comprising: a bottom wall having a bearing surface; and a ring-shaped side wall connected to a periphery of the bottom wall, wherein the ring-shaped side wall comprises at least two steps, the at least two steps comprising a first step and a second step, the first step being connected between the bearing surface and the second step, the first step protruding toward a center of the bottom wall relative to the second step, the ring-shaped side wall surrounding the center; and a wafer carried on the bearing surface, wherein a side of the first step and a side of the second step face the wafer, a periphery of the wafer contacts the side of the first step and has a spacing from the side of the second step, the bearing surface comprises a bottom surface and an inclined surface, the inclined surface being connected between the bottom surface and the first step and being inclined to the bottom surface The wafer holder carries the wafer in a epitaxy process. The ring-shaped side wall surrounds a receiving space on the bottom wall, the receiving space comprising a first sub-space and a second sub-space, the first sub-space corresponding to the first step, the second sub-space corresponding to the second step, a dimension of the second sub-space in a first direction parallel to a protruding direction of the first step toward the center is greater than a dimension of the first sub-space in the first direction.

6. The wafer structure of claim 5, wherein, A dimension of the first sub-space in a second direction perpendicular to the first direction is less than a thickness of the wafer, a sum of the dimensions of the first sub-space and the second sub-space in the second direction is greater than or equal to the thickness of the wafer.

7. The wafer structure of claim 6, wherein, A hardness of the bottom wall and the ring-shaped side wall is less than a hardness of the wafer.

8. The wafer structure of claim 5, wherein, The wafer holder comprises:

9. A method of processing a wafer, characterized by, ​ A wafer holder is provided, wherein the wafer holder includes a bottom wall having a bearing surface and an annular sidewall including at least two steps, the at least two steps including a first step and a second step, the first step being connected between the bearing surface and the second step, the first step protruding toward a center of the bottom wall relative to the second step, the annular sidewall surrounding the center; bonding a wafer to the bearing surface, wherein a periphery of the wafer contacts the first step and has a spacing from the second step, the step of bonding the wafer to the bearing surface including bonding the wafer to the bearing surface by a thermal compression bonding process or an oxide layer bonding process; epitaxially growing the wafer; and separating the wafer from the wafer holder.

10. The wafer processing method according to claim 9, wherein The step of separating the wafer from the wafer holder includes: cutting the wafer holder to remove the second step and at least a portion of the first step; forming a glue layer on the epitaxially grown wafer; and removing a portion of the wafer and the wafer holder by a grinding process or a laser process.

11. The wafer processing method according to Claim 9, wherein The step of bonding the wafer to the bearing surface includes bonding the wafer to the bearing surface by an oxide layer bonding process, the step of separating the wafer from the wafer holder includes removing an oxide layer between the wafer and the wafer holder, the processing method further including: thinning the wafer after separating the wafer from the wafer holder.

12. The wafer processing method according to Claim 9, wherein The step of separating the wafer from the wafer holder includes separating a portion of the wafer from the wafer holder by a laser process, the processing method further including: removing another portion of the wafer remaining on the wafer holder after separating the portion of the wafer from the wafer holder.

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