Electrostatic discharge protection device

Abstract

This invention discloses an electrostatic discharge protection device, comprising first and second N-type well regions in a P-type semiconductor substrate. First N-type and P-type, second N-type and P-type, and third P-type doped regions are located in the first and second N-type well regions. First and second P-type well regions are located in the first N-type well region. Third N-type and fourth P-type, fourth N-type and fifth P-type doped regions are located in the first and second P-type well regions. The third P-type well region is located in the second N-type well region. Fifth N-type and sixth P-type doped regions are located in the third P-type well region. The first N-type and fifth P-type doped regions are directly electrically connected. The second N-type and sixth P-type doped regions are directly electrically connected. The first P-type and fifth N-type, second P-type and third N-type, and third P-type and fourth N-type and P-type doped regions are electrically connected to an input / output terminal, a power supply terminal, and a ground terminal.

Description

Technical Field

[0001] This invention relates to electrostatic discharge protection devices, and more particularly to the structure and layout of electrostatic discharge protection devices. Background Technology

[0002] Integrated circuits, including semiconductor components, are highly susceptible to damage from electrical overstress (EOS). EOS includes electrostatic discharge (ESD), transient conditions, latch-up, and incorrect polarity connections. ESD conditions are classified as overvoltage or overcurrent events. Electrostatic discharge (ESD) occurs when an object with accumulated charge comes into contact with an integrated circuit. The resulting current can damage the semiconductor components and circuitry. Therefore, protecting semiconductor components from ESD and other electrical overstress conditions is a critical issue. Furthermore, for high-speed, high-end chips, diodes or transistors alone cannot completely eliminate the ESD problem. Summary of the Invention

[0003] Some embodiments of the present invention provide an electrostatic discharge (ESD) protection device. The ESD protection device includes a P-type semiconductor substrate, a first N-type well region, a second N-type well region, a first N-type doped region, a first P-type doped region, a second N-type doped region, a second P-type doped region, a third N-type doped region, a third P-type doped region, a fourth N-type doped region, a fourth P-type doped region, a fifth N-type doped region, a fifth P-type doped region, a sixth P-type doped region, a first P-type well region, and a second P-type well region. A first N-type well region is located in a P-type semiconductor substrate; a first N-type doped region is located in the first N-type well region; a first P-type doped region is located in the first N-type well region, and is arranged side-by-side and spaced apart from the first N-type doped region; a second N-type well region is located in a P-type semiconductor substrate, and is arranged side-by-side and spaced apart from the first N-type well region; a second N-type doped region is located in the second N-type well region; a second P-type doped region is located in the second N-type well region; a third P-type doped region is located in the second N-type well region, wherein the second N-type doped region, the second P-type doped region, and the third P-type doped region are arranged side-by-side and spaced apart from each other; a first P-type well region is located in the first N-type well region; a third N-type doped region is located in the first P-type well region; a fourth P-type doped region is located in the first P-type well region, and is arranged side-by-side and spaced apart from the third N-type doped region; a second P-type well region is located in the first N-type well region. The fourth N-type doped region is located in the second P-type well region, and is arranged side-by-side with the fourth N-type doped region and spaced apart from it. The fifth P-type doped region is located in the second P-type well region, and is arranged side-by-side with the fourth N-type doped region and spaced apart from it. The third P-type well region is located in the second N-type well region. The fifth N-type doped region is located in the third P-type well region. The sixth P-type doped region is located in the third P-type well region, and is arranged side-by-side with the fifth N-type doped region and spaced apart from it. The first N-type doped region is directly electrically connected to the fifth P-type doped region. The second N-type doped region is directly electrically connected to the sixth P-type doped region. The first P-type doped region and the fifth N-type doped region are electrically connected to the input / output terminal. The second P-type doped region and the third N-type doped region are electrically connected to the power supply terminal. The third P-type doped region, the fourth N-type doped region, and the fourth P-type doped region are electrically connected to the ground terminal. Attached Figure Description

[0004] Figure 1 This is a top view schematic diagram of an electrostatic discharge protection device according to some embodiments of the present invention;

[0005] Figure 2A For along Figure 1 The diagram shows a cross-sectional view of the electrostatic discharge protection device according to some embodiments of the present invention along line A-A'.

[0006] Figure 2B For along Figure 1 The diagram shows a cross-sectional view of the electrostatic discharge protection device according to some embodiments of the present invention along line A-A'.

[0007] Figure 3A This is a schematic diagram of the equivalent discharge circuit where an electrostatic discharge event occurs at the input / output terminal (IO) and the ground terminal (VSS);

[0008] Figure 3B for Figure 2A A magnified view of a portion of the image, showing... Figure 3A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the electrostatic discharge protection device;

[0009] Figure 4A This is a schematic diagram of another equivalent discharge circuit where an electrostatic discharge event occurs at the input / output terminal (IO) and the power supply terminal (VCC);

[0010] Figure 4B for Figure 2A A magnified view of a portion of the image, showing... Figure 4A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the electrostatic discharge protection device;

[0011] Figure 5A This is a schematic diagram of the equivalent discharge circuit for an electrostatic discharge event occurring at the power supply terminal (VCC) and the input / output terminal (IO).

[0012] Figure 5B for Figure 2A A magnified view of a portion of the image, showing... Figure 5A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the electrostatic discharge protection device;

[0013] Figure 6A This is a schematic diagram of the equivalent discharge circuit where an electrostatic discharge event occurs at the ground terminal (VSS) and the input / output terminal (IO).

[0014] Figure 6B for Figure 2A A magnified view of a portion of the image, showing... Figure 6A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the electrostatic discharge protection device.

[0015] Symbol Explanation

[0016] 100, 110: Direction

[0017] 200: P-type semiconductor substrate

[0018] 210, 220: Conductors

[0019] 2DN, 2DP: Two parasitic diodes connected in series

[0020] 2DN-1: First parasitic diode

[0021] 2DN-2: Second parasitic diode

[0022] 2DP-1: Fourth Parasitic Diode

[0023] 2DP-2: Fifth Parasitic Diode

[0024] 2DP-3: Sixth Parasitic Diode

[0025] 500, 500A, 500B: Electrostatic discharge protection devices

[0026] 510, 520: Area

[0027] A-A' : Tangent

[0028] B1: First parasitic bipolar junction transistor (junction type)

[0029] B2: Second parasitic bipolar junction transistor

[0030] B3: Third parasitic bipolar junction transistor

[0031] B4: Fourth parasitic bipolar junction transistor

[0032] B5: Fifth parasitic bipolar junction transistor

[0033] B6: Sixth parasitic bipolar junction transistor

[0034] B7: Seventh Parasitic Bipolar Junction Transistor

[0035] DNW1: First type N deep well region

[0036] DNW2: Second type N deep well region

[0037] DNW1E,DNW2E,NW1E,NW2E: Boundaries

[0038] HDNW, HPW, HNW: Depth

[0039] IO: Input / Output Terminal

[0040] N1: First N-type doped region

[0041] N2: Second N-type doped region

[0042] N3: Third N-type doped region

[0043] N4: Fourth N-type doped region

[0044] N5: Fifth N-type doped region

[0045] NW1: First N-type well region

[0046] NW2: Second N-type well region

[0047] NW1b, NW2b, PW1b, PW2b, PW3b: bottom surface

[0048] P1: First P-type doped region

[0049] P2: Second P-type doped region

[0050] P3: Third P-type doped region

[0051] P4: Fourth P-type doped region

[0052] P5: Fifth P-type doped region

[0053] P6: Sixth P-type doped region

[0054] PW1: First P-type well region

[0055] PW2: Second P-type well region

[0056] PW3: Third P-type well region

[0057] PH1, PH2, PH2-1, PH2-2, PH3, PH4: Current paths

[0058] SCR-1: First Parasitic Semiconductor Controlled Rectifier

[0059] SCR-2: Second Parasitic Semiconductor Controlled Rectifier

[0060] SCR-3: Third Parasitic Semiconductor Controlled Rectifier

[0061] SCR-4: Fourth Parasitic Semiconductor Controlled Rectifier

[0062] VCC: Power supply end

[0063] VSS: Grounding terminal Detailed Implementation

[0064] The invention is described more fully below with reference to the accompanying drawings of embodiments thereof. However, the invention may be implemented in various different ways and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals denote the same or similar elements in the drawings.

[0065] Figure 1 This is a top view schematic diagram of an electrostatic discharge protection device 500 (including electrostatic discharge protection devices 500A and 500B) according to some embodiments of the present invention. Figures 2A-2B For along Figure 1The diagram shows a cross-sectional view of the electrostatic discharge protection device 500A according to some embodiments of the present invention along line A-A'. The electrostatic discharge protection device 500 is electrically connected between the input / output terminal (IO), ground terminal (VSS), and power supply terminal (VCC) of the system to prevent electrostatic discharge (ESD) current from flowing through the protected circuit. Furthermore, the electrostatic discharge protection device 500 of the present invention is suitable for systems with an operating voltage less than 1.0 V (the voltage difference between the high-level endpoint and the low-level endpoint in the system is less than 1.0 V). The electrostatic discharge protection device 500A includes a P-type semiconductor substrate 200, and a first N-type well region NW1, a second N-type well region NW2, a first P-type well region PW1, a second P-type well region PW2, and a third P-type well region PW3 located in the P-type semiconductor substrate 200. Each of these well regions includes at least one pair of heavily doped regions with opposite conductivity types. Furthermore, the second N-type well region NW2 has one more P-type heavily doped region than the number of N-type heavily doped regions. For example, the first N-type well region NW1 includes a first N-type doped region N1 and a first P-type doped region P1; the second N-type well region NW2 includes a second N-type doped region N2, a second P-type doped region P2, and a third P-type doped region P3; the first P-type well region PW1 includes a third N-type doped region N3 and a fourth P-type doped region P4; the second P-type well region PW2 includes a fourth N-type doped region N4 and a fifth P-type doped region P5; and the third P-type well region PW3 includes a fifth N-type doped region N5 and a sixth P-type doped region P6. For illustration, Figure 1 Only the above components are shown; the remaining components can be found in [the following locations]. Figure 2A , Figure 2B A cross-sectional schematic diagram, which along Figure 1 The tangent AA is intercepted, and the tangent AA is actually parallel to the direction 100.

[0066] like Figure 1 , Figure 2A As shown, the first N-type well region NW1 and the second N-type well region NW2 are both located in adjacent regions 510 and 520 of the P-type semiconductor substrate 200, and are arranged side by side and spaced apart from each other along direction 100. The first N-type doped region N1 and the first P-type doped region P1 located in the first N-type well region NW1 extend along direction 110 (e.g., in a long strip shape), and are arranged side by side and spaced apart from each other along direction 100. In this embodiment, the first N-type doped region N1 is located in the peripheral region of the first N-type well region NW1 away from the second N-type well region NW2, and the first P-type doped region P1 is located close to the middle region of the first N-type well region NW1. However, the positional relationship between the first N-type doped region N1 and the first P-type doped region P1 described above is not intended to limit the present invention.

[0067] like Figure 1 , Figure 2AAs shown, the second N-type doped region N2, the second P-type doped region P2, and the third P-type doped region P3 located in the second N-type well region NW2 all extend along direction 110 (e.g., in a long strip shape) and are arranged side-by-side and spaced apart from each other along direction 100. Specifically, the second N-type doped region N2 and the second P-type doped region P2 are located in the peripheral region of the second N-type well region NW2 close to the first N-type well region NW1, while the third P-type doped region P3 is located in the peripheral region of the second N-type well region NW2 away from the first N-type well region NW1. Furthermore, the second N-type doped region N2 and the third P-type doped region P3 are located on opposite sides of the second P-type doped region P2 that are substantially parallel to direction 110, and are spaced apart from the second P-type doped region P2 along direction 100.

[0068] like Figure 1 , Figure 2A As shown, the first P-type well region PW1 and the second P-type well region PW2 of the electrostatic discharge protection device 500A are both located in the first N-type well region NW1, extending along direction 110 and side by side along direction 100. In... Figure 1 In the top view shown, both the first P-type well region PW1 and the second P-type well region PW2 are surrounded by the first N-type well region NW1. Figures 2A-2B In the cross-sectional view shown, the depth HNW of the first N-type well region NW1 is greater than the depth HPW of the first P-type well region PW1 and the second P-type well region PW2. In some embodiments, the first P-type well region PW1 is located between the first N-type doped region N1 and the first P-type doped region P1 along direction 100. The second P-type well region PW2 is located in the peripheral region of the first N-type well region NW1, close to the second N-type well region NW2. Furthermore, the first P-type well region PW1 and the second P-type well region PW2 are located on opposite sides of the first P-type doped region P1, substantially parallel to direction 110, and are spaced apart from the first P-type doped region P1 along direction 100.

[0069] like Figure 1 , Figure 2A As shown, the third N-type doped region N3 and the fourth P-type doped region P4, located in the first P-type well region PW1, both extend along direction 110 (e.g., in a long strip shape) and are arranged side-by-side and spaced apart from each other along direction 100. Specifically, the third N-type doped region N3 is located along direction 100 between the first P-type doped region P1 and the fourth P-type doped region P4. The fourth P-type doped region P4 is located along direction 100 between the first N-type doped region N1 and the third N-type doped region N3.

[0070] like Figure 1 , Figure 2AAs shown, the fourth N-type doped region N4 and the fifth P-type doped region P5, located in the second P-type well region PW2, both extend along direction 110 (e.g., in a long strip shape) and are arranged side by side and spaced apart from each other along direction 100. In detail, the fourth N-type doped region N4 is located along direction 100 between the first P-type doped region P1 and the fifth P-type doped region P5.

[0071] like Figure 1 , Figure 2A As shown, the third P-type well region PW3 of the electrostatic discharge protection device 500A is located in the second N-type well region NW2 and extends along direction 110. In some embodiments, the second P-type doped region P2 and the third P-type doped region P3 are located on opposite sides of the third P-type well region PW3 that are substantially parallel to direction 110, and are spaced apart from the third P-type well region PW3 along direction 100.

[0072] like Figure 1 , Figure 2A As shown, the fifth N-type doped region N5 and the sixth P-type doped region P6, located in the third P-type well region PW3, both extend along direction 110 (e.g., in a long strip shape) and are arranged side-by-side and spaced apart from each other along direction 100. Specifically, the fifth N-type doped region N5 is located along direction 100 between the second P-type doped region P2 and the sixth P-type doped region P6. The sixth P-type doped region P6 is located along direction 100 between the fifth N-type doped region N5 and the third P-type doped region P3.

[0073] like Figure 2A As shown, in some embodiments, the first N-type doped region N1 in the first N-type well region NW1 is directly electrically connected to the fifth P-type doped region P5 in the second P-type well region PW2 via wire 210. Additionally, the first P-type doped region P1 in the first N-type well region NW1 is electrically connected to the input / output terminal IO. The third N-type doped region N3 in the first P-type well region PW1 is electrically connected to the power supply terminal VCC. The fourth N-type doped region N4 in the second P-type well region PW2 and the fourth P-type doped region P4 in the first P-type well region PW1 are electrically connected to the ground terminal VSS. In some embodiments, the second N-type doped region N2 in the second N-type well region NW2 is directly electrically connected to the sixth P-type doped region P6 in the third P-type well region PW3 via wire 220. The second P-type doped region P2 in the second N-type well region NW2 is electrically connected to the power supply terminal VCC. The third P-type doped region P3 in the second N-type well region NW2 is electrically connected to the ground terminal VSS. The fifth N-type doped region N5 in the third P-type well region PW3 is electrically connected to the input / output terminal IO.

[0074] In some embodiments, the N-type well region and the surrounding P-type well region may have the same depth, and the bottoms of the N-type well regions may be electrically connected to each other using N-type deep well regions (DNW). Figure 2B For along Figure 1The diagram shows a cross-sectional view of the electrostatic discharge protection device 500B along line A-A', representing some embodiments of the present invention. Compared to the electrostatic discharge protection device 500A, the first N-type well region NW1, the second N-type well region NW2, the first P-type well region PW1, the second P-type well region PW2, and the third P-type well region PW3 of the electrostatic discharge protection device 500B have the same depth HPW. The electrostatic discharge protection device 500B also includes a first N-type deep well region DNW1 and a second N-type deep well region DNW2. In some embodiments, the first N-type deep well region DNW1 is located below the first N-type well region NW1, the first P-type well region PW1, and the second P-type well region PW2. In some embodiments, the depth HDNW of the first N-type deep well region DNW1 is greater than the depth HPW of the first N-type well region NW1, the second N-type well region NW2, the first P-type well region PW1, the second P-type well region PW2, and the third P-type well region PW3. The first N-type deep well region DNW1 is in contact with the bottom surfaces NW1b, PW1b, and PW2b of the first N-type well region NW1, the first P-type well region PW1, and the second P-type well region PW2. Figure 2B In the cross-sectional view shown, the boundary DNW1E of the first N-type deep well region DNW1 is aligned with the boundary NW1E of the first N-type well region NW1.

[0075] like Figure 2B As shown, the second N-type deep well region DNW2 of the electrostatic discharge protection device 500B is located below the second N-type deep well region NW2 and the third P-type deep well region PW3, and is spaced apart from the first N-type deep well region DNW1. In some embodiments, the first N-type deep well region DNW1 and the second N-type deep well region DNW2 have the same depth HDNW. The second N-type deep well region DNW2 is in contact with the bottom surfaces NW2b and PW3b of the second N-type deep well region NW2 and the third P-type deep well region PW3. Figure 2B In the cross-sectional view shown, the boundary DNW2E of the second N-type deep well region DNW2 is aligned with the boundary NW2E of the second N-type well region NW2.

[0076] The following describes the equivalent circuit and current discharge path triggered when an electrostatic discharge event occurs at the input / output terminal IO, the power supply terminal VCC, or the ground terminal VSS, using electrostatic discharge protection device 500A as an example. In some embodiments, the equivalent circuit and current discharge path between different terminals of electrostatic discharge protection device 500B are the same as those of electrostatic discharge protection device 500A, and therefore will not be described again.

[0077] Figure 3A This indicates the equivalent discharge circuit where an electrostatic discharge event occurs between the input / output terminal IO and the ground terminal VSS. Figure 3B for Figure 2A A magnified view of region 510, which shows Figure 3A Parasitic elements in the equivalent circuit Figure 2AA schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 3A , Figure 3B As shown, the equivalent discharge circuit for an electrostatic discharge event occurring between the input / output terminal IO and the ground terminal VSS includes a first parasitic diode 2DN-1 composed of a first P-type doped region P1 and a first N-type well region NW1, and a second parasitic diode 2DN-2 composed of a fifth P-type doped region P5, a second P-type well region PW2, and a fourth N-type doped region N4. The first parasitic diode 2DN-1 is connected in series with the second parasitic diode 2DN-2, and is labeled as two parasitic diodes 2DN connected in series. The equivalent circuit also includes a first parasitic bipolar junction transistor (BJT) B1 (e.g., a parasitic PNP BJT) composed of the first P-type doped region P1, the first N-type well region NW1, and the second P-type well region PW2. The emitter, base, and collector of the first parasitic bipolar junction transistor B1 are respectively composed of the first P-type doped region P1, the first N-type well region NW1, and the second P-type well region PW2. Furthermore, the equivalent circuit described above also includes a second parasitic bipolar junction transistor B2 (e.g., a parasitic NPNBJT) composed of a fourth N-type doped region N4, a second P-type well region PW2, and a first N-type well region NW1. The emitter, base, and collector of the second parasitic bipolar junction transistor B2 are respectively composed of the fourth N-type doped region N4, the second P-type well region PW2, and the first N-type well region NW1. The base (first N-type well region NW1) of the first parasitic bipolar junction transistor B1 is electrically connected (shared) with the collector (first N-type well region NW1) of the second parasitic bipolar junction transistor B2, and the base (second P-type well region PW2) of the second parasitic bipolar junction transistor B2 is electrically connected with the collector (second P-type well region PW2) of the first parasitic bipolar junction transistor B1, thereby forming a first parasitic semiconductor controlled rectifier SCR-1. Furthermore, the base (first N-type well region NW1) of the first parasitic bipolar junction transistor B1 is electrically connected to the negative terminal of the first parasitic diode 2DN-1. The base (second P-type well region PW2) of the second parasitic bipolar junction transistor B2 is electrically connected to the positive terminal of the second parasitic diode 2DN-2.

[0078] When an electrostatic discharge (ESD) event occurs between the input / output terminal IO and the ground terminal VSS, the high pulse received by the input / output terminal IO will apply a forward bias voltage to the first parasitic diode 2DN-1 and the second parasitic diode 2DN-2 connected in series through the wire 210, triggering the two parasitic diodes to conduct (in a slightly conducting state), forming a current path PH1 from the input / output terminal IO through the first parasitic diode 2DN-1, the wire 210 and the second parasitic diode 2DN-2 and to the ground terminal VSS (the end point of the ESD event, or the receiving end of the ESD), allowing a small (partial) ESD current to pass through. Since the first parasitic diode 2DN-1 is also a parasitic diode formed by the emitter (first P-type doped region P1)-base (first N-type well region NW1) junction of the first parasitic bipolar junction transistor B1, and the second parasitic diode 2DN-2 is also a parasitic diode formed by the base (second P-type well region PW2)-emitter (fourth N-type doped region N4) junction of the second parasitic bipolar junction transistor B2, when the first parasitic diode 2DN-1 and the second parasitic diode 2DN-2 (two parasitic diodes 2DN connected in series) are slightly turned on, the first parasitic bipolar junction transistor B1 and the second parasitic bipolar junction transistor B2 will be triggered to turn on together. This will trigger the highly efficient first parasitic semiconductor controlled rectifier SCR-1 to turn on, releasing most of the electrostatic discharge current from the input / output terminal IO to the ground terminal VSS, thus preventing the electrostatic discharge current from flowing through the protected circuit.

[0079] Figure 4A This demonstrates an alternative equivalent discharge circuit where an electrostatic discharge event occurs between the input / output (IO) terminal and the power supply terminal (VCC). Figure 4B for Figure 2A A magnified view of a portion of the image, showing... Figure 4A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 4A , Figure 4BAs shown, the first parasitic diode 2DN-1 is connected in series with the second parasitic diode 2DN-2, and is also labeled as two parasitic diodes 2DN connected in series. The equivalent circuit above also includes a third parasitic bipolar junction transistor B3 (e.g., a parasitic NPN BJT) composed of a third N-type doped region N3, a first P-type well region PW1, and a first N-type well region NW1. The emitter, base, and collector of the third parasitic bipolar junction transistor B3 are respectively composed of the third N-type doped region N3, the first P-type well region PW1, and the first N-type well region NW1. The equivalent circuit above also includes a fourth parasitic bipolar junction transistor B4 (e.g., a parasitic PNPBJT) composed of a first P-type doped region P1, a first N-type well region NW1, and a first P-type well region PW1. The emitter, base, and collector of the fourth parasitic bipolar junction transistor B4 are respectively composed of a first P-type doped region P1, a first N-type well region NW1, and a first P-type well region PW1. Furthermore, the base (first P-type well region PW1) of the third parasitic bipolar junction transistor B3 is electrically connected (shared) with the collector (first P-type well region PW1) of the fourth parasitic bipolar junction transistor B4, and the base (first N-type well region NW1) of the fourth parasitic bipolar junction transistor B4 is electrically connected with one collector (first N-type well region NW1) of the third parasitic bipolar junction transistor B3, thus forming the second parasitic semiconductor controlled rectifier SCR-2. In addition, the base (first N-type well region NW1) of the fourth parasitic bipolar junction transistor B4 is electrically connected to the cathode of the first parasitic diode 2DN-1 and the anode of the second parasitic diode 2DN-2 via wire 210.

[0080] When an electrostatic discharge (ESD) event occurs between the input / output terminal IO and the power supply terminal VCC, the high pulse received by the input / output terminal IO will apply a forward bias voltage to the first parasitic diode 2DN-1 and the second parasitic diode 2DN-2 connected in series through the wire 210, thereby triggering the two parasitic diodes to conduct (in a slightly conducting state), forming a current path PH2-1 from the input / output terminal IO through the first parasitic diode 2DN-1, the wire 210 and the second parasitic diode 2DN-2 and to the ground terminal VSS. Because the small conducting current of the first parasitic diode 2DN-1 and the second parasitic diode 2DN-2 (i.e., the two parasitic diodes 2DN connected in series) will be connected to the base of the third parasitic bipolar junction transistor B3 through the common wire 210 of the ground terminal VSS, a current path PH2-2 will be formed that flows through the base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the third parasitic bipolar junction transistor B3 and to the power supply terminal VCC (the end point of the electrostatic discharge event, or the receiving end of the electrostatic discharge). The above current paths PH2-1 and PH2-2 form the current path PH2 from the input / output terminal IO to the power supply terminal VCC, allowing a small (partial) electrostatic discharge current to pass through. When the first parasitic diode 2DN-1 and the second parasitic diode 2DN-2 (i.e., two parasitic diodes 2DN connected in series) are slightly turned on, a forward bias voltage is also applied to the base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the third parasitic bipolar junction transistor B3 and the emitter (first P-type doped region P1)-base (first N-type well region NW1) junction of the fourth parasitic bipolar junction transistor B4. This causes the third parasitic bipolar junction transistor B3 and the fourth parasitic bipolar junction transistor B4 to be triggered and turned on together. This triggers the high-efficiency second parasitic semiconductor controlled rectifier SCR-2 to be turned on, releasing most of the electrostatic discharge current from the input / output terminal IO to the power supply terminal VCC, so as to prevent the electrostatic discharge current from flowing through the protected circuit.

[0081] Figure 5A This indicates that the electrostatic discharge event occurred in the equivalent discharge circuit between the power supply terminal VCC and the input / output terminal IO. Figure 5B for Figure 2A A magnified view of a portion of the image, showing... Figure 5A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 5A , Figure 5BAs shown, the equivalent discharge circuit for an electrostatic discharge event occurring between the power supply terminal VCC and the input / output terminal IO includes a fourth parasitic diode 2DP-1 composed of a second P-type doped region P2 and a second N-type well region NW2, and a fifth parasitic diode 2DP-2 composed of a sixth P-type doped region P6, a third P-type well region PW3, and a fifth N-type doped region N5. The fourth parasitic diode 2DP-1 is connected in series with the fifth parasitic diode 2DP-2, and is labeled as two parasitic diodes 2DP connected in series. The equivalent circuit also includes a fifth parasitic bipolar junction transistor B5 (e.g., a parasitic PNP BJT) composed of a second P-type doped region P2, a second N-type well region NW2, and a third P-type well region PW3. The emitter, base, and collector of the fifth parasitic bipolar junction transistor B5 are respectively composed of a second P-type doped region P2, a second N-type well region NW2, and a third P-type well region PW3. The equivalent circuit described above also includes a sixth parasitic bipolar junction transistor (BJT) B6 (e.g., an NPN BJT) composed of a fifth N-type doped region N5, a third P-type well region PW3, and a second N-type well region NW2. The emitter, base, and collector of the sixth parasitic bipolar junction transistor B6 are respectively composed of the fifth N-type doped region N5, the third P-type well region PW3, and the second N-type well region NW2. Furthermore, the base (second N-type well region NW2) of the fifth parasitic bipolar junction transistor B5 is electrically connected to the collector (second N-type well region NW2) of the sixth parasitic bipolar junction transistor B6, and the base (third P-type well region PW3) of the sixth parasitic bipolar junction transistor B6 is electrically connected (shared) to the collector B5 (third P-type well region PW3) of the fifth parasitic bipolar junction transistor, thus forming a third parasitic semiconductor controlled rectifier SCR-3. In addition, the base (second N-type well region NW2) of the fifth parasitic bipolar junction transistor B5 is electrically connected to the negative terminal of the fourth parasitic diode 2DP-1, and the base (third P-type well region PW3) of the sixth parasitic bipolar junction transistor B6 is electrically connected to the positive terminal of the fifth parasitic diode 2DP-2.

[0082] When an electrostatic discharge (ESD) event occurs between the power supply terminal VCC and the input / output terminal IO, the high pulse received by the power supply terminal VCC will apply a forward bias voltage to the fourth parasitic diode 2DP-1 and the fifth parasitic diode 2DP-2 connected in series through the wire 220, thereby triggering the two parasitic diodes (i.e., the two parasitic diodes 2DP connected in series) to conduct (in a slightly conducting state), forming a current path PH3 from the power supply terminal VCC through the fourth parasitic diode 2DP-1, the wire 220 and the fifth parasitic diode 2DP-2 and flowing to the input / output terminal IO (receiving low level), allowing a small (partial) electrostatic discharge current to pass through. Since the fourth parasitic diode 2DP-1 is also a parasitic diode formed by the emitter (second P-type doped region P2)-base (second N-type well region NW2) junction of the fifth parasitic bipolar junction transistor B5, and the fifth parasitic diode 2DP-2 is also a parasitic diode formed by the base (third P-type well region PW3)-emitter (fifth N-type doped region N5) junction of the sixth parasitic bipolar junction transistor B6, when the fourth parasitic diode 2DP-1 and the fifth parasitic diode 2DP-2 (i.e., the two parasitic diodes 2DP connected in series) are slightly turned on, the fifth parasitic bipolar junction transistor B5 and the sixth parasitic bipolar junction transistor B6 will also be triggered to turn on, thereby triggering the third parasitic semiconductor controlled rectifier SCR-3 to turn on, releasing most of the electrostatic discharge current from the power supply terminal VCC to the input / output terminal IO, thus preventing the electrostatic discharge current from flowing through the protected circuit.

[0083] Figure 6A This indicates the equivalent discharge circuit where an electrostatic discharge event occurs between the ground terminal VSS and the input / output terminal IO. Figure 6B for Figure 2A A magnified view of a portion of the image, showing... Figure 6A Parasitic elements in the equivalent circuit Figure 2A A schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 6A , Figure 6BAs shown, in addition to the fifth parasitic diode 2DP-2 and the sixth parasitic bipolar junction transistor B6 (e.g., a parasitic NPN BJT), the equivalent discharge circuit where an electrostatic discharge event occurs between the ground terminal VSS and the input / output terminal IO also includes the sixth parasitic diode 2DP-3, which is composed of the third P-type doped region P3 and the second N-type well region NW2. The fifth parasitic diode 2DP-2 is connected in series with the sixth parasitic diode 2DP-3, and is also labeled as two parasitic diodes 2DP connected in series. The above equivalent circuit also includes the seventh parasitic bipolar junction transistor B7 (e.g., a parasitic PNP BJT) composed of the third P-type doped region P3, the second N-type well region NW2, and the third P-type well region PW3. The emitter, base, and collector of the seventh parasitic bipolar junction transistor B7 are composed of the third P-type doped region P3, the second N-type well region NW2, and the third P-type well region PW3, respectively. Furthermore, the base (third P-type well region PW3) of the sixth parasitic bipolar junction transistor B6 is electrically connected (shared) with the collector (third P-type well region PW3) of the seventh parasitic bipolar junction transistor B7, and the base (second N-type well region NW2) of the seventh parasitic bipolar junction transistor B7 is electrically connected with the collector (second N-type well region NW2) of the sixth parasitic bipolar junction transistor B6, thus forming the fourth parasitic semiconductor controlled rectifier SCR-4. In addition, the base (second N-type well region NW2) of the seventh parasitic bipolar junction transistor B7 is electrically connected with the negative terminal of the sixth parasitic diode 2DP-3, and the base (third P-type well region PW3) of the sixth parasitic bipolar junction transistor B6 is electrically connected with the positive terminal of the fifth parasitic diode 2DP-2.

[0084] When an electrostatic discharge (ESD) event occurs between the ground terminal VSS and the input / output terminal IO, the high pulse received at the ground terminal VSS applies a forward bias voltage to the sixth parasitic diode 2DP-3 and the fifth parasitic diode 2DP-2 connected in series via wire 220 (i.e., two parasitic diodes 2DP connected in series), triggering both parasitic diodes to conduct. This forms a current path PH4 that flows from the ground terminal VSS through the sixth parasitic diode 2DP-3, wire 220, and the fifth parasitic diode 2DP-2 to the input / output terminal IO (the end point of the ESD event, or the receiving end of the ESD), allowing a small (partial) ESD current to pass through. As mentioned earlier, the fifth parasitic diode 2DP-2 is also a parasitic diode formed by the base (third P-type well region PW3)-emitter (fifth N-type doped region N5) junction of the sixth parasitic bipolar junction transistor B6. Furthermore, the sixth parasitic diode 2DP-3 is also a parasitic diode formed by the emitter (third P-type doped region P3)-base (second N-type well region NW2) junction of the seventh parasitic bipolar junction transistor B7. When the fifth parasitic diode 2DP-2 and the sixth parasitic diode 2DP-3 (i.e., the two parasitic diodes 2DP connected in series) are slightly turned on, the sixth parasitic bipolar junction transistor B6 and the seventh parasitic bipolar junction transistor B7 will also be triggered to turn on, thereby triggering the fourth parasitic semiconductor controlled rectifier SCR-4 to turn on, releasing most of the electrostatic discharge current from the ground terminal VSS to the input / output terminal IO, so as to prevent the electrostatic discharge current from flowing through the protected circuit.

[0085] This invention provides an electrostatic discharge (ESD) protection device applicable to systems with operating voltages below 1.0 V. The ESD protection device utilizes a layout with two different P-type well regions within two N-type well regions and N-type / P-type heavily doped regions located in the N-type and P-type well regions respectively. This allows a parasitic semiconductor controlled rectifier (SCR) to be inserted between two series-connected parasitic diodes. The base of the parasitic NPN BJT in the SCR is electrically connected to the base of the PNP BJT, which is then connected to the negative terminal of the first parasitic diode and the positive terminal of the second parasitic diode. Furthermore, the distance between the heavily doped P-type region receiving a higher level of energy in the two N-type well regions and the heavily doped N-type region receiving a lower level of energy in the surrounding P-type well region is reduced to the minimum spacing specified in the design rules (meaning that in a cross-sectional view, there are no other heavily doped N-type regions between the heavily doped P-type region in the aforementioned N-type well region and the heavily doped N-type region in the surrounding P-type well region), thereby shortening the distance from the anode (the first P-type doped region at the PNPN junction) to the cathode (the last N-type doped region at the PNPN junction) of the parasitic semiconductor controlled rectifier. The aforementioned parasitic semiconductor controlled rectifier is a multidirectional semiconductor controlled rectifier, capable of guiding electrostatic charges away from the protected circuit for electrostatic discharge events occurring at any of the input / output terminals IO, power supply terminal VCC, or ground terminal VSS. When an electrostatic discharge (ESD) event occurs, a portion of the ESD current first flows through two parasitic diodes connected in series to the low-level terminal, rapidly triggering the conduction of the parasitic semiconductor-controlled rectifier. This allows most of the ESD current to be released from the high-level terminal to the low-level terminal, preventing the ESD current from flowing through the protected circuit. The ESD protection device of this invention significantly improves discharge efficiency and provides extremely low electrical parameters such as trigger voltage (Vt1), holding voltage, and on-resistance (Ron), meeting the requirements of high-end chip manufacturing.

[0086] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention should be defined by the appended claims.

Claims

1. An electrostatic discharge protection device, comprising: P-type semiconductor substrate; The first N-type well region is located in the P-type semiconductor substrate; The first N-type doped region is located in the first N-type well region; The first P-type doped region is located in the first N-type well region and is arranged side by side with the first N-type doped region and spaced apart from each other; The second N-type well region is located in the P-type semiconductor substrate and is arranged side by side with the first N-type well region and spaced apart from each other; The second N-type doped region is located in the second N-type well region; The second P-type doped region is located in the second N-type well region; The third P-type doped region is located in the second N-type well region, wherein the second N-type doped region, the second P-type doped region and the third P-type doped region are arranged side by side and spaced apart from each other; The first P-type well region is located within the first N-type well region; The third N-type doped region is located in the first P-type well region; The fourth P-type doped region is located in the first P-type well region and is arranged side by side with the third N-type doped region and spaced apart from each other; The second P-type well region is located within the first N-type well region and is arranged side by side with the first P-type well region and spaced apart from each other; The fourth N-type doped region is located within the second P-type well region; The fifth P-type doped region is located in the second P-type well region and is arranged side by side with the fourth N-type doped region and spaced apart from each other; The third P-type well region is located within the second N-type well region; The fifth N-type doped region is located in the third P-type well region; as well as The sixth P-type doped region is located in the third P-type well region and is arranged side by side with the fifth N-type doped region and spaced apart from each other; The first N-type doped region is directly electrically connected to the fifth P-type doped region. The second N-type doped region is directly electrically connected to the sixth P-type doped region. The first P-type doped region and the fifth N-type doped region are electrically connected to the input / output terminal. The second P-type doped region and the third N-type doped region are electrically connected to the power supply terminal. The third P-type doped region, the fourth N-type doped region, and the fourth P-type doped region are electrically connected to the ground terminal.

2. The electrostatic discharge protection device as claimed in claim 1, wherein the first N-type well region and the second N-type well region are arranged side by side along the first direction and spaced apart from each other.

3. The electrostatic discharge protection device as claimed in claim 2, wherein the first P-type well region is located between the first N-type doped region and the first P-type doped region along the first direction.

4. The electrostatic discharge protection device as claimed in claim 2, wherein the first P-type well region and the second P-type well region are respectively located on opposite sides of the first P-type doped region that are substantially parallel to the second direction, and are respectively spaced apart from the first P-type doped region along the first direction.

5. The electrostatic discharge protection device as claimed in claim 2, wherein the second P-type doped region and the third P-type doped region are respectively located on opposite sides of the third P-type well region that are substantially parallel to the second direction, and are respectively spaced apart from the third P-type well region along the first direction.

6. The electrostatic discharge protection device as claimed in claim 1, wherein in a cross-sectional view, the first N-type well region and the second N-type well region have a first depth, the first P-type well region, the second P-type well region and the third P-type well region have a second depth, and the first depth is greater than the second depth.

7. The electrostatic discharge protection device as described in claim 1, further comprising: The first N-type deep well region is located below the first N-type well region, the first P-type well region, and the second P-type well region, wherein the first N-type deep well region is in contact with multiple bottom surfaces of the first N-type well region, the first P-type well region, and the second P-type well region.

8. The electrostatic discharge protection device of claim 7, wherein in a cross-sectional view, the boundary of the first N-type deep well region is aligned with the boundary of the first N-type well region.

9. The electrostatic discharge protection device as described in claim 7, further comprising: The second N-type deep well region is located below the first N-type deep well region and the third P-type deep well region, and is spaced apart from the first N-type deep well region. The second N-type deep well region is in contact with multiple bottom surfaces of the first N-type deep well region and the third P-type deep well region.

10. The electrostatic discharge protection device of claim 9, wherein in a cross-sectional view, the boundary of the second N-type deep well region is aligned with the boundary of the second N-type well region.

11. The electrostatic discharge protection device as claimed in claim 9, wherein in a cross-sectional view, the first N-type well region and the second N-type well region have a first depth, and the first P-type well region, the second P-type well region and the third P-type well region have a second depth, the first depth being equal to the second depth.

12. The electrostatic discharge protection device of claim 11, wherein in the cross-sectional view, the first N-type deep well region and the second N-type deep well region have a third depth, the third depth being greater than the first depth and the second depth.

13. The electrostatic discharge protection device as described in claim 1, wherein: The first P-type doped region and the first N-type well region constitute the first parasitic diode. The fifth P-type doped region, the second P-type well region, and the fourth N-type doped region constitute the second parasitic diode, wherein the first parasitic diode is connected in series with the second parasitic diode. The first P-type doped region, the first N-type well region, and the second P-type well region constitute the first parasitic bipolar junction transistor. The fourth N-type doped region, the second P-type well region, and the first N-type well region constitute the second parasitic bipolar junction transistor. The base of the first parasitic bipolar junction transistor is electrically connected to the collector of the second parasitic bipolar junction transistor, and the base of the second parasitic bipolar junction transistor is electrically connected to the collector of the first parasitic bipolar junction transistor, thereby forming a first parasitic semiconductor controlled rectifier. The base of the first parasitic bipolar junction transistor is electrically connected to the negative terminal of the first parasitic diode. The base of the second parasitic bipolar junction transistor is electrically connected to the positive terminal of the second parasitic diode.

14. The electrostatic discharge protection device of claim 13, wherein when an electrostatic discharge event occurs between the input / output terminal and the ground terminal, the first parasitic diode and the second parasitic diode are triggered to conduct, and the first parasitic bipolar junction transistor and the second parasitic bipolar junction transistor are triggered to conduct, thereby triggering the first parasitic semiconductor control rectifier to conduct.

15. The electrostatic discharge protection device as described in claim 1, wherein: The first P-type doped region and the first N-type well region constitute the first parasitic diode. The second P-type well region, the fifth P-type doped region, and the fourth N-type doped region constitute the second parasitic diode, wherein the first parasitic diode is connected in series with the second parasitic diode. The third N-type doped region, the first P-type well region, and the first N-type well region constitute the third parasitic bipolar junction transistor. The first P-type doped region, the first N-type well region, and the first P-type well region constitute the fourth parasitic bipolar junction transistor. The base of the third parasitic bipolar junction transistor is electrically connected to the collector of the fourth parasitic bipolar junction transistor, and the base of the fourth parasitic bipolar junction transistor is electrically connected to the collector of the third parasitic bipolar junction transistor, thereby forming a second parasitic semiconductor controlled rectifier. The base of the fourth parasitic bipolar junction transistor is electrically connected to the negative terminal of the first parasitic diode, and is electrically connected to the positive terminal of the second parasitic diode through a wire.

16. The electrostatic discharge protection device of claim 15, wherein when an electrostatic discharge event occurs between the input / output terminal and the power supply terminal, the first parasitic diode and the second parasitic diode are triggered to conduct, and the third parasitic bipolar junction transistor and the fourth parasitic bipolar junction transistor are triggered to conduct, thereby triggering the second parasitic semiconductor control rectifier to conduct.

17. The electrostatic discharge protection device as described in claim 1, wherein: The second P-type doped region and the second N-type well region constitute the fourth parasitic diode. The sixth P-type doped region, the third P-type well region, and the fifth N-type doped region constitute the fifth parasitic diode, wherein the fourth parasitic diode is connected in series with the fifth parasitic diode. The second P-type doped region, the second N-type well region, and the third P-type well region constitute the fifth parasitic bipolar junction transistor. The fifth N-type doped region, the third P-type well region, and the second N-type well region constitute the sixth parasitic bipolar junction transistor. The base of the fifth parasitic bipolar junction transistor is electrically connected to the collector of the sixth parasitic bipolar junction transistor, and the base of the sixth parasitic bipolar junction transistor is electrically connected to the collector of the fifth parasitic bipolar junction transistor, thereby forming a third parasitic semiconductor controlled rectifier. The base of the fifth parasitic bipolar junction transistor is electrically connected to the negative terminal of the fourth parasitic diode. The base of the sixth parasitic bipolar junction transistor is electrically connected to the positive terminal of the fifth parasitic diode.

18. The electrostatic discharge protection device of claim 17, wherein when an electrostatic discharge event occurs between the power supply terminal and the input / output terminal, the fourth parasitic diode and the fifth parasitic diode are triggered to conduct, and the fifth parasitic bipolar junction transistor and the sixth parasitic bipolar junction transistor are triggered to conduct, thereby triggering the third parasitic semiconductor control rectifier to conduct.

19. The electrostatic discharge protection device as described in claim 17, wherein: The sixth P-type doped region, the third P-type well region, and the fifth N-type doped region constitute the fifth parasitic diode. The third P-type doped region and the second N-type well region constitute the sixth parasitic diode, wherein the fifth parasitic diode is connected in series with the sixth parasitic diode. The fifth N-type doped region, the third P-type well region, and the second N-type well region constitute the sixth parasitic bipolar junction transistor. The third P-type doped region, the second N-type well region, and the third P-type well region constitute the seventh parasitic bipolar junction transistor. The base of the sixth parasitic bipolar junction transistor is electrically connected to the collector of the seventh parasitic bipolar junction transistor, and the base of the seventh parasitic bipolar junction transistor is electrically connected to the collector of the sixth parasitic bipolar junction transistor, thereby forming a fourth parasitic semiconductor controlled rectifier. The base of the seventh parasitic bipolar junction transistor is electrically connected to the negative terminal of the sixth parasitic diode. The base of the sixth parasitic bipolar junction transistor is electrically connected to the positive terminal of the fifth parasitic diode.

20. The electrostatic discharge protection device of claim 19, wherein when an electrostatic discharge event occurs between the ground terminal and the input / output terminal, the fifth parasitic diode and the sixth parasitic diode are triggered to conduct, and the sixth parasitic bipolar junction transistor and the seventh parasitic bipolar junction transistor are triggered to conduct, thereby triggering the four parasitic semiconductor controlled rectifier to conduct.

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