Metal oxide thin-film transistor array substrate, its fabrication method and display panel

Abstract

A metal oxide thin-film transistor array substrate, its fabrication method, and a display panel are disclosed, comprising: a substrate; scan lines and gates formed by etching a first metal layer on the substrate; a gate insulating layer covering the scan lines and gates; a metal oxide semiconductor layer, a second metal layer, and an isolation insulating layer sequentially disposed on the gate insulating layer; wherein the isolation insulating layer, the second metal layer, and the metal oxide semiconductor layer are all etched and patterned; the second metal layer is etched to form data lines and mutually spaced source and drain electrodes; the metal oxide semiconductor layer is etched to form a semiconductor active layer at the channel position; the etched isolation insulating layer is disposed vertically overlapping the data lines, source electrodes, and drain electrodes; a metal oxide semiconductor layer is stacked below the data lines, source electrodes, and drain electrodes; and an oxide layer is formed on the sides of the data lines, source electrodes, and drain electrodes by oxidation treatment.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a metal oxide thin-film transistor array substrate, its fabrication method, and a display panel. Background Technology

[0002] With the development of the information age, as a human-machine interface application, the display screen has increasingly higher requirements for various specifications. Due to the limited performance of amorphous silicon (a-Si) driving devices, it is necessary to replace them with devices made of materials with high electron mobility to meet product performance specifications. As the requirements for display screen resolution and power consumption increase, the use of low-impedance metals is also a trend.

[0003] Metal oxide semiconductors (MOS) offer advantages over amorphous silicon, including higher electron mobility, lower leakage current, and compatibility with most device fabrication processes. Common MOS materials include indium gallium zinc oxide (IGZO). Due to their high mobility, MOS devices are frequently used in high-end, high-specification products. Therefore, they are often paired with copper processes because copper (Cu) has low impedance, which simultaneously reduces the resistance-capacitance (RC) delay of metal traces and the charging time required for the device. This combination provides high resolution and low power consumption.

[0004] Metal-oxide-semiconductor-layer transistors (MOS-TFTs) have two common structures: Etch-Stop Layer (ESL) and Back Channel Etch (BCE). In ESL MOS-TFTs, the etch stop layer protects the channel of the thin-film transistor during source and drain etching, but requires an additional patterning step compared to BCE MOS-TFTs. BCE MOS-TFTs, because they do not require an etch stop layer, save a patterning step, are compatible with current mass-production silicon-based manufacturing processes, and therefore have relatively lower production costs and technological advantages.

[0005] However, copper (Cu) is a highly reactive metal, readily undergoing metal ion diffusion, which introduces numerous instabilities into the manufacturing process. Current methods employ a multilayer structure of silicon oxide (SiOx) and silicon nitride (SiNx) stacked in contact with the copper to prevent metal ion penetration. While the stacked use of SiOx and SiNx ensures a secure interface with the copper, the inconsistent etching rates of SiOx and SiNx lead to undercutting, expose the sides of the copper layer (which cannot prevent metal ion diffusion), and require a large number of photomasks, resulting in a complex, costly, and inefficient manufacturing process. Summary of the Invention

[0006] The purpose of this invention is to provide a metal oxide thin film transistor array substrate and its fabrication method, which combines copper processing with back-channel etched metal oxide thin film transistors to solve the problems of easy metal ion penetration, complicated processes, high costs, and low production efficiency in the prior art.

[0007] This invention provides a metal oxide thin-film transistor array substrate, comprising: a substrate; scan lines and gates formed by etching and patterning a first metal layer on the substrate; a gate insulating layer covering the scan lines and the gates; and a metal oxide semiconductor layer, a second metal layer, and an isolation insulating layer sequentially disposed on the gate insulating layer.

[0008] In this process, the insulating layer, the second metal layer, and the metal oxide semiconductor layer are all etched and patterned. After the second metal layer is etched, it forms data lines and source and drain electrodes spaced apart from each other. After the metal oxide semiconductor layer is etched, it forms a semiconductor active layer at the channel position. The etched insulating layer is stacked vertically with the data lines, the source electrodes, and the drain electrodes. The metal oxide semiconductor layer is stacked below the data lines, the source electrodes, and the drain electrodes. The sides of the data lines, the source electrodes, and the drain electrodes are oxidized to form an oxide layer.

[0009] Furthermore, the insulating layer also covers the active semiconductor layer, and the pattern of the insulating layer after etching is the same as the pattern formed by the data line, the source, the drain, and the active semiconductor layer.

[0010] Furthermore, the metal oxide thin-film transistor array substrate further includes: a first passivation layer covering the isolation insulating layer on the gate insulating layer; a planarization layer on the first passivation layer; a common electrode formed by etching and patterning a first transparent conductive layer on the planarization layer; a second passivation layer covering the common electrode, wherein a contact hole is formed through the second passivation layer, the planarization layer, the first passivation layer, and the isolation insulating layer at a position corresponding to the drain; and a pixel electrode formed by etching and patterning a second transparent conductive layer on the second passivation layer, wherein the pixel electrode is filled in the contact hole and electrically connected to the drain.

[0011] Furthermore, the pattern of the insulating layer after etching is the same as the pattern formed by the data line, the source, and the drain together.

[0012] Furthermore, the metal oxide thin-film transistor array substrate further includes: a first passivation layer covering the isolation insulating layer and the semiconductor active layer on the gate insulating layer; a planarization layer on the first passivation layer; a common electrode formed by etching and patterning a first transparent conductive layer on the planarization layer; a second passivation layer covering the common electrode, wherein a contact hole is formed through the second passivation layer, the planarization layer, the first passivation layer and the isolation insulating layer at a position corresponding to the drain; and a pixel electrode formed by etching and patterning a second transparent conductive layer on the second passivation layer, wherein the pixel electrode fills the contact hole and is electrically connected to the drain.

[0013] This invention also provides a method for fabricating a metal oxide thin-film transistor array substrate, comprising:

[0014] A first metal layer is formed on a substrate, and the first metal layer is etched and patterned so that the first metal layer is etched to form scan lines and gates.

[0015] A gate insulating layer, a metal oxide semiconductor layer, and a second metal layer covering the scan line and the gate are sequentially and continuously formed on the substrate.

[0016] A photoresist layer is coated on the second metal layer;

[0017] The photoresist layer is exposed and developed using a halftone photomask, leaving a first photoresist pattern and a second photoresist pattern on the photoresist layer. Other areas where no photoresist is left are exposed, revealing the second metal layer. The thickness of the first photoresist pattern is greater than the thickness of the second photoresist pattern. The first photoresist pattern corresponds to the positions of the data line, source, and drain, and the second photoresist pattern corresponds to the position of the channel region.

[0018] Using the first photoresist pattern and the second photoresist pattern as a mask, the second metal layer is etched and patterned to remove the exposed second metal layer. After the second metal layer is etched for the first time, data lines are formed and the underlying metal oxide semiconductor layer is exposed.

[0019] Using the first photoresist pattern and the second photoresist pattern as a mask, the metal oxide semiconductor layer is etched and patterned to remove the exposed metal oxide semiconductor layer, so that the metal oxide semiconductor layer is etched to form a semiconductor active layer at the channel position.

[0020] The second photoresist pattern is removed by photoresist ashing to expose the second metal layer at the channel location, but the first photoresist pattern remains.

[0021] Using the first photoresist pattern as a mask, the second metal layer at the channel position is etched and patterned to remove the second metal layer exposed at the channel position. After the second metal layer is etched a second time, it forms a source and drain that are spaced apart from each other, and exposes the semiconductor active layer below at the channel position. After the second metal layer is etched twice, the sides of the data line, the source and the drain formed are exposed.

[0022] After forming the data line, the source, and the drain, the first photoresist pattern is removed;

[0023] An isolation insulating layer is formed on the gate insulating layer, covering the data line, the source, the drain and the semiconductor active layer, and the isolation insulating layer is etched and patterned so that the pattern of the isolation insulating layer after etching is the same as the pattern formed by the data line, the source, the drain and the semiconductor active layer together, and the sides of the data line, the source and the drain are still exposed.

[0024] The exposed sides of the data line, the source electrode, and the drain electrode are oxidized using plasma, forming an oxide layer.

[0025] Furthermore, the manufacturing method also includes:

[0026] A first passivation layer covering the isolation insulating layer is formed on the gate insulating layer;

[0027] A planarization layer is formed on the first passivation layer, and the planarization layer is patterned so that a perforation is formed on the planarization layer at a position corresponding to the drain electrode, exposing the underlying first passivation layer.

[0028] A first transparent conductive layer is formed on the planar layer, and the first transparent conductive layer is etched and patterned so that the first transparent conductive layer is etched to form a common electrode.

[0029] A second passivation layer covering the common electrode is formed on the planar layer, and the second passivation layer, the first passivation layer and the isolation insulating layer are simultaneously etched and patterned. A contact hole is formed at the position corresponding to the drain electrode, penetrating the second passivation layer, the first passivation layer and the isolation insulating layer, so that the drain electrode is exposed through the contact hole.

[0030] A second transparent conductive layer is formed on the second passivation layer, and the second transparent conductive layer is etched and patterned so that the second transparent conductive layer is etched to form a pixel electrode, wherein the pixel electrode is filled into the contact hole and conductively connected to the drain electrode.

[0031] This invention also provides a method for fabricating a metal oxide thin-film transistor array substrate, comprising:

[0032] A first metal layer is formed on a substrate, and the first metal layer is etched and patterned so that the first metal layer is etched to form scan lines and gates.

[0033] A gate insulating layer, a metal oxide semiconductor layer, a second metal layer, and an isolation insulating layer covering the scan line and the gate are sequentially and continuously formed on the substrate.

[0034] A photoresist layer is coated on the insulating layer;

[0035] The photoresist layer is exposed and developed using a halftone photomask, leaving a first photoresist pattern and a second photoresist pattern on the photoresist layer. Other areas where no photoresist is left are exposed, revealing the insulating layer. The thickness of the first photoresist pattern is greater than the thickness of the second photoresist pattern. The first photoresist pattern corresponds to the positions of the data line, source, and drain, and the second photoresist pattern corresponds to the position of the channel region.

[0036] Using the first photoresist pattern and the second photoresist pattern as a mask, the insulating layer is etched and patterned to remove the exposed insulating layer, and after the insulating layer is etched for the first time, the underlying second metal layer is exposed.

[0037] Using the first photoresist pattern and the second photoresist pattern as a mask, the second metal layer is etched and patterned to remove the exposed second metal layer. After the second metal layer is etched for the first time, data lines are formed and the underlying metal oxide semiconductor layer is exposed.

[0038] Using the first photoresist pattern and the second photoresist pattern as a mask, the metal oxide semiconductor layer is etched and patterned to remove the exposed metal oxide semiconductor layer, so that the metal oxide semiconductor layer is etched to form a semiconductor active layer at the channel position.

[0039] The second photoresist pattern is removed by photoresist ashing to expose the insulating layer at the channel location, but the first photoresist pattern remains.

[0040] Using the first photoresist pattern as a mask, the insulating layer at the channel position is etched and patterned to remove the insulating layer exposed at the channel position, and after the insulating layer is etched a second time, the second metal layer below is exposed at the channel position.

[0041] Using the first photoresist pattern as a mask, the second metal layer at the channel position is etched and patterned to remove the second metal layer exposed at the channel position. After the second etching, the second metal layer forms a source and drain that are spaced apart from each other, and exposes the underlying semiconductor active layer at the channel position. The pattern of the isolation insulating layer after the two etchings is the same as the pattern formed by the data line, the source and the drain. The sides of the data line, the source and the drain formed by the second metal layer after the two etchings are exposed.

[0042] After forming the data line, the source, and the drain, the first photoresist pattern is removed;

[0043] The exposed sides of the data line, the source electrode, and the drain electrode are oxidized using plasma, forming an oxide layer.

[0044] Furthermore, the manufacturing method also includes:

[0045] A first passivation layer is formed on the gate insulating layer, covering the isolation insulating layer and the semiconductor active layer;

[0046] A planarization layer is formed on the first passivation layer, and the planarization layer is patterned so that a perforation is formed on the planarization layer at a position corresponding to the drain electrode, exposing the underlying first passivation layer.

[0047] A first transparent conductive layer is formed on the planar layer, and the first transparent conductive layer is etched and patterned so that the first transparent conductive layer is etched to form a common electrode.

[0048] A second passivation layer covering the common electrode is formed on the planar layer, and the second passivation layer, the first passivation layer and the isolation insulating layer are simultaneously etched and patterned. A contact hole is formed at the position corresponding to the drain electrode, penetrating the second passivation layer, the first passivation layer and the isolation insulating layer, so that the drain electrode is exposed through the contact hole.

[0049] A second transparent conductive layer is formed on the second passivation layer, and the second transparent conductive layer is etched and patterned so that the second transparent conductive layer is etched to form a pixel electrode, wherein the pixel electrode is filled into the contact hole and conductively connected to the drain electrode.

[0050] This invention also provides a display panel comprising the aforementioned metal oxide thin-film transistor array substrate.

[0051] The metal oxide thin-film transistor array substrate and its fabrication method provided in this invention include a copper layer in the second metal layer. An oxide layer is formed on the exposed sides of the data lines, source, and drain by using plasma oxidation treatment. Since the copper on the sides of the data lines, source, and drain is oxidized, metal ions are less likely to penetrate from these sides, effectively suppressing copper ion diffusion and better ensuring the characteristic curve of the TFT. The presence of the insulating layer prevents the copper on the upper surfaces of the data lines, source, and drain from being oxidized, avoiding problems such as poor conductive contact between the pixel electrode and the drain.

[0052] The process described in this invention can be matched with existing production processes and can fabricate back-channel etched MOS-TFTs based on copper traces. Due to the low impedance of copper, the resistance-capacitance (RC) delay of the metal traces and the charging time required by the device can be reduced simultaneously. When combined with metal oxide, it can provide high resolution and low power consumption, making it suitable for high-end, high-specification products. At the same time, with the use of halftone photomasks, the etching of the second metal layer and the metal oxide semiconductor layer can share the same photomask, or the etching of the isolation insulating layer, the second metal layer, and the metal oxide semiconductor layer can share the same photomask. This can reduce the number of photomasks used, greatly reduce costs, save process time, and improve production efficiency.

[0053] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0054] Figure 1 This is a partial cross-sectional schematic diagram of the metal oxide thin-film transistor array substrate in the first embodiment of the present invention;

[0055] Figures 2a to 2o for Figure 1 A cross-sectional schematic diagram of the fabrication process of a metal oxide thin-film transistor array substrate;

[0056] Figure 3 This is a partial cross-sectional schematic diagram of the metal oxide thin-film transistor array substrate in the second embodiment of the present invention;

[0057] Figures 4a to 4p for Figure 3 A cross-sectional schematic diagram of the fabrication process of a metal oxide thin-film transistor array substrate;

[0058] Figure 5This is a partial cross-sectional schematic diagram of the peripheral region of the metal oxide thin film transistor array substrate in an embodiment of the present invention. Detailed Implementation

[0059] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the specific embodiments, structures, features, and effects of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments:

[0060] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

[0061] [First Embodiment]

[0062] Figure 1 This is a partial cross-sectional schematic diagram of the metal oxide thin-film transistor array substrate in the first embodiment of the present invention, as shown below. Figure 1 As shown, the first embodiment of the present invention provides a metal oxide thin film transistor array substrate, including: a substrate 10; a scan line (not shown) and a gate 111 formed by etching and patterning a first metal layer 11 on the substrate 10. The gate 111 is connected to the scan line or is part of the scan line; a gate insulating layer 12 covering the scan line and the gate 111; and a metal oxide semiconductor layer 13, a second metal layer 14, and an isolation insulating layer 15 sequentially disposed on the gate insulating layer 12.

[0063] The second metal layer 14 includes a copper layer. The isolation insulating layer 15, the second metal layer 14, and the metal oxide semiconductor layer 13 are all etched and patterned. After the second metal layer 14 is etched, it forms a data line (not shown) and a source electrode 141 and a drain electrode 142 spaced apart from each other. After the metal oxide semiconductor layer 13 is etched, it forms a semiconductor active layer 131 at the channel position. The etched isolation insulating layer 15 is stacked vertically with the data line, the source electrode 141, and the drain electrode 142. The metal oxide semiconductor layer 13 is stacked below the data line, the source electrode 141, and the drain electrode 142. The copper exposed on the side of the data line, the source electrode 141, and the drain electrode 142 is oxidized to form an oxide layer 143.

[0064] Specifically, the second metal layer 14 can be a single-layer structure containing only a copper layer, or a multi-layer structure containing a copper layer. For example, the top layer of the second metal layer 14 is a copper layer, and the bottom layer is a molybdenum (Mo) or molybdenum-niobium alloy (MoNb) layer.

[0065] Specifically, a half-tone mask (HTM) can be used to expose the coated photoresist layer on the second metal layer 14. In a half-tone mask process, the same photoresist is used as a mask to sequentially etch and pattern the second metal layer 14 and the metal oxide semiconductor layer 13, so that in addition to forming the semiconductor active layer 131 at the channel position, the metal oxide semiconductor layer 13 is also stacked below the data line, the source 141 and the drain 142.

[0066] In this embodiment, the insulating layer 15 also covers the active semiconductor layer 131. The pattern of the insulating layer 15 after etching is the same as the pattern formed by the data lines, source 141, drain 142, and active semiconductor layer 131 (that is, the insulating layer 15 is only covered directly above the data lines, source 141, drain 142, and active semiconductor layer 131 in the panel, and there is no insulating layer 15 in other positions). The etched insulating layer 15 is vertically overlapped with the data lines, source 141, drain 142, and active semiconductor layer 131. Preferably, when etching the insulating layer 15, the photomask used can be the halftone photomask mentioned above, so that the pattern obtained after etching the insulating layer 15 is the same as the pattern formed by the data lines, source 141, drain 142, and active semiconductor layer 131.

[0067] Specifically, after forming the data line, source 141, drain 142, and insulating layer 15, plasma (e.g., N2O, O2) can be used to oxidize the exposed sides of the data line, source 141, and drain 142 to form an oxide layer 143 on each of these exposed sides. Due to the strong oxidizing properties of plasma, the exposed copper metal on the sides of the data line, source 141, and drain 142 will be oxidized, thus forming an oxide layer 143 on each of these sides. However, since the upper surfaces of the data line, source 141, and drain 142 are covered with the insulating layer 15, the oxidation of the copper metal on the upper surfaces of the data line, source 141, and drain 142 can be effectively prevented.

[0068] Since the copper on the sides of the data line, source 141, and drain 142 is oxidized, metal ions are less likely to penetrate from the sides of these components, effectively suppressing copper ion diffusion and better ensuring the characteristic curve of the TFT. Simultaneously, the presence of the insulating layer 15 prevents the copper on the upper surfaces of the data line, source 141, and drain 142 from oxidizing, thus avoiding poor conductive contact issues when the pixel electrode 231 is connected to the drain 142 in subsequent processes.

[0069] This embodiment can be matched with the existing production process and can fabricate back-channel etched MOS-TFTs based on copper traces. Since copper has the advantage of low impedance, it can simultaneously reduce the resistance-capacitance (RC) delay of the metal traces and the charging time required by the device. When combined with metal oxide, it can provide high resolution and low power consumption, which is suitable for high-end and high-specification products. At the same time, with the use of halftone photomasks, when etching the second metal layer 14 and etching the metal oxide semiconductor layer 13, the etching of the two layers can share the same photomask, which can reduce the number of photomasks used, reduce costs, save process time, and improve production efficiency.

[0070] Furthermore, the metal oxide thin-film transistor array substrate further includes: a first passivation layer 16 covering an isolation insulating layer 15 on the gate insulating layer 12; a planarization layer 17 on the first passivation layer 16; a common electrode 181 formed by etching a first transparent conductive layer 18 on the planarization layer 17; a second passivation layer 19 covering the common electrode 181, wherein a contact hole 191 is formed through the second passivation layer 19, the planarization layer 17, the first passivation layer 16 and the isolation insulating layer 15 at a position corresponding to the drain 142; and a pixel electrode 231 formed by etching a second transparent conductive layer 23 on the second passivation layer 19, wherein the pixel electrode 231 is filled in the contact hole 191 and electrically connected to the drain 142.

[0071] In the plasma processing steps described above, since the insulating layer 15 covers the data line, source 141 and drain 142, the presence of the insulating layer 15 effectively prevents the copper metal on the upper surface of the data line, source 141 and drain 142 from being oxidized. Therefore, the pixel electrode 231 can make good conductive contact with the drain 142.

[0072] Specifically, the gate insulating layer 12, the isolation insulating layer 15, the first passivation layer 16, and the second passivation layer 19 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a composite layer of silicon nitride and silicon oxide, etc. The isolation insulating layer 15 and the first passivation layer 16 use the same material, for example, both being silicon oxide (SiOx). This avoids undercutting caused by inconsistent etching rates between the two different materials when forming the contact hole 191. The metal oxide semiconductor layer 13 can be made of indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc. The first transparent conductive layer 18 and the second transparent conductive layer 23 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0073] Figures 2a to 2o for Figure 1 A cross-sectional schematic diagram of the fabrication process of a metal-oxide-slim thin-film transistor array substrate, as shown below. Figures 2a to 2oAs shown, the first embodiment of the present invention also provides a method for fabricating a metal oxide thin-film transistor array substrate. Specifically, the fabrication method includes:

[0074] Please refer to Figure 2a A first metal layer 11 is formed on the substrate 10, and the first metal layer 11 is etched and patterned so that the first metal layer 11 is etched to form a scan line (not shown) and a gate 111. The gate 111 is connected to the scan line or is part of the scan line.

[0075] Please refer to Figure 2b A gate insulating layer 12, a metal oxide semiconductor layer 13, and a second metal layer 14 covering the scan line and the gate 111 are sequentially and continuously formed on the substrate 10, wherein the second metal layer 14 includes a copper layer. Specifically, the second metal layer 14 can be a single-layer structure containing only a copper layer, or it can be a multi-layer structure containing copper layers. For example, the top layer of the second metal layer 14 is a copper layer, and the bottom layer is a molybdenum (Mo) or molybdenum-niobium alloy (MoNb) layer.

[0076] Please refer to Figure 2c A photoresist layer 20 is coated on the second metal layer 14.

[0077] Please refer to Figure 2d A halftone mask 30 (HTM) is used to expose and develop the photoresist layer 20, leaving a first photoresist pattern 21 and a second photoresist pattern 22 on the photoresist layer 20. Other areas without photoresist are exposed, revealing the second metal layer 14. The thickness of the first photoresist pattern 21 is greater than the thickness of the second photoresist pattern 22. The first photoresist pattern 21 corresponds to the positions of the data lines, source 141, and drain 142, while the second photoresist pattern 22 corresponds to the position of the channel region. Except for the first and second photoresist patterns 21 and 22, other areas have no photoresist and expose the second metal layer 14.

[0078] Specifically, the halftone mask 30 includes an opaque area 31, a semi-transparent area 32, and a fully transparent area 33, wherein the opaque area 31, the semi-transparent area 32, and the fully transparent area 33 correspond to the first photoresist pattern 21, the second photoresist pattern 22, and other areas where no photoresist needs to be left, respectively. In this way, after exposure and development, the photoresist layer 20 can leave the first photoresist pattern 21 and the second photoresist pattern 22, and the thickness of the first photoresist pattern 21 is greater than the thickness of the second photoresist pattern 22.

[0079] Please refer to Figure 2eUsing the first photoresist pattern 21 and the second photoresist pattern 22 as a mask, the second metal layer 14 is etched and patterned to remove the exposed second metal layer 14. After the second metal layer 14 is etched for the first time, data lines are formed and the underlying metal oxide semiconductor layer 13 is exposed. Specifically, the second metal layer 14 can be etched and patterned using a first etchant, such as copper acid, which contains hydrogen peroxide.

[0080] Please refer to Figure 2f The metal oxide semiconductor layer 13 is then etched and patterned using the first photoresist pattern 21 and the second photoresist pattern 22 as shielding elements, removing any exposed metal oxide semiconductor layer 13. Specifically, a second etchant, such as aluminic acid or oxalic acid, can be used to etch and pattern the metal oxide semiconductor layer 13.

[0081] Please refer to Figure 2g The second photoresist pattern 22 is removed using photoresist ashing to expose the second metal layer 14 at the channel location, but the first photoresist pattern 21 remains. It should be noted that during the photoresist ashing process, the first photoresist pattern 21 is also thinned, but since the first photoresist pattern 21 is thicker than the second photoresist pattern 22, the first photoresist pattern 21 still covers the positions corresponding to the data line, source 141, and drain 142 after thinning.

[0082] Please refer to Figure 2h Using the first photoresist pattern 21 as a mask, the second metal layer 14 at the channel location is etched and patterned to remove the exposed second metal layer 14 at the channel location. This allows the first metal layer 11 to be etched a second time, forming a source electrode 141 and a drain electrode 142 spaced apart from each other, and exposing the underlying semiconductor active layer 131 at the channel location. After the second metal layer 14 is etched twice, the data lines, the sides of the source electrode 141 and the drain electrode 142 are all exposed. Specifically, the first etchant is used to etch and pattern the second metal layer 14 at the channel location to remove the exposed second metal layer 14 at the channel location. The source electrode 141 is connected to the data line or is part of the data line, and the source electrode 141 and the drain electrode 142 are spaced apart from each other.

[0083] Since the channel region where the semiconductor active layer 131 is located is easily damaged by the etching solution used to form the source 141 and drain 142 when forming the source 141 and drain 142 in the back channel etched MOS-TFT, after exposing the underlying semiconductor active layer 131 at the channel position, annealing can be performed on the channel region of the semiconductor active layer 131 to improve the damage condition of the semiconductor active layer 131 and repair the electrical characteristics of the metal oxide semiconductor as the semiconductor active layer 131.

[0084] In the above process, since the same photoresist is used as a mask to etch and pattern the second metal layer 14 and the metal oxide semiconductor layer 13 in a single half-tone photomask process, in addition to forming a semiconductor active layer 131 at the channel position, the metal oxide semiconductor layer 13 is also stacked below the data line, the source 141 and the drain 142.

[0085] Please refer to Figure 2i After forming the data line, source 141 and drain 142, the first photoresist pattern 21 is removed.

[0086] Please refer to Figure 2j An isolation insulating layer 15 is formed on the gate insulating layer 12, covering the data lines, source 141, drain 142, and active semiconductor layer 131. The isolation insulating layer 15 is then etched and patterned so that the etched pattern is identical to the pattern formed by the data lines, source 141, drain 142, and active semiconductor layer 131 (i.e., the isolation insulating layer 15 is only present directly above the data lines, source 141, drain 142, and active semiconductor layer 131, while other locations are uncovered), while the sides of the data lines, source 141, and drain 142 remain exposed. Preferably, the photomask used for etching and patterning the isolation insulating layer 15 can be a halftone photomask as described above, so that the resulting pattern after etching the isolation insulating layer 15 is identical to the pattern formed by the data lines, source 141, drain 142, and active semiconductor layer 131.

[0087] Please refer to Figure 2k The exposed sides of the data line, source 141, and drain 142 are oxidized using plasma (e.g., N2O, O2), causing the exposed copper on these sides to oxidize and form an oxide layer 143. Due to the strong oxidizing properties of plasma, the exposed copper on the sides of the data line, source 141, and drain 142 is oxidized, resulting in an oxide layer 143 on each side. However, since the upper surfaces of the data line, source 141, and drain 142 are covered with an insulating layer 15, oxidation of the copper on the upper surfaces of these components is effectively prevented.

[0088] In the above process, since the copper on the sides of the data line, source 141, and drain 142 is oxidized, metal ions are less likely to penetrate out from the sides of the data line, source 141, and drain 142, effectively suppressing copper ion diffusion and better ensuring the characteristic curve of the TFT. Since the above plasma treatment steps can only be performed in a CVD machine, and photoresist is prone to contaminating the CVD machine, photoresist cannot be used as a barrier layer. Using an insulating layer 15 effectively avoids this problem, preventing the copper on the upper surfaces of the data line, source 141, and drain 142 from oxidation. This prevents poor conductive contact when the pixel electrode 231 is connected to the drain 142 in subsequent processes.

[0089] The above process can be matched with the existing production process and can produce back-channel etched MOS-TFTs based on copper traces. Since copper has the advantage of low impedance, it can simultaneously reduce the resistance-capacitance (RC) delay of the metal traces and the charging time required by the device. When combined with metal oxide, it can provide high resolution and low power consumption, which is suitable for high-end and high-specification products. At the same time, with the use of halftone photomasks, when etching the second metal layer 14 and etching the metal oxide semiconductor layer 13, the etching of the two layers can share the same photomask, which can reduce the number of photomasks used, reduce costs, save process time, and improve production efficiency.

[0090] Further, please refer to Figures 21 to 20 The manufacturing method also includes:

[0091] A first passivation layer 16 covering the isolation insulating layer 15 is formed on the gate insulating layer 12;

[0092] A planarization layer 17 is formed on the first passivation layer 16, and the planarization layer 17 is patterned so that a through-hole is formed in the planarization layer 17 at a position corresponding to the drain electrode 142, exposing the underlying first passivation layer 16, as shown. Figure 2l As shown;

[0093] A first transparent conductive layer 18 is formed on the planarization layer 17, and the first transparent conductive layer 18 is etched and patterned so that the first transparent conductive layer 18 is etched to form a common electrode 181, such as... Figure 2m As shown;

[0094] A second passivation layer 19 covering the common electrode 181 is formed on the planarization layer 17, and the second passivation layer 19, the first passivation layer 16, and the isolation insulating layer 15 are simultaneously etched and patterned. A contact hole 191 is formed at a position corresponding to the drain electrode 142, penetrating the second passivation layer 19, the first passivation layer 16, and the isolation insulating layer 15, so that the drain electrode 142 is exposed through the contact hole 191. Figure 2n As shown;

[0095] A second transparent conductive layer 23 is formed on the second passivation layer 19, and the second transparent conductive layer 23 is etched and patterned so that the second transparent conductive layer 23 is etched to form a pixel electrode 231, wherein the pixel electrode 231 is filled into the contact hole 191 and electrically connected to the drain 142, such as Figure 2o As shown. In the plasma processing step described above, since the insulating layer 15 covers the data line, source 141 and drain 142, the presence of the insulating layer 15 effectively prevents the copper metal on the upper surface of the data line, source 141 and drain 142 from being oxidized. Therefore, the pixel electrode 231 can make good conductive contact with the drain 142.

[0096] After the above process, a metal oxide thin-film transistor array substrate with a back-channel etched MOS-TFT is finally formed, such as... Figure 1 As shown.

[0097] Specifically, the gate insulating layer 12, the isolation insulating layer 15, the first passivation layer 16, and the second passivation layer 19 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a composite layer of silicon nitride and silicon oxide, etc. The isolation insulating layer 15 and the first passivation layer 16 use the same material, for example, both being silicon oxide (SiOx). This avoids undercutting caused by inconsistent etching rates between the two different materials when forming the contact hole 191. The metal oxide semiconductor layer 13 can be made of indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc. The first transparent conductive layer 18 and the second transparent conductive layer 23 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0098] [Second Embodiment]

[0099] Figure 3 This is a partial cross-sectional schematic diagram of the metal oxide thin-film transistor array substrate in the second embodiment of the present invention, as shown below. Figure 3 As shown, a second embodiment of the present invention provides a metal oxide thin-film transistor array substrate, comprising: a substrate 10; a scan line (not shown) and a gate 111 formed by etching a first metal layer 11 on the substrate 10. The gate 111 is connected to the scan line or is part of the scan line; a gate insulating layer 12 covering the scan line and the gate 111; and a metal oxide semiconductor layer 13, a second metal layer 14, and an isolation insulating layer 15 sequentially disposed on the gate insulating layer 12.

[0100] The second metal layer 14 includes a copper layer. The isolation insulating layer 15, the second metal layer 14, and the metal oxide semiconductor layer 13 are all etched and patterned. After the second metal layer 14 is etched, it forms data lines and source electrodes 141 and drain electrodes 142 that are spaced apart from each other. After the metal oxide semiconductor layer 13 is etched, it forms a semiconductor active layer 131 at the channel position. The etched isolation insulating layer 15 is stacked vertically with the data lines, source electrodes 141, and drain electrodes 142. The metal oxide semiconductor layer 13 is stacked below the data lines, source electrodes 141, and drain electrodes 142. The copper exposed on the sides of the data lines, source electrodes 141, and drain electrodes 142 is oxidized to form an oxide layer 143.

[0101] Specifically, the second metal layer 14 can be a single-layer structure containing only a copper layer, or a multi-layer structure containing a copper layer. For example, the top layer of the second metal layer 14 is a copper layer, and the bottom layer is a molybdenum (Mo) or molybdenum-niobium alloy (MoNb) layer.

[0102] Specifically, a halftone mask (HTM) can be used to expose the coated photoresist layer on the isolation insulating layer 15. In a half tone mask process, the same photoresist is used as a mask to sequentially etch and pattern the isolation insulating layer 15, the second metal layer 14, and the metal oxide semiconductor layer 13, so that in addition to forming a semiconductor active layer 131 at the channel position, the metal oxide semiconductor layer 13 is also stacked below the data line, the source 141, and the drain 142.

[0103] In this embodiment, the pattern of the isolation insulating layer 15 after etching is the same as the pattern formed by the data line, the source 141 and the drain 142 together (that is, the isolation insulating layer 15 is only covered directly above the data line, the source 141 and the drain 142 in the panel, and there is no isolation insulating layer 15 in other positions). The etched isolation insulating layer 15 is arranged vertically overlapping the data line, the source 141 and the drain 142.

[0104] Specifically, after forming the data line, source 141, and drain 142, plasma (e.g., N2O, O2) can be used to oxidize the exposed sides of the data line, source 141, and drain 142 to form an oxide layer 143 on each of the exposed sides. Due to the strong oxidizing properties of plasma, the exposed copper metal on the sides of the data line, source 141, and drain 142 will be oxidized, thus forming an oxide layer 143 on each of the sides of the data line, source 141, and drain 142. However, since the upper surfaces of the data line, source 141, and drain 142 are covered with an insulating layer 15, the oxidation of the copper metal on the upper surfaces of the data line, source 141, and drain 142 can be effectively prevented. Since the copper on the sides of the data line, source 141, and drain 142 is oxidized, metal ions are less likely to penetrate from the sides of these components, effectively suppressing copper ion diffusion and better ensuring the characteristic curve of the TFT. Simultaneously, the presence of the insulating layer 15 prevents the copper on the upper surfaces of the data line, source 141, and drain 142 from oxidizing, thus avoiding poor conductive contact issues when the pixel electrode 231 is connected to the drain 142 in subsequent processes.

[0105] In this embodiment, plasma can also be used to simultaneously treat the channel region of the semiconductor active layer 131 to improve the damage condition of the semiconductor active layer 131. After plasma treatment, the damage to the film on the surface of the semiconductor active layer 131 can be improved, resulting in a better contact interface between the semiconductor active layer 131 and the first passivation layer 16 when the first passivation layer 16 is applied in subsequent processes.

[0106] This embodiment can be matched with the existing production process and can fabricate back-channel etched MOS-TFTs based on copper traces. Since copper has the advantage of low impedance, it can simultaneously reduce the resistance-capacitance (RC) delay of the metal traces and the charging time required by the device. When combined with metal oxide, it can provide high resolution and low power consumption, which is suitable for high-end and high-specification products. At the same time, with the use of halftone photomasks, the etching of the isolation insulating layer 15, the second metal layer 14 and the metal oxide semiconductor layer 13 can all share the same photomask, which can reduce the number of photomasks used, greatly reduce costs, save process time and improve production efficiency.

[0107] Furthermore, the metal oxide thin-film transistor array substrate further includes: a first passivation layer 16 covering an isolation insulating layer 15 and a semiconductor active layer 131 on the gate insulating layer 12; a planarization layer 17 on the first passivation layer 16; a common electrode 181 formed by etching a first transparent conductive layer 18 on the planarization layer 17; a second passivation layer 19 covering the common electrode 181, wherein a contact hole 191 is formed through the second passivation layer 19, the planarization layer 17, the first passivation layer 16 and the isolation insulating layer 15 at a position corresponding to the drain 142; and a pixel electrode 231 formed by etching a second transparent conductive layer 23 on the second passivation layer 19, wherein the pixel electrode 231 is filled in the contact hole 191 and electrically connected to the drain 142.

[0108] In the plasma processing steps described above, since the insulating layer 15 covers the data line, source 141 and drain 142, the presence of the insulating layer 15 effectively prevents the copper metal on the upper surface of the data line, source 141 and drain 142 from being oxidized. Therefore, the pixel electrode 231 can make good conductive contact with the drain 142.

[0109] Specifically, the gate insulating layer 12, the isolation insulating layer 15, the first passivation layer 16, and the second passivation layer 19 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a composite layer of silicon nitride and silicon oxide, etc. The isolation insulating layer 15 and the first passivation layer 16 use the same material, for example, both being silicon oxide (SiOx). This avoids undercutting caused by inconsistent etching rates between the two different materials when forming the contact hole 191. The metal oxide semiconductor layer 13 can be made of indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc. The first transparent conductive layer 18 and the second transparent conductive layer 23 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0110] Figures 4a to 4p for Figure 3 A cross-sectional schematic diagram of the fabrication process of a metal-oxide-slim thin-film transistor array substrate, as shown below. Figures 4a to 4p As shown, the second embodiment of the present invention also provides a method for fabricating a metal oxide thin-film transistor array substrate. Specifically, the method includes:

[0111] Please refer to Figure 4a A first metal layer 11 is formed on the substrate 10, and the first metal layer 11 is etched and patterned so that the first metal layer 11 is etched to form a scan line (not shown) and a gate 111. The gate 111 is connected to the scan line or is part of the scan line.

[0112] Please refer to Figure 4bA gate insulating layer 12, a metal oxide semiconductor layer 13, a second metal layer 14, and an isolation insulating layer 15 covering the scan line and the gate 111 are sequentially and continuously formed on the substrate 10, wherein the second metal layer 14 includes a copper layer. Specifically, the second metal layer 14 can be a single-layer structure containing only a copper layer, or it can be a multi-layer structure containing copper layers. For example, the top layer of the second metal layer 14 is a copper layer, and the bottom layer is a molybdenum (Mo) or molybdenum-niobium alloy (MoNb) layer.

[0113] Please refer to Figure 4c A photoresist layer 20 is coated on the insulating layer 15.

[0114] Please refer to Figure 4d The photoresist layer 20 is exposed and developed using a halftone mask 30 (HTM), leaving a first photoresist pattern 21 and a second photoresist pattern 22 on the photoresist layer 20. Other areas without photoresist are exposed, revealing the insulating layer 15. The thickness of the first photoresist pattern 21 is greater than the thickness of the second photoresist pattern 22. The first photoresist pattern 21 corresponds to the positions of the data line, source 141, and drain 142, while the second photoresist pattern 22 corresponds to the position of the channel region. Except for the first and second photoresist patterns 21 and 22, other areas have no photoresist and expose the insulating layer 15.

[0115] Specifically, the halftone mask 30 includes an opaque area 31, a semi-transparent area 32, and a fully transparent area 33, wherein the opaque area 31, the semi-transparent area 32, and the fully transparent area 33 correspond to the first photoresist pattern 21, the second photoresist pattern 22, and other areas where no photoresist needs to be left, respectively. In this way, after exposure and development, the photoresist layer 20 can leave the first photoresist pattern 21 and the second photoresist pattern 22, and the thickness of the first photoresist pattern 21 is greater than the thickness of the second photoresist pattern 22.

[0116] Please refer to Figure 4e Using the first photoresist pattern 21 and the second photoresist pattern 22 as a mask, the insulating layer 15 is etched and patterned to remove the exposed insulating layer 15. After the insulating layer 15 is etched for the first time, the underlying second metal layer 14 is exposed. Specifically, the insulating layer 15 can be etched and patterned first using a dry etching method.

[0117] Please refer to Figure 4f The second metal layer 14 is then etched and patterned using the first photoresist pattern 21 and the second photoresist pattern 22 as shielding elements. This removes the exposed second metal layer 14, and after the second metal layer 14 is etched for the first time, data lines are formed, exposing the underlying metal oxide semiconductor layer 13. Specifically, the second metal layer 14 can be etched and patterned using a first etchant, such as copper acid, which contains hydrogen peroxide.

[0118] Please refer to Figure 4g The metal oxide semiconductor layer 13 is then etched and patterned using the first photoresist pattern 21 and the second photoresist pattern 22 as shielding elements, removing any exposed metal oxide semiconductor layer 13. Specifically, a second etchant, such as aluminic acid or oxalic acid, can be used to etch and pattern the metal oxide semiconductor layer 13.

[0119] Please refer to Figure 4h The second photoresist pattern 22 is removed using photoresist ashing to expose the insulating layer 15 at the channel location, but the first photoresist pattern 21 remains. It should be noted that during the photoresist ashing process, the first photoresist pattern 21 is also thinned, but since the first photoresist pattern 21 is thicker than the second photoresist pattern 22, the first photoresist pattern 21 still covers the positions corresponding to the data line, source 141, and drain 142 after thinning.

[0120] Please refer to Figure 4i Using the first photoresist pattern 21 as a mask, the insulating layer 15 at the channel position is etched and patterned to remove the insulating layer 15 exposed at the channel position. After the insulating layer 15 is etched a second time, the second metal layer 14 below is exposed at the channel position. Specifically, the insulating layer 15 at the channel position can be etched and patterned first using a dry etching method.

[0121] Please refer to Figure 4j Using the first photoresist pattern 21 as a mask, the second metal layer 14 at the channel location is etched and patterned to remove the exposed second metal layer 14 at the channel location. After the second etching, the second metal layer 14 forms a source electrode 141 and a drain electrode 142 that are spaced apart from each other, exposing the underlying semiconductor active layer 131 at the channel location. The pattern of the isolation insulating layer 15 after the two etchings is the same as the pattern formed by the data lines, source electrode 141, and drain electrode 142 (that is, the isolation insulating layer 15 is only covered directly above the data lines, source electrode 141, and drain electrode 142 in the panel, and there is no isolation insulating layer 15 in other locations). The sides of the data lines, source electrode 141, and drain electrode 142 formed by the second metal layer 14 after the two etchings are exposed. Specifically, the second metal layer 14 at the channel location is etched and patterned using the first etching solution to remove the exposed second metal layer 14 at the channel location. In this configuration, source 141 is connected to the data line or is part of the data line, and source 141 and drain 142 are spaced apart from each other.

[0122] In the above process, since the same photoresist is used as a mask in a half-tone photomask process to sequentially etch and pattern the isolation insulating layer 15, the second metal layer 14 and the metal oxide semiconductor layer 13, the pattern of the isolation insulating layer 15 after etching is the same as the pattern formed by the data line, the source 141 and the drain 142 together (that is, the isolation insulating layer 15 is only covered directly above the data line, the source 141 and the drain 142 in the panel, and there is no isolation insulating layer 15 in other positions). The etched isolation insulating layer 15 is stacked vertically with the data line, the source 141 and the drain 142. In addition to forming the semiconductor active layer 131 at the channel position, the metal oxide semiconductor layer 13 is also stacked below the data line, the source 141 and the drain 142.

[0123] Please refer to Figure 4k After forming the data line, source 141 and drain 142, the first photoresist pattern 21 is removed.

[0124] Please refer to Figure 4l The exposed sides of the data line, source 141, and drain 142 are oxidized using plasma (e.g., N2O, O2), causing the exposed copper metal on these sides to oxidize and form an oxide layer 143. Due to the strong oxidizing properties of plasma, the exposed copper metal on the sides of the data line, source 141, and drain 142 is oxidized, resulting in an oxide layer 143 on each side. However, since the upper surfaces of the data line, source 141, and drain 142 are covered with an insulating layer 15, oxidation of the copper metal on the upper surfaces of these components is effectively prevented.

[0125] Since the copper on the sides of the data line, source 141, and drain 142 is oxidized, metal ions are less likely to penetrate from the sides of these components, effectively suppressing copper ion diffusion and better ensuring the characteristic curve of the TFT. Because the plasma treatment steps described above can only be performed in a CVD machine, photoresist cannot be used as a barrier layer. The presence of the insulating layer 15 effectively avoids this problem, preventing the copper on the upper surfaces of the data line, source 141, and drain 142 from oxidizing. This ensures that there will be no poor conductive contact when the pixel electrode 231 is connected to the drain 142 in subsequent processes.

[0126] Furthermore, in back-channel etched MOS-TFTs, the channel region where the semiconductor active layer 131 is located is easily damaged by the etching solution used to form the source 141 and drain 142 during the formation of the source 141 and drain 142. In this embodiment, plasma can be used to simultaneously treat the channel region of the semiconductor active layer 131 to improve its damage condition. Specifically, treating the channel region of the semiconductor active layer 131 with plasma means using active oxygen ions in the plasma to fill the dangling bonds formed in the semiconductor active layer 131 (such as IGZO) after oxygen ions are removed by H, thereby repairing the electrical characteristics of the metal oxide semiconductor as the semiconductor active layer 131. After plasma treatment, the channel region of the semiconductor active layer 131 can improve the film damage problem on the surface of the semiconductor active layer 131, resulting in a better contact interface between the semiconductor active layer 131 and the first passivation layer 16 when the first passivation layer 16 is applied in subsequent processes.

[0127] The above process can be matched with the existing production process and can produce back-channel etched MOS-TFTs based on copper traces. Since copper has the advantage of low impedance, it can simultaneously reduce the resistance-capacitance (RC) delay of the metal traces and the charging time required by the device. When combined with metal oxide, it can provide high resolution and low power consumption, which is suitable for high-end and high-specification products. At the same time, with the use of halftone photomasks, the etching of the isolation insulating layer 15, the second metal layer 14 and the metal oxide semiconductor layer 13 can all share the same photomask, which can reduce the number of photomasks used, greatly reduce costs, save process time and improve production efficiency.

[0128] Further, please refer to Figures 4m to 4p The manufacturing method also includes:

[0129] A first passivation layer 16 is formed on the gate insulating layer 12, covering the isolation insulating layer 15 and the semiconductor active layer 131;

[0130] A planarization layer 17 is formed on the first passivation layer 16, and the planarization layer 17 is patterned so that a through-hole is formed in the planarization layer 17 at a position corresponding to the drain electrode 142, exposing the underlying first passivation layer 16, as shown. Figure 4m As shown;

[0131] A first transparent conductive layer 18 is formed on the planarization layer 17, and the first transparent conductive layer 18 is etched and patterned so that the first transparent conductive layer 18 is etched to form a common electrode 181, such as... Figure 4n As shown;

[0132] A second passivation layer 19 covering the common electrode 181 is formed on the planarization layer 17, and the second passivation layer 19, the first passivation layer 16, and the isolation insulating layer 15 are simultaneously etched and patterned. A contact hole 191 is formed at a position corresponding to the drain electrode 142, penetrating the second passivation layer 19, the first passivation layer 16, and the isolation insulating layer 15, so that the drain electrode 142 is exposed through the contact hole 191. Figure 4o As shown;

[0133] A second transparent conductive layer 23 is formed on the second passivation layer 19, and the second transparent conductive layer 23 is etched and patterned so that the second transparent conductive layer 23 is etched to form a pixel electrode 231, wherein the pixel electrode 231 is filled into the contact hole 191 and electrically connected to the drain 142, such as Figure 4p As shown. In the plasma processing step described above, since the insulating layer 15 covers the data line, source 141 and drain 142, the presence of the insulating layer 15 effectively prevents the copper metal on the upper surface of the data line, source 141 and drain 142 from being oxidized. Therefore, the pixel electrode 231 can make good conductive contact with the drain 142.

[0134] After the above process, a metal oxide thin-film transistor array substrate with a back-channel etched MOS-TFT is finally formed, such as... Figure 3 As shown. Compared to the first embodiment described above, in this embodiment, the isolation insulating layer 15 is no longer etched separately, but is etched together with the second metal layer 14 and the metal oxide semiconductor layer 13 in a single half-tone photomask process. This saves one etching process, further reducing costs and processing time.

[0135] Specifically, the gate insulating layer 12, the isolation insulating layer 15, the first passivation layer 16, and the second passivation layer 19 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a composite layer of silicon nitride and silicon oxide, etc. The isolation insulating layer 15 and the first passivation layer 16 use the same material, for example, both being silicon oxide (SiOx). This avoids undercutting caused by inconsistent etching rates between the two different materials when forming the contact hole 191. The metal oxide semiconductor layer 13 can be made of indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc. The first transparent conductive layer 18 and the second transparent conductive layer 23 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0136] Figure 5 This is a partial cross-sectional schematic diagram of the peripheral region of the metal oxide thin-film transistor array substrate in Embodiment 1 or Embodiment 2 of the present invention. Please refer to... Figure 5The metal oxide thin-film transistor array substrate includes a display area and a peripheral area surrounding the display area. The peripheral area is provided with a wire structure electrically connected to the circuit board. The wire structure of the peripheral area is also fabricated during the fabrication of the display area. Specifically, the peripheral area includes: a first wire 112 formed by etching and patterning a first metal layer 11 on the substrate 10, a second wire 144 formed by etching a second metal layer 14, and a connecting line 232 formed by etching and patterning a second transparent conductive layer 23. When forming the contact hole 191, contact holes are simultaneously formed at positions corresponding to the first wire 112 and the second wire 144 to expose the first wire 112 and the second wire 144. When forming the connecting line 232, the connecting line 232 is filled into the contact hole to connect the first wire 112 and the second wire 144. In the surrounding area, since the copper metal on the side of the second conductor 144 is oxidized, metal ions are not easy to penetrate out from the side of the second conductor 144, which can effectively inhibit the diffusion of copper ions. In addition, the insulating layer 15 prevents the copper metal on the upper surface of the second conductor 144 from being oxidized, so there will be no problems such as poor conductive contact when the connecting wire 232 is connected.

[0137] The present invention also provides a display panel, comprising the aforementioned metal oxide thin-film transistor array substrate. Specifically, the display panel may be a liquid crystal display panel.

[0138] The above specific examples illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. For those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A metal oxide thin-film transistor array substrate, characterized in that, include: Substrate (10); The scan lines and gate (111) are patterned by etching the first metal layer (11) on the substrate (10); Gate insulating layer (12) covering the scan line and the gate (111); A metal oxide semiconductor layer (13), a second metal layer (14), and an isolation insulating layer (15) are sequentially disposed on the gate insulating layer (12); The isolation insulating layer (15), the second metal layer (14), and the metal oxide semiconductor layer (13) are all etched and patterned. After the second metal layer (14) is etched, it forms data lines and source (141) and drain (142) spaced apart from each other. After the metal oxide semiconductor layer (13) is etched, it forms a semiconductor active layer (131) at the channel position. The etched isolation insulating layer (15) is stacked vertically with the data lines, the source (141), and the drain (142). The metal oxide semiconductor layer (13) is stacked below the data lines, the source (141), and the drain (142). The sides of the data lines, the source (141), and the drain (142) are oxidized to form an oxide layer (143).

2. The metal oxide thin-film transistor array substrate as described in claim 1, characterized in that, The isolation insulating layer (15) also covers the semiconductor active layer (131). The pattern of the isolation insulating layer (15) after etching is the same as the pattern formed by the data line, the source (141), the drain (142) and the semiconductor active layer (131).

3. The metal oxide thin-film transistor array substrate as described in claim 2, characterized in that, The metal oxide thin-film transistor array substrate also includes: A first passivation layer (16) is located on the gate insulating layer (12) and covers the isolation insulating layer (15); A planarization layer (17) located on the first passivation layer (16); A common electrode (181) is formed by etching a first transparent conductive layer (18) on the planar layer (17); A second passivation layer (19) covering the common electrode (181) has a contact hole (191) formed through the second passivation layer (19), the planarization layer (17), the first passivation layer (16) and the isolation insulating layer (15) at a position corresponding to the drain electrode (142). A pixel electrode (231) is formed by etching a second transparent conductive layer (23) on the second passivation layer (19), wherein the pixel electrode (231) is filled in the contact hole (191) and electrically connected to the drain electrode (142).

4. The metal oxide thin-film transistor array substrate as described in claim 1, characterized in that, The pattern of the insulating layer (15) after etching is the same as the pattern formed by the data line, the source (141) and the drain (142).

5. The metal oxide thin-film transistor array substrate as described in claim 4, characterized in that, The metal oxide thin-film transistor array substrate also includes: A first passivation layer (16) is located on the gate insulating layer (12) covering the isolation insulating layer (15) and the semiconductor active layer (131); A planarization layer (17) located on the first passivation layer (16); A common electrode (181) is formed by etching a first transparent conductive layer (18) on the planar layer (17); A second passivation layer (19) covering the common electrode (181) has a contact hole (191) formed through the second passivation layer (19), the planarization layer (17), the first passivation layer (16) and the isolation insulating layer (15) at a position corresponding to the drain electrode (142). A pixel electrode (231) is formed by etching a second transparent conductive layer (23) on the second passivation layer (19), wherein the pixel electrode (231) is filled in the contact hole (191) and electrically connected to the drain electrode (142).

6. A method for fabricating a metal oxide thin-film transistor array substrate, characterized in that, include: A first metal layer (11) is formed on a substrate (10), and the first metal layer (11) is etched and patterned so that the first metal layer (11) is etched to form scan lines and gates (111); A gate insulating layer (12), a metal oxide semiconductor layer (13), and a second metal layer (14) covering the scan line and the gate (111) are sequentially and continuously formed on the substrate (10); A photoresist layer (20) is coated on the second metal layer (14); The photoresist layer (20) is exposed and developed using a halftone photomask (30) to leave a first photoresist pattern (21) and a second photoresist pattern (22) on the photoresist layer (20). Other areas where no photoresist is left are exposed to reveal the second metal layer (14). The thickness of the first photoresist pattern (21) is greater than the thickness of the second photoresist pattern (22). The first photoresist pattern (21) corresponds to the positions of the data line, the source (141) and the drain (142), and the second photoresist pattern (22) corresponds to the position of the channel region. Using the first photoresist pattern (21) and the second photoresist pattern (22) as a shield, the second metal layer (14) is etched and patterned to remove the exposed second metal layer (14). After the second metal layer (14) is etched for the first time, a data line is formed and the underlying metal oxide semiconductor layer (13) is exposed. Using the first photoresist pattern (21) and the second photoresist pattern (22) as a mask, the metal oxide semiconductor layer (13) is etched and patterned to remove the exposed metal oxide semiconductor layer (13), so that the metal oxide semiconductor layer (13) is etched and a semiconductor active layer (131) is formed at the channel position. The second photoresist pattern (22) is removed by photoresist ashing to expose the second metal layer (14) at the channel location, but the first photoresist pattern (21) remains. Using the first photoresist pattern (21) as a shield, the second metal layer (14) at the channel position is etched and patterned to remove the second metal layer (14) exposed at the channel position. After the second metal layer (14) is etched for the second time, it forms a source (141) and a drain (142) that are spaced apart from each other, and exposes the semiconductor active layer (131) below at the channel position. After the second metal layer (14) is etched twice, the sides of the data line, the source (141) and the drain (142) formed are exposed. After forming the data line, the source (141) and the drain (142), the first photoresist pattern (21) is removed; An isolation insulating layer (15) is formed on the gate insulating layer (12) to cover the data line, the source (141), the drain (142) and the semiconductor active layer (131), and the isolation insulating layer (15) is etched and patterned so that the pattern of the isolation insulating layer (15) after etching is the same as the pattern formed by the data line, the source (141), the drain (142) and the semiconductor active layer (131), and the sides of the data line, the source (141) and the drain (142) are still exposed; The exposed sides of the data line, the source (141) and the drain (142) are oxidized using plasma, so that the sides of the data line, the source (141) and the drain (142) are oxidized to form an oxide layer (143).

7. The method for fabricating a metal oxide thin-film transistor array substrate as described in claim 6, characterized in that, The production method also includes: A first passivation layer (16) covering the isolation insulating layer (15) is formed on the gate insulating layer (12); A planarization layer (17) is formed on the first passivation layer (16), and the planarization layer (17) is patterned so that the planarization layer (17) forms a perforation at a position corresponding to the drain electrode (142) and exposes the underlying first passivation layer (16). A first transparent conductive layer (18) is formed on the planar layer (17), and the first transparent conductive layer (18) is etched and patterned so that the first transparent conductive layer (18) is etched to form a common electrode (181). A second passivation layer (19) covering the common electrode (181) is formed on the planar layer (17), and the second passivation layer (19), the first passivation layer (16) and the isolation insulating layer (15) are simultaneously etched and patterned. A contact hole (191) is formed at a position corresponding to the drain electrode (142) and penetrates the second passivation layer (19), the first passivation layer (16) and the isolation insulating layer (15) so that the drain electrode (142) is exposed through the contact hole (191). A second transparent conductive layer (23) is formed on the second passivation layer (19), and the second transparent conductive layer (23) is etched and patterned so that the second transparent conductive layer (23) is etched to form a pixel electrode (231), wherein the pixel electrode (231) is filled into the contact hole (191) and electrically connected to the drain electrode (142).

8. A method for fabricating a metal oxide thin-film transistor array substrate, characterized in that, include: A first metal layer (11) is formed on a substrate (10), and the first metal layer (11) is etched and patterned so that the first metal layer (11) is etched to form scan lines and gates (111); A gate insulating layer (12), a metal oxide semiconductor layer (13), a second metal layer (14), and an isolation insulating layer (15) covering the scan line and the gate (111) are sequentially and continuously formed on the substrate (10); A photoresist layer (20) is coated on the insulating layer (15); The photoresist layer (20) is exposed and developed using a halftone photomask (30) to leave a first photoresist pattern (21) and a second photoresist pattern (22) on the photoresist layer (20). Other areas where no photoresist is left are exposed to the insulating layer (15). The thickness of the first photoresist pattern (21) is greater than the thickness of the second photoresist pattern (22). The first photoresist pattern (21) corresponds to the position of the data line, the source (141) and the drain (142), and the second photoresist pattern (22) corresponds to the position of the channel region. Using the first photoresist pattern (21) and the second photoresist pattern (22) as a mask, the isolation insulating layer (15) is etched and patterned to remove the exposed isolation insulating layer (15), and after the isolation insulating layer (15) is etched for the first time, the second metal layer (14) underneath is exposed. Using the first photoresist pattern (21) and the second photoresist pattern (22) as a shield, the second metal layer (14) is etched and patterned to remove the exposed second metal layer (14). After the second metal layer (14) is etched for the first time, a data line is formed and the underlying metal oxide semiconductor layer (13) is exposed. Using the first photoresist pattern (21) and the second photoresist pattern (22) as a mask, the metal oxide semiconductor layer (13) is etched and patterned to remove the exposed metal oxide semiconductor layer (13), so that the metal oxide semiconductor layer (13) is etched and a semiconductor active layer (131) is formed at the channel position. The second photoresist pattern (22) is removed by photoresist ashing to expose the insulating layer (15) at the channel location, but the first photoresist pattern (21) remains. Using the first photoresist pattern (21) as a mask, the isolation insulating layer (15) at the channel position is etched and patterned to remove the isolation insulating layer (15) exposed at the channel position, and after the isolation insulating layer (15) is etched for the second time, the second metal layer (14) below is exposed at the channel position. Using the first photoresist pattern (21) as a shield, the second metal layer (14) at the channel position is etched and patterned to remove the second metal layer (14) exposed at the channel position. After the second etching, the second metal layer (14) forms a source (141) and a drain (142) that are spaced apart from each other, and exposes the semiconductor active layer (131) below at the channel position. The pattern of the isolation insulating layer (15) after two etchings is the same as the pattern formed by the data line, the source (141) and the drain (142). The sides of the data line, the source (141) and the drain (142) formed by the second metal layer (14) after two etchings are exposed. After forming the data line, the source (141) and the drain (142), the first photoresist pattern (21) is removed; The exposed sides of the data line, the source (141) and the drain (142) are oxidized using plasma, so that the sides of the data line, the source (141) and the drain (142) are oxidized to form an oxide layer (143).

9. The method for fabricating a metal oxide thin-film transistor array substrate as described in claim 8, characterized in that, The production method also includes: A first passivation layer (16) is formed on the gate insulating layer (12) to cover the isolation insulating layer (15) and the semiconductor active layer (131); A planarization layer (17) is formed on the first passivation layer (16), and the planarization layer (17) is patterned so that the planarization layer (17) forms a perforation at a position corresponding to the drain electrode (142) and exposes the underlying first passivation layer (16). A first transparent conductive layer (18) is formed on the planar layer (17), and the first transparent conductive layer (18) is etched and patterned so that the first transparent conductive layer (18) is etched to form a common electrode (181). A second passivation layer (19) covering the common electrode (181) is formed on the planar layer (17), and the second passivation layer (19), the first passivation layer (16) and the isolation insulating layer (15) are simultaneously etched and patterned. A contact hole (191) is formed at a position corresponding to the drain electrode (142) and penetrates the second passivation layer (19), the first passivation layer (16) and the isolation insulating layer (15) so that the drain electrode (142) is exposed through the contact hole (191). A second transparent conductive layer (23) is formed on the second passivation layer (19), and the second transparent conductive layer (23) is etched and patterned so that the second transparent conductive layer (23) is etched to form a pixel electrode (231), wherein the pixel electrode (231) is filled in the contact hole (191) and electrically connected to the drain electrode (142).

10. A display panel, characterized in that, Includes the metal oxide thin-film transistor array substrate as described in any one of claims 1-5.

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