A trench type MOSFET cell structure and a method for manufacturing the same

Abstract

This invention discloses a trench-type MOSFET cell structure, comprising: a gate trench, an auxiliary source trench, and an N-type MOSFET. + Source region, P-type base region, P + Buried layer, N drift layer, N + Substrate, wherein N + The source region is located above the P-type base region and is partially enclosed by the P-type base region. The P-type base region is located above the N-drift layer, and the N-drift layer is located above the N-type base region. + Above the substrate, a gate trench vertically penetrates N. + The source region and P-type base region extend into the N-drift layer, and the auxiliary source trench vertically penetrates the P-type base region and extends into the N-drift layer. + The buried layer is located beneath the gate trench and auxiliary source trench and is encased by an N-drift layer, P + The buried layer located below the gate trench is discontinuous in the direction parallel to the gate trench and is spatially periodically distributed. The bottom of the auxiliary source trench is adjacent to the P... + The buried layer makes direct contact, and an ohmic contact metal layer is provided at the bottom of the auxiliary source trench. A diode is integrated into the sidewall of the auxiliary source trench. This invention increases the conductivity of the device and reduces conduction losses.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a trench MOSFET cell structure with better dual-sided conduction capability and its fabrication method. Background Technology

[0002] SiC material is highly attractive for high-power applications due to its excellent properties, making it one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and UMOSFETs with vertical gate trench structures. The DMOSFET structure employs planar diffusion technology, using a refractory material such as a polysilicon gate as a mask, and defining the P-type base region and N-type region by the edge of the polysilicon gate. + Source region, utilizing P-type base region and N + The lateral diffusion difference in the source region forms the surface channel region. The vertical gate trench structure of the UMOSFET, named after the U-shaped trench structure, is formed in the gate region using reactive ion etching. The high channel density of the U-shaped trench structure significantly reduces the on-state characteristic resistance of the device. After years of research in the industry, some manufacturers have already launched commercial products of planar SiC MOSFETs. For the ordinary lateral DMOSFET structure, modern technological advancements have reached a point where shrinking the MOS cell size cannot reduce the on-resistance, mainly due to the limitation of the JFET neck resistance. Even with smaller photolithography dimensions, it is difficult to reduce the on-resistance per unit area to 2mΩ·cm. 2 The trench structure can effectively solve this problem. The U-shaped trench structure uses the trench etching technology invented in the manufacturing process of memory capacitors, which changes the conductive channel from horizontal to vertical. Compared with the ordinary structure, it eliminates the neck resistance of JFET, greatly increases the cell density, and improves the current handling capability of power semiconductors.

[0003] However, several problems still exist in the actual fabrication and application of SiC UMOSFETs: First, the high electric field in the SiC drift region leads to a very high electric field on the gate oxide layer. This problem is exacerbated at the slot corner, resulting in rapid breakdown of the gate oxide layer under high drain voltage. This also leads to poor resistance to electrostatic discharge (ESD) in harsh environments and high-voltage spikes in the circuit. Second, since SiC power MOSFETs are mainly used in high-voltage, high-frequency, and high-current applications, parasitic parameters in the circuit can cause spikes such as overshoot during high-frequency switching, resulting in instantaneous overvoltage in the device's current path and increasing switching losses. Furthermore, changes in power load can generate large surge voltages. Therefore, the surge voltage resistance and overvoltage protection of MOSFETs are also crucial. Because existing MOSFET devices do not inherently possess surge voltage self-suppression and overvoltage protection capabilities, complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits are often required in practical applications. However, such external matching suppression and overvoltage protection circuits often have time delays. In actual switching processes, high-frequency peak voltage surges are still borne by the device itself, which can sometimes lead to breakdown failure in the device channel region, as well as gradual failure of the gate structure and electrode ohmic contact areas, causing device reliability issues. In addition, due to the limited ion implantation depth, many targeted trench gate protection structures and surge protection designs are difficult to implement from a manufacturing perspective.

[0004] To better protect the gate oxide layer of trench MOSFETs, especially the bottom and trench corners, the industry mainly employs three technical solutions and device structures for SiC trench MOSFETs. These include the dual-trench source structure constructed on both sides of the gate trench by Rohm of Japan to shield the bottom of the middle gate trench, and the P-type structure used by Infineon of Germany. + The semi-enclosed asymmetric trench structure, adopted by Sumitomo Chemical in Japan, involves constructing P-type terminals connected to the source on both sides below the bottom of the trench gate. + Buried structure. In actual device fabrication and product applications, Infineon's semi-enclosed trench MOSFETs exhibit better trench gate bottom protection and reliability. Device structure analysis and TCAD simulation also demonstrate the superior protection capabilities of the bottom and trench side P-type structures. + The semi-enclosed protection method can create better trench gate electric field shielding. However, using Infineon's semi-enclosed trench structure means that the trench MOSFET can only conduct through one side of the channel, while the other side is used to construct the P-channel. + The shielding layer sacrifices the conductive trench, resulting in increased conduction losses in the device unit. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a trench MOSFET cell structure with better dual-sided conduction capability, thereby reducing conduction losses and improving device performance.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A trench-type MOSFET cell structure includes: a gate trench, an auxiliary source trench, and an N-type gate trench. + Source region, P-type base region, P + Buried layer, N drift layer, N + Substrate, wherein the N + The source region is located above the P-type base region and is partially enclosed by the P-type base region. The P-type base region is located above the N-drift layer, and the N-drift layer is located above the N-type base region. + Above the substrate, the gate trench vertically penetrates the N + The source region and the P-type base region extend to the N-drift layer. The auxiliary source trench vertically penetrates the P-type base region and extends to the N-drift layer. + The buried layer is located below the gate trench and the auxiliary source trench and is wrapped by the N drift layer, the P + The buried layer located below the gate trench is discontinuous in the direction parallel to the gate trench and is spatially periodically distributed. The bottom of the auxiliary source trench is adjacent to the P... + The buried layer is in direct contact, and an ohmic contact metal layer is provided at the bottom of the auxiliary source trench. A diode is integrated on the sidewall of the auxiliary source trench.

[0008] In some embodiments, a Schottky diode is integrated into the sidewall of the auxiliary source trench, and the Schottky diode is located in the contact region between the auxiliary source trench and the N drift layer.

[0009] In some implementations, a PIN diode is integrated into the sidewall of the auxiliary source trench.

[0010] In some embodiments, the bottom of the gate trench is connected to the P + Direct contact with the buried layer.

[0011] In some embodiments, the bottom of the gate trench is connected to the P + The burial layer is not in direct contact.

[0012] In some implementations, the gate trench and / or auxiliary source trench adopts a stepped multi-level trench.

[0013] In some implementations, the depth of the auxiliary source trench is greater than the depth of the gate trench.

[0014] In some implementations, the auxiliary source trench is discontinuous in the direction parallel to the gate trench.

[0015] This invention also provides a method for fabricating the above-mentioned trench MOSFET cell structure, comprising the following steps:

[0016] S1. In N + An N-drift layer is epitaxially grown on the substrate;

[0017] S2. Using local ion implantation, P is formed on the N drift layer. + Burial layer;

[0018] S3. Secondary epitaxial growth of N-drift layer;

[0019] S4. A P-type base region is formed on the N-drift layer using ion implantation;

[0020] S5. Using local ion implantation, N-type base regions are formed on the P-type base region. + Source region;

[0021] S6. Using a local etching method, a through-hole is formed in the N + The source region and the P-type base region extend into the gate trench of the N-drift layer;

[0022] S7. A gate dielectric layer is formed in the gate trench using a thermal oxidation process, and a gate electrode is formed on the gate dielectric layer using a polysilicon deposition process;

[0023] S8. Using a local etching method, a source electrode and an auxiliary source trench that penetrates the P-type base region and extends to the N-drift layer are formed;

[0024] S9. An ohmic contact metal layer is formed at the bottom of the source and auxiliary source trenches using a metal deposition process, and a diode is formed on the sidewall of the auxiliary source trench.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] This invention employs a one-sided auxiliary source trench diode construction, combined with a P-type gate bottom. + By using a buried layer, a semi-enclosed trench MOSFET cell structure with better double-sided conduction capability is constructed, increasing the device's conduction capability and reducing conduction losses. Simultaneously, a Schottky diode can be integrated into the sidewall of the trench diode source, and an MPS ohmic contact can be integrated into the bottom, cleverly integrating the Schottky diode into the trench MOSFET to form better freewheeling characteristics. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the MOSFET structure in Example 1;

[0028] Figure 2 for Figure 1 Enlarged view of the cross-section at point A;

[0029] Figure 3 This is a flowchart illustrating the fabrication method of the MOSFET structure in Example 1;

[0030] Figure 4 This is a schematic diagram of the MOSFET structure in Example 2;

[0031] Figure 5 This is a schematic diagram of the MOSFET structure in Example 3;

[0032] Figure 6 This is a schematic diagram of the MOSFET structure in Example 4;

[0033] Figure 7 This is a schematic diagram of the MOSFET structure in Example 5;

[0034] Figure 8 This is a schematic diagram of the MOSFET structure in Example 6;

[0035] Figure 9 This is a schematic diagram of the MOSFET structure in Example 7;

[0036] Figure 10 This is a schematic diagram of the MOSFET structure in Example 8;

[0037] Figure 11 This is a schematic diagram of the MOSFET structure in Example 9;

[0038] Figure 12 This is the TCAD model of the MOSFET cell structure in Example 9;

[0039] Figure 13 The results are the simulation analysis results of the TCAD model in Example 9.

[0040] Attached image labels: 1-N + Substrate, 2-N drift layer, 3-P + Buried layer, 4-P type base region, 5-N + Source region, 6-gate dielectric layer, 7-gate trench, 8-auxiliary source trench, 801-ohmic contact metal layer, 802-Schottky diode, 9-drain. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to specific embodiments, so that those skilled in the art can more clearly understand the present invention. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention. In the embodiments of the present invention, unless otherwise specified, all raw material components are commercially available products well known to those skilled in the art; unless specifically specified, the technical means used are all conventional means well known to those skilled in the art.

[0042] An embodiment of the present invention provides a trench-type MOSFET cell structure, comprising: a gate trench, an auxiliary source trench, and an N-type MOSFET. + Source region, P-type base region, P + Buried layer, N drift layer, N + Substrate, wherein N + The source region is located above the P-type base region and is partially enclosed by the P-type base region. The P-type base region is located above the N-drift layer, and the N-drift layer is located above the N-type base region. + Above the substrate, a gate trench vertically penetrates N. + The source region and P-type base region extend into the N-drift layer, and the auxiliary source trench vertically penetrates the P-type base region and extends into the N-drift layer. + The buried layer is located beneath the gate trench and auxiliary source trench and is encased by an N-drift layer, P + The buried layer located below the gate trench is discontinuous in the direction parallel to the gate trench and is spatially periodically distributed. The bottom of the auxiliary source trench is adjacent to the P... + The buried layer is in direct contact, and an ohmic contact metal layer is provided at the bottom of the auxiliary source trench. A diode is integrated on the sidewall of the auxiliary source trench.

[0043] In some implementations, a Schottky diode is integrated into the sidewall of the auxiliary source trench, and the Schottky diode is located in the contact region between the auxiliary source trench and the N drift layer.

[0044] In some implementations, a PIN diode is integrated into the sidewall of the auxiliary source trench.

[0045] In some implementations, the bottom of the gate trench is adjacent to P + Direct contact of the buried layer can be between the bottom portion of the gate trench and the P + The buried layer can be in direct contact, or the bottom of the gate trench can be completely in contact with the P-type gate. + Direct contact of the buried layer, or the bottom of the gate trench being P + Encased in a burial layer.

[0046] In some implementations, the bottom of the gate trench is adjacent to P + The buried layer does not directly contact, P + The deeper the burial layer, the better its conductivity.

[0047] In some implementations, the gate trench and / or auxiliary source trench adopts a stepped multi-level trench, and the bottom of the gate trench can be treated with a gate oxide thickening process.

[0048] In some implementations, the auxiliary source trench depth is greater than the gate trench depth, and the auxiliary source trench extends deeper into P. + Inside the buried layer.

[0049] In some implementations, the auxiliary source trenches are discontinuous in the direction parallel to the gate trenches and are spatially periodically distributed, resulting in a larger conduction area and a smaller on-resistance.

[0050] The method for fabricating a trench-type MOSFET cell structure provided in this embodiment of the invention includes the following steps:

[0051] S1. In N + An N-drift layer is epitaxially grown on the substrate;

[0052] S2. Using local ion implantation, P is formed on the N drift layer. + Burial layer;

[0053] S3. Secondary epitaxial growth of N-drift layer;

[0054] S4. A P-type base region is formed on the N-drift layer using ion implantation;

[0055] S5. Using local ion implantation, N-type base regions are formed on the P-type base region. + Source region;

[0056] S6. Using a local etching method, a through-hole is formed in the N + The source region and the P-type base region extend into the gate trench of the N-drift layer;

[0057] S7. A gate dielectric layer is formed in the gate trench using a thermal oxidation process, and a gate electrode is formed on the gate dielectric layer using a polysilicon deposition process;

[0058] S8. Using a local etching method, a source electrode and an auxiliary source trench that penetrates the P-type base region and extends to the N-drift layer are formed;

[0059] S9. An ohmic contact metal layer is formed at the bottom of the source and auxiliary source trenches using a metal deposition process, and a diode is formed on the sidewall of the auxiliary source trench.

[0060] Example 1

[0061] This embodiment provides a trench-type MOSFET cell structure, such as Figure 1 As shown, it includes: gate trench 7, auxiliary source trench 8, N + Source region 5, P-type base region 4, P + Buried layer 3, N drift layer 2, N + Substrate 1, N + Source region 2 is located above P-type base region 4 and is partially enclosed by P-type base region 4. P-type base region 4 is located above N-drift layer 2, and N-drift layer 2 is located in the N-type base region 4. + Above substrate 1, gate trench 7 vertically penetrates N. +Source region 5 and P-type base region 4 extend into N-drift layer 2. Auxiliary source trench 8 vertically penetrates P-type base region 4 and extends into N-drift layer 2. + Buried layer 3 is located below gate trench 7 and auxiliary source trench 8 and is wrapped by N drift layer 2, P + The buried layer 3 located below the gate trench 7 is discontinuous in the direction parallel to the gate trench 7 and is spatially periodically distributed. The bottom portion of the gate trench 7 is connected to P + The buried layer 3 is in direct contact with the bottom of the auxiliary source trench 8 and P. + The buried layer 3 is in direct contact with the auxiliary source trench 8, and the bottom of the auxiliary source trench 8 is provided with an ohmic contact metal layer 801. The sidewall of the auxiliary source trench 8 is integrated with a Schottky diode 802. Figure 1 The structure of the bottom and sidewalls of the auxiliary source trench at section A is as follows: Figure 2 As shown, the bottom of the auxiliary source trench 8 is connected to P + An ohmic contact metal layer 801 is formed between the buried layers 3; a Schottky diode 802 is integrated between the sidewall of the auxiliary source trench 8 and the N drift layer 2 to form a Schottky contact.

[0062] The method for fabricating the trench MOSFET cell structure provided in this embodiment is as follows: Figure 3 As shown, it includes the following steps:

[0063] In N + An N-drift layer 2 is epitaxially grown on substrate 1; a P-type layer is formed on the N-drift layer 2 using local ion implantation. + Buried layer 3; secondary epitaxial growth of N-drift layer 2; P-type base region 4 on N-drift layer 2 using ion implantation; N-type base region 4 formed on P-type base region 4 using local ion implantation. + Source region 5; local etching method is used to form a through-N + A gate trench 7 extending from the source region 5 and the P-type base region 4 to the N-drift layer 2 is formed. A gate dielectric layer 6 is formed in the gate trench 7 using a thermal oxidation process. A gate electrode is formed on the gate dielectric layer 6 using a polysilicon deposition process. A source electrode and an auxiliary source trench 8 extending through the P-type base region 4 to the N-drift layer 2 are formed using a local etching method. An ohmic contact metal layer 801 is formed at the bottom of the source electrode and the auxiliary source trench 8 using a metal deposition process. A Schottky diode 802 is formed on the sidewall of the auxiliary source trench 8. Finally, an ohmic contact metal layer is formed on the drain electrode 9 to thicken the drain metal.

[0064] Example 2

[0065] This embodiment provides a trench-type MOSFET cell structure, such as Figure 4 As shown, the difference from Example 1 is that the bottom of the gate trench is entirely connected to the P + Direct contact with the buried layer.

[0066] Example 3

[0067] This embodiment provides a trench-type MOSFET cell structure, such as Figure 5 As shown, the difference from Example 1 is that the bottom of the gate trench is P + Encased in a burial layer.

[0068] Example 4

[0069] The trench MOSFET cell structure provided in this embodiment, such as Figure 6 As shown, the difference from Examples 1-3 is that the auxiliary source trench has a PIN diode integrated on its sidewall.

[0070] Example 5

[0071] The trench MOSFET cell structure provided in this embodiment, such as Figure 7 As shown, the difference from Examples 1-3 is that the bottom of the gate trench is adjacent to the P + The burial layer is not in direct contact.

[0072] Example 6

[0073] The trench MOSFET cell structure provided in this embodiment, such as Figure 8 As shown, the difference from Examples 1-3 is that the gate trench adopts a stepped double-level trench, and the bottom of the gate trench can be made using a gate oxide thickening process.

[0074] Example 7

[0075] The trench MOSFET cell structure provided in this embodiment, such as Figure 9 As shown, the difference from Examples 1-3 is that the auxiliary source trench adopts a stepped two-stage trench.

[0076] Example 8

[0077] The trench MOSFET cell structure provided in this embodiment, such as Figure 10 As shown, the difference from Examples 1-3 is that the auxiliary source trench depth is greater than the gate trench depth, and the auxiliary source trench extends deeper into P. + Inside the buried layer.

[0078] Example 9

[0079] The trench MOSFET cell structure provided in this embodiment, such as Figure 11 As shown, the difference from Example 1 is that the auxiliary source trench is not continuous in the direction parallel to the gate trench, and is periodically distributed in space.

[0080] The cell structure of this embodiment was simulated and analyzed based on TCAD, and the results are as follows: Figure 12 , Figure 13 As shown.

[0081] Figure 12 The TCAD model of the cell structure in this embodiment shows an ohmic contact metal layer formed at the bottom of the source and auxiliary source trenches, a Schottky diode formed on the sidewall of the auxiliary source trench, and the auxiliary source trenches are discontinuous in the direction parallel to the gate trench and are periodically distributed in space.

[0082] Figure 13 for Figure 12 The TCAD model shown presents the simulation results of current density distribution at a gate-source voltage of 20V and a source-drain voltage of 1V. The Z-direction is parallel to the gate trench. At the device cross-section where Z=0, there is a P+ buried layer below the auxiliary source trench, and only the left channel is conductive. At the device cross-section where Z=1.5, there is no P+ buried layer below the auxiliary source trench, and both channels are conductive.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A trench-type MOSFET cell structure, characterized in that, include: Gate trench, auxiliary source trench, N + Source region, P-type base region, P + Buried layer, N drift layer, N + Substrate, wherein the N + The source region is located above the P-type base region and is partially enclosed by the P-type base region. The P-type base region is located above the N-drift layer, and the N-drift layer is located above the N-type base region. + Above the substrate, the gate trench vertically penetrates the N + The source region and the P-type base region extend to the N-drift layer. The auxiliary source trench vertically penetrates the P-type base region and extends to the N-drift layer. + The buried layer is located below the gate trench and the auxiliary source trench and is wrapped by the N drift layer, the P + The buried layer located below the gate trench is discontinuous in the direction parallel to the gate trench and is spatially periodically distributed. The bottom of the auxiliary source trench is adjacent to the P... + The buried layer is in direct contact, and an ohmic contact metal layer is provided at the bottom of the auxiliary source trench. A diode is integrated on the sidewall of the auxiliary source trench.

2. The trench MOSFET cell structure according to claim 1, characterized in that, A Schottky diode is integrated on the sidewall of the auxiliary source trench, and the Schottky diode is located in the contact region between the auxiliary source trench and the N drift layer.

3. The trench MOSFET cell structure according to claim 1, characterized in that, The auxiliary source trench has a PIN diode integrated on its sidewall.

4. The trench MOSFET cell structure according to any one of claims 1 to 3, characterized in that, The bottom of the gate trench is connected to the P + Direct contact with the buried layer.

5. The trench MOSFET cell structure according to any one of claims 1 to 3, characterized in that, The bottom of the gate trench is connected to the P + The burial layer is not in direct contact.

6. The trench MOSFET cell structure according to any one of claims 1 to 3, characterized in that, The gate trench and / or auxiliary source trench adopts a stepped multi-level trench.

7. The trench MOSFET cell structure according to any one of claims 1 to 3, characterized in that, The depth of the auxiliary source trench is greater than the depth of the gate trench.

8. The trench MOSFET cell structure according to any one of claims 1 to 3, characterized in that, The auxiliary source trench is discontinuous in the direction parallel to the gate trench.

9. The method for fabricating the trench MOSFET cell structure according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. In N + An N-drift layer is epitaxially grown on the substrate; S2. Using local ion implantation, P is formed on the N drift layer. + Burial layer; S3. Secondary epitaxial growth of N-drift layer; S4. A P-type base region is formed on the N-drift layer using ion implantation; S5. Using local ion implantation, N-type base regions are formed on the P-type base region. + Source region; S6. Using a local etching method, a through-hole is formed in the N + The source region and the P-type base region extend into the gate trench of the N-drift layer; S7. A gate dielectric layer is formed in the gate trench using a thermal oxidation process, and a gate electrode is formed on the gate dielectric layer using a polysilicon deposition process; S8. Using a local etching method, a source electrode and an auxiliary source trench that penetrates the P-type base region and extends to the N-drift layer are formed; S9. An ohmic contact metal layer is formed at the bottom of the source and auxiliary source trenches using a metal deposition process, and a diode is formed on the sidewall of the auxiliary source trench.

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