Power semiconductor device
By introducing multiple current gain structures into the gate-commutated thyristor and controlling the doping concentration and diffusion depth, the problem of simultaneously optimizing the turn-off characteristics and on-state loss characteristics of IGCT devices is solved, and independent control of loss characteristics is achieved, thereby improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUZHOU CRRC TIMES SEMICON CO LTD
- Filing Date
- 2022-12-12
- Publication Date
- 2026-05-22
AI Technical Summary
Existing IGCT devices are difficult to optimize simultaneously in terms of turn-off characteristics and on-state loss characteristics, making it difficult to reduce loss characteristics at the same time.
By introducing a multi-current gain structure design in the gate-commutated thyristor, the doping concentration and diffusion depth of the first, second, and third sub-base regions can be controlled to optimize the current gain of PNP and NPN transistors, thereby achieving independent control of on-state loss and turn-off loss.
While ensuring turn-off capability, the turn-off loss and on-state loss of gate-commutated thyristors are significantly reduced, improving the flexibility and efficiency of device performance.
Smart Images
Figure CN116013980B_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of power electronics technology, and specifically relates to a power semiconductor device. Background Technology
[0002] Gate commutated thyristors (GCTs) are ultra-high power capacity semiconductor devices in the field of power electronics. IGCTs are characterized by high power capacity, low conduction losses, and robustness against short-circuit failure modes, making them promising for future applications in the power grid sector. As a core component of power devices, the loss characteristics of IGCTs are closely related to the energy transmission efficiency of these devices. For standard IGCTs, their loss characteristics are typically controlled by the current gain α1 of the pnp equivalent transistor and the current gain α2 of the npn equivalent transistor in the GCT chip. Since the turn-off characteristics of IGCTs require the sum of the two current gains α1 + α2 to be approximately equal to 1, within a certain range, to meet the high turn-off capability requirements of GCTs, the turn-off and conduction losses are mainly compromised by the current gain α1 of the pnp equivalent transistor. Therefore, it is difficult to simultaneously reduce the turn-on and turn-off losses of gate commutated thyristors. Summary of the Invention
[0003] This disclosure provides a power semiconductor device.
[0004] This disclosure adopts the following technical solution: a power semiconductor device, comprising: a first P-type region, a first N-type region, a second P-type region, and a second N-type region arranged sequentially from bottom to top, wherein the second N-type region is embedded in the second P-type region, and the top surfaces of the second N-type region and the second P-type region are coplanar, wherein the second P-type region comprises: a P-base region and a first sub-base region, a second sub-base region, and a third sub-base region located above the P-base region, wherein the second sub-base region is located below the second N-type region and does not extend beyond the second N-type region in the horizontal direction, wherein the third sub-base region surrounds the second sub-base region, the first sub-base region surrounds the third sub-base region, and the third sub-base region is in contact with at least the side of the second N-type region, wherein the doping concentration of the P-base region is denoted as n0, the doping concentration of the first sub-base region is denoted as n1, the doping concentration of the second sub-base region is denoted as n2, and the doping concentration of the third sub-base region is denoted as n3, satisfying: n2 > n1 > n3 > n0.
[0005] In some embodiments, the doping concentration of the first subbase region is 1E15 to 1E18 cm⁻¹. -3 The doping concentration of the second subbase region is 1E15~8E18cm. -3 The doping concentration of the third subbase region is 1E15~5E17cm. -3 .
[0006] In some embodiments, the diffusion depth of the first subbase region is denoted as X. jp1The diffusion depth of the second subbase region is denoted as X. jp2 The diffusion depth of the third subbase region is denoted as X. jp3 Satisfying: X jP2 ≥X jP3 ≥X jP1 .
[0007] In some embodiments, in a top perspective view of a power semiconductor device, the second sub-base region has a vertical short axis and a long axis, wherein the short axis dimension x2 of the second sub-base region satisfies: 10μm≤x2≤500μm, and the long axis dimension y2 of the second sub-base region satisfies: 250μm≤y2≤6mm.
[0008] In some embodiments, in a top perspective view of a power semiconductor device, a third sub-base region surrounds a second N-type region and has an annular overlapping region with the second N-type region, and the width W of the third sub-base region satisfies: 5μm≤W≤60μm.
[0009] In some embodiments, the peak doping concentration of the P-based region is 1E13 to 2E16 cm⁻¹. -3 .
[0010] In some embodiments, the diffusion coefficient of most impurities in the P-base region is greater than the diffusion coefficient of most impurities in the first sub-base region, the second sub-base region, and the third sub-base region.
[0011] In some embodiments, the majority of impurities in the P-based region are aluminum or gallium.
[0012] In some embodiments, the majority of impurities in the first, second, and third sub-base regions are boron.
[0013] In some embodiments, the diffusion depth of the P-base region in the region opposite to the first sub-base region is a first depth, and the diffusion depth of the P-base region in the region opposite to the second sub-base region is a second depth, wherein the second depth is less than the first depth.
[0014] In some embodiments, the power semiconductor device further includes: a cathode disposed on the top surface of the second N-type region and in ohmic contact with the second N-type region, and a gate disposed on the top surface of the first sub-base region and in ohmic contact with the first sub-base region, wherein the height of the top surface of the cathode is higher than the height of the top surface of the gate.
[0015] In some embodiments, the power semiconductor device includes a gate-commutated thyristor.
[0016] By controlling the majority carrier concentration in the first, second, and third sub-sub ... Attached Figure Description
[0017] Figure 1This is a cross-sectional view of a power semiconductor device according to an embodiment of the present disclosure.
[0018] Figure 2 This is a cross-sectional view of a power semiconductor device according to another embodiment of this disclosure.
[0019] Figure 3 yes Figure 2 The diagram shows the doping concentration distribution of the power semiconductor device.
[0020] Figure 4 yes Figure 2 A top perspective view of a portion of the structure of the power semiconductor device shown.
[0021] Figure 5 yes Figure 2 A top perspective view of a portion of the structure of the power semiconductor device shown.
[0022] Figure 6 yes Figure 2 The diagram shows a variation of the power semiconductor device.
[0023] Figure 7 yes Figure 2 Another variation of the power semiconductor device shown.
[0024] Figure 8 yes Figure 2 Another variation of the power semiconductor device shown.
[0025] Figure 9 yes Figure 2 Another variation of the power semiconductor device shown. Detailed Implementation
[0026] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.
[0027] It should be noted that the spatial relationships mentioned in this disclosure describe the spatial relationships between the various structures when the anode of a power semiconductor device is located below the cathode.
[0028] Figure 1 This is a cross-sectional view of a power semiconductor device according to an embodiment of the present disclosure.
[0029] refer to Figure 1The present disclosure provides a power semiconductor device, comprising: a first P-type region, a first N-type region, a second P-type region, and a second N-type region arranged sequentially from bottom to top, wherein the second N-type region is embedded in the second P-type region, and the top surfaces of the second N-type region and the second P-type region are coplanar. The second P-type region includes: a P-base region and a first sub-base region, a second sub-base region, and a third sub-base region located above the P-base region. The second sub-base region is located below the second N-type region and does not extend beyond the second N-type region in the horizontal direction. The third sub-base region surrounds the second sub-base region, and the first sub-base region surrounds the third sub-base region. The third sub-base region is in contact with the second N-type region. The doping concentration of the P-base region is denoted as n0, the doping concentration of the first sub-base region is denoted as n1, the doping concentration of the second sub-base region is denoted as n2, and the doping concentration of the third sub-base region is denoted as n3, satisfying: n2 > n1 > n3 > n0.
[0030] The first P-type region serves as the anode region, with the anode positioned below it, forming an ohmic contact with the first P-type region. A gate electrode is positioned above the first sub-base region, forming an ohmic contact with it. The second N-type region serves as the cathode region, with the cathode positioned above it, forming an ohmic contact with the second N-type region.
[0031] Specifically, the power semiconductor device may include a gate-commutated thyristor. Figure 1 The diagram shown is a cross-sectional view of a cell region in a gate-commutated thyristor.
[0032] In a gate-commutated thyristor, the first P-type region, the first N-type region, and the second P-type region form a PNP transistor, with its current gain denoted as α1. The first N-type region, the second P-type region, and the second N-type region form an NPN transistor, with its current gain denoted as α2. To satisfy the hard turn-off characteristics of a gate-commutated thyristor, the design of a gate-commutated thyristor typically requires α1 + α2 ≈ 1, thus requiring a compromise between turn-off loss and on-state loss characteristics.
[0033] exist Figure 1 In the illustrated embodiment, the PNP transistor can be subdivided into three parts. The first part consists of a first P-type region, a first N-type region, a P-base region, and a first sub-base region, with its current gain denoted as α11. The second part consists of a first P-type region, a first N-type region, a P-base region, and a second sub-base region, with its current gain denoted as α12. The third part consists of a first P-type region, a first N-type region, a P-base region, and a third sub-base region, with its current gain denoted as α13.
[0034] exist Figure 1 In the illustrated embodiment, the NPN transistor can be subdivided into two parts. The first part consists of a first N-type region, a P-base region, a second sub-base region, and a second N-type region, with its current gain denoted as α21. The second part consists of a first N-type region, a P-base region, a third sub-base region, and a second N-type region, with its current gain denoted as α22.
[0035] The current gains α12, α13, α21, and α22 primarily affect the turn-off capability and turn-off loss of this gate-commutated thyristor. The current gains α11, α13, α21, and α22 primarily affect the triggering characteristics, turn-off capability, and on-state characteristics of this gate-commutated thyristor.
[0036] The first subbase region has a significant impact on the conduction characteristics and conduction losses of the gate-commutated thyristor. The second subbase region has a significant impact on the turn-off capability and turn-off losses of the gate-commutated thyristor. The third subbase region has a significant impact on the on-state losses of the gate-commutated thyristor.
[0037] By controlling the doping concentration and diffusion depth of the first, second, and third sub-base regions, the on-state loss, turn-off capability, and turn-off loss of the gate-commutated thyristor can be freely adjusted. While ensuring a sufficiently strong turn-off capability, the turn-off loss and on-state loss of the gate-commutated thyristor can be reduced simultaneously. The introduction of a multi-current gain structure in the gate-commutated thyristor greatly enhances the flexibility of device performance control.
[0038] In some embodiments of this disclosure, the power semiconductor device further includes: a cathode disposed on the top surface of the second N-type region and in ohmic contact with the second N-type region, and a gate disposed on the top surface of the first sub-base region and in ohmic contact with the first sub-base region, wherein the height of the top surface of the cathode is higher than the height of the top surface of the gate.
[0039] The insulation process for the gate and cathode is the same as that for existing trench gate commutator thyristors, and no special process needs to be introduced.
[0040] In other embodiments, the height of the top surface of the cathode is equal to the height of the top surface of the gate.
[0041] Figure 2 This is a cross-sectional view of a power semiconductor device according to another embodiment of this disclosure.
[0042] In the cross-sectional view of this power semiconductor device, from bottom to top, are: anode 7, transparent anode 1, N-type buffer layer 2, N-type base region 3, and P-type base region 4. Above the P-type base region 4, from the inside out, are the second sub-base region 5b, the third sub-base region 5c, and the first sub-base region 5a. The N-type cathode region 6 forms a J3 junction 13 with the second sub-base region 5b and the third sub-base region 5c. A J2 junction 12 is formed between the P-type base region 4 and the N-type base region 3. A J1 junction 11 is formed between the transparent anode 1 and the N-type buffer layer 3. The gate 10 forms an ohmic contact with the first sub-base region 5a. The cathode 9 forms an ohmic contact with the N-type cathode region 6.
[0043] Figure 3 yes Figure 2 The diagram shows the doping concentration distribution of the power semiconductor device.
[0044] Specifically, the doping concentration of the first subbase region 5a is 1E15~1E18 cm⁻¹. -3 The doping concentration of the second subbase region 5b is 1E15~8E18cm. -3 The doping concentration of the third subbase region 5c is 1E15~5E17cm. -3 .
[0045] Specifically, the peak doping concentration of P-based region 4 is 1E13~2E16 cm⁻¹. -3 .
[0046] Specifically, the doping concentration of the N-type cathode region 6 is 1E17 to 1E22 cm⁻¹. -3 The doping concentration of transparent anode 1 is 1E17 to 1E19 cm⁻¹. -3 The doping concentration of the N-type buffer layer 2 is 5E14 to 1E17 cm⁻¹. -3 The doping concentration of the N-type base region 3 depends on the voltage level, typically ranging from 1E12 to 1E14 cm⁻¹. -3 .
[0047] Optionally, the diffusion coefficient of most impurities in the P-base region 4 is greater than the diffusion coefficient of most impurities in the first sub-base region 5a, the second sub-base region 5b, and the third sub-base region 5c.
[0048] For example, most impurities in P-based region 4 are aluminum or gallium.
[0049] For example, most of the impurities in the first sub-subbase region 5a, the second sub-subbase region 5b, and the third sub-subbase region are boron.
[0050] Specifically, the diffusion depth of impurities can be controlled by high-temperature diffusion propagation.
[0051] By adjusting the diffusion depths of the first sub-base region 5a, the second sub-base region 5b, and the third sub-base region 5c, the current gains a11, a12, a13, a21, and a22 can be adjusted, thereby increasing the design flexibility of power semiconductor devices.
[0052] In the embodiments of this disclosure, the diffusion depth of the first sub-base region 5a is denoted as X. jp1 The diffusion depth of the second subbase region 5b is denoted as X. jp2 The diffusion depth of the third subbase region 5c is denoted as X. jp3 Satisfying: X jP2 ≥X jP3 ≥X jP1 .
[0053] The doping concentrations of each sub-base region 5a, 5b, and 5c are relatively high, while the doping concentration of the P-base region is relatively low. Both distributions exhibit Gaussian distributions, and there is usually a concentration change inflection point for both distributions. The distance from this inflection point to the top surface of the second N-type region is the diffusion depth.
[0054] For example in Figure 2 In the embodiment shown, X jP2 =X jP3 =X jP1 .
[0055] Figure 6 yes Figure 2 The diagram shows a variation of the power semiconductor device.
[0056] exist Figure 6 In the embodiment shown, X jP2 >X jP3 =X jP1 This design achieves a high NPN transistor current gain α21 through the second sub-base region 5b to meet the requirements of high turn-off current and low turn-off loss. Secondly, the NPN transistor current gain α22 is reduced by decreasing the diffusion depth of the third sub-base region 5c. Furthermore, the electron emission efficiency of the second N-type region in the on-state is improved by increasing the current gain α13 of the PNP transistor formed by the first P-type region, the first N-type region, the P-base region, and the third sub-base region. This enhances the bipolar carrier modulation effect in the on-state and reduces the on-state loss. Therefore, through multiple current gain control designs, the turn-on and turn-off losses of the device are further reduced.
[0057] Figure 4 yes Figure 2 A top perspective view of a portion of the structure of the power semiconductor device shown.
[0058] In this embodiment, the N-type cathode region 6 has two mutually perpendicular axes of symmetry. The dimension of the N-type cathode region 6 along its major axis is denoted as y0, and the dimension along its minor axis is denoted as x0. The second sub-base region 5b has two mutually perpendicular axes of symmetry. The dimension of the second sub-base region 5b along its major axis is denoted as y2, and the dimension along its minor axis is denoted as x2. The third sub-base region 5c surrounds and is in close contact with the second sub-base region 5b. The outer boundary of the third sub-base region 5c has mutually perpendicular major and minor axes. All major axes are in the same direction, and all minor axes are in the same direction. The width of the third sub-base region 5c along its major axis is denoted as y3, and the width of the third sub-base region 5c along its minor axis is denoted as x3.
[0059] In these embodiments, in the top perspective view of the power semiconductor device, the minor axis dimension x2 of the second sub-base region 5b satisfies: 10μm≤x2≤500μm, and the major axis dimension y2 of the second sub-base region satisfies: 250μm≤y2≤6mm.
[0060] In these embodiments, in the top perspective view of the power semiconductor device, the third sub-base region 5c surrounds the second N-type region 6 and has an annular overlapping region with the second N-type region 6, and the width W of the third sub-base region satisfies: 5μm≤W≤60μm. Where W represents x3 or y3.
[0061] In these embodiments, the following conditions are met: x2≤x3≤(x0+60μm), y2≤y3≤(y0+60μm).
[0062] Figure 5 yes Figure 2 A top perspective view of a portion of the structure of the power semiconductor device shown.
[0063] The N-type cathode region 6 is also called the cathode comb. The cathode comb is arranged in a fan shape, and the gate 10 is distributed in the gap area of the cathode comb. The lead-out part of the gate 10 can be annular. Figure 5 The image shows a portion of the power semiconductor device.
[0064] Figure 7 yes Figure 2 Another variation of the power semiconductor device shown.
[0065] In some embodiments, the diffusion depth of the P-base region 4 in the region opposite to the first sub-base region 5a is a first depth, and the diffusion depth of the P-base region 4 in the region opposite to the second sub-base region 5b is a second depth, the second depth being less than the first depth.
[0066] In other words, the bottom surface of the P-type base region 4 is recessed inward in the region opposite to the second sub-base region 5b. Correspondingly, the top surface of the N-type base region 3 forms a protrusion in the region opposite to the second sub-base region 5b.
[0067] This design creates a transverse electric field in the P-base region 4, enhancing the rate at which the device extracts charge carriers during turn-off. It prevents hole carriers from accumulating in the second sub-base region 5b, which would cause enhanced electron carrier emission in the second N-type region. It also avoids the formation of a PN junction re-triggering between the second sub-base region 5b and the second N-type region during turn-off, thereby increasing the turn-off current density of the power semiconductor device.
[0068] Figure 8 yes Figure 2 Another variation of the power semiconductor device shown. Figure 8 The structure shown can be a partial structure of a reverse-resistance gate-commutated thyristor.
[0069] Figure 8 The anode region of the power semiconductor device shown includes a P-type anode emitter region 1a and a P-type anode region 1b. The doping concentration of the P-type anode emitter region 1a is, for example, 1E16~1E20 cm⁻¹. -3The doping concentration of the P-type anode region 1b is, for example, 1E13~2E16 cm⁻¹. -3 .
[0070] Figure 9 yes Figure 2 Another variation of the power semiconductor device shown. Figure 9 The power semiconductor device shown can be a partial structure of a reverse-conducting gate-commutated thyristor. The gate-commutated thyristor is integrated with an anti-parallel diode.
[0071] Specifically, the diode includes: a P-type anode emitter region 14, a P-type anode region 15, an N-type base region 3, an N-type buffer layer 16, and an N-type cathode emitter region 17.
[0072] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0073] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.
Claims
1. A power semiconductor device, comprising: A first P-type region, a first N-type region, a second P-type region, and a second N-type region are arranged sequentially from bottom to top. The second N-type region is embedded in the second P-type region. The top surfaces of the second N-type region and the second P-type region are coplanar. The second P-type region includes a P-base region and a first sub-base region, a second sub-base region, and a third sub-base region located above the P-base region. The second sub-base region is located below the second N-type region and does not extend beyond the second N-type region in the horizontal direction. The third sub-base region surrounds the second sub-base region, and the first sub-base region surrounds the third sub-base region. The third sub-base region is in contact with the second N-type region. The doping concentration of the P-base region is denoted as n0, the doping concentration of the first sub-base region is denoted as n1, the doping concentration of the second sub-base region is denoted as n2, and the doping concentration of the third sub-base region is denoted as n3, satisfying: n2 > n1 > n3 > n0.
2. The power semiconductor device according to claim 1, characterized in that, The doping concentration of the first subbase region is 1E15~1E18cm. -3 The doping concentration of the second subbase region is 1E15~8E18cm. -3 The doping concentration of the third subbase region is 1E15 to 5E17 cm⁻¹. -3 .
3. The power semiconductor device according to claim 1, characterized in that, The diffusion depth of the first sub-base region is denoted as X. jp1 The diffusion depth of the second subbase region is denoted as X. jp2 The diffusion depth of the third subbase region is denoted as X. jp3 Satisfying: X jP2 ≥X jP3 ≥X jP1 .
4. The power semiconductor device according to claim 1, characterized in that, In the top perspective view of the power semiconductor device, the second sub-base region has a short axis and a long axis that are perpendicular to each other. The short axis dimension x2 of the second sub-base region satisfies: 10μm≤x2≤500μm, and the long axis dimension y2 of the second sub-base region satisfies: 250μm≤y2≤6mm.
5. The power semiconductor device according to claim 1, characterized in that, In the top perspective view of the power semiconductor device, the third sub-base region surrounds the second N-type region and has an annular overlapping area with the second N-type region, and the width W of the third sub-base region satisfies: 5μm≤W≤60μm.
6. The power semiconductor device according to claim 1, characterized in that, The peak doping concentration of the P-based region is 1E13~2E16 cm⁻¹ -3 .
7. The power semiconductor device according to claim 1, characterized in that, The diffusion depth of the P-base region in the region opposite to the first sub-base region is a first depth, and the diffusion depth of the P-base region in the region opposite to the second sub-base region is a second depth, the second depth being less than the first depth.
8. The power semiconductor device according to claim 1, characterized in that, The power semiconductor device further includes: a cathode disposed on the top surface of the second N-type region and in ohmic contact with the second N-type region, and a gate disposed on the top surface of the first sub-base region and in ohmic contact with the first sub-base region, wherein the height of the top surface of the cathode is higher than the height of the top surface of the gate.
9. The power semiconductor device according to claim 1, characterized in that, The power semiconductor device includes: a gate-commutated thyristor.