A pressure sensor modulation circuit

Abstract

This invention provides a pressure sensor modulation circuit, comprising: a pre-filter that filters the differential signal and outputs it to a gain amplifier, which then amplifies it and outputs it to an analog-to-digital converter (ADC) to output a digital signal to a signal processor; the signal processor processes the data and outputs it to the digital-to-analog converter (DAC), and also inputs and outputs digital signals to and from a HART transceiver; the ADC converts the digital signal into an analog voltage signal and outputs it to a 4-20mA constant current generator, which, after passing the analog voltage signal from the ADC through a V / I circuit, generates a 4-20mA constant current that is connected in parallel with the HART bus transmission signal generated by the HART transceiver and outputs it. The advantages of this invention are: the operational amplifier circuit uses high-voltage components; the push-pull power amplifier circuit employs a complementary push-pull circuit structure to prevent output signal deformation; and it addresses the shortcomings of existing pressure sensor modulation circuits, such as limited compatibility with specific core components and unstable output signals under vibration.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology and relates to a pressure sensor modulation circuit. Background Technology

[0002] With the increasing diversity of pressure sensor requirements, conventional pressure sensor manual modulation circuits not only suffer from poor modulation effects and low accuracy, but also exhibit unstable output signals during vibration. Currently, the industry often uses modulation circuits from existing pressure sensor chip manufacturers that are compatible with specific pressure sensor chip models, resulting in poor compatibility. Therefore, it is necessary to invent a pressure sensor modulation circuit to overcome the shortcomings of existing pressure sensor modulation circuits. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing pressure sensor modulation circuits by providing a pressure sensor modulation circuit that solves the problems of existing pressure sensor modulation circuits being limited to compatible cores, having poor compatibility, and having unstable output signals when subjected to vibration.

[0004] To achieve the above objectives, the present invention provides a pressure sensor modulation circuit, comprising:

[0005] The power processing module is used to connect to DC power and process it to provide power to other modules with the required voltage;

[0006] A pre-filter, connected to the pressure sensor core, is used to connect the differential signal output by the pressure sensor core and filter it before outputting it to the gain amplifier.

[0007] The gain amplifier, connected to the output signal of the pre-filter, amplifies the signal and outputs it to the analog-to-digital converter.

[0008] An analog-to-digital converter (ADC) is connected to the output signal of a gain amplifier. After analog-to-digital conversion, the analog signal is converted into a digital signal and output to the signal processing unit.

[0009] The signal processor is connected to the output signal of the analog-to-digital converter and also to the HART transceiver. After data processing, the processed signal is output to the analog-to-digital converter. It also performs digital signal input and output with the HART transceiver.

[0010] The digital-to-analog converter is connected to the digital signal after signal processing. After digital-to-analog conversion, the digital signal is converted into an analog voltage signal and output to the 4-20mA constant current generator. It generates a 4-20mA constant current through the V / I circuit of the analog voltage signal after digital-to-analog conversion. This constant current is connected in parallel with the HART bus transmission signal generated by the HART transceiver and output.

[0011] The HART transceiver connects to the input and output digital signals of the signal processing unit, and simultaneously generates the HART bus transmit signal and outputs a 4-20mA constant current signal generated by the 4-20m signal generator in parallel.

[0012] The advantages of this invention are: the operational amplifier circuit has high voltage withstand capability, and the push-pull power amplifier circuit adopts a complementary push-pull circuit structure to prevent output signal distortion. The input differential small signal is fed to the differential amplifier circuit for initial amplification, and then the amplified signal is sent to the intermediate stage amplifier circuit for voltage amplification. Finally, the voltage-amplified signal is sent to the output push-pull power amplifier circuit for power amplification and output. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating the principle of implementing the present invention;

[0014] Figure 2 This is a circuit diagram of the power processing module of the present invention;

[0015] Figure 3 This is a circuit diagram of the pre-filter, gain amplifier, and analog-to-digital converter of the present invention.

[0016] Figure 4 This is a circuit diagram of the signal processor of the present invention;

[0017] Figure 5 This is the circuit diagram of the 4-20m signal generator of the present invention;

[0018] Figure 6 This is a circuit diagram of the digital-to-analog converter and HART transceiver of the present invention. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] This invention relates to a pressure sensor modulation circuit. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the invention. The figures only show the components related to the invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] I. For example Figure 1As shown, the pressure sensor modulation circuit of this embodiment includes at least: a power supply processing circuit, a pre-filter, a gain amplifier and analog-to-digital conversion signal processing circuit, a signal processing and digital-to-analog conversion circuit, a 4-20m signal generator circuit, and a HART transceiver circuit. The power supply processing module is used to connect to a DC power supply and process the voltage to provide power to other modules.

[0022] A pre-filter, connected to the pressure sensor core, is used to connect the differential signal output by the pressure sensor core and filter it before outputting it to the gain amplifier.

[0023] The gain amplifier, connected to the output signal of the pre-filter, amplifies the signal and outputs it to the analog-to-digital converter.

[0024] An analog-to-digital converter (ADC) is connected to the output signal of a gain amplifier. After analog-to-digital conversion, the analog signal is converted into a digital signal and output to the signal processing unit.

[0025] The signal processor is connected to the output signal of the analog-to-digital converter and also to the HART transceiver. After data processing, the processed signal is output to the analog-to-digital converter. It also performs digital signal input and output with the HART transceiver.

[0026] The digital-to-analog converter is connected to the digital signal after signal processing. After digital-to-analog conversion, the digital signal is converted into an analog voltage signal and output to the 4-20mA constant current generator. It generates a 4-20mA constant current through the V / I circuit of the analog voltage signal after digital-to-analog conversion. This constant current is connected in parallel with the HART bus transmission signal generated by the HART transceiver and output.

[0027] The HART transceiver connects to the input and output digital signals of the signal processing unit, and simultaneously generates the HART bus transmit signal and outputs a 4-20mA constant current signal generated by the 4-20m signal generator in parallel.

[0028] II. Power supply processing circuit, such as Figure 2As shown, it consists of diodes D1, D2, and D3; capacitors C3, C9, C10, C11, C15, and C17; resistors R4 and R5; inductor L1; and integrated circuits V1, V2, and V3. The circuit consists of diodes D1 and D2 forming a power supply protection circuit, responsible for protecting the power supply voltage VCC12V from overvoltage and reverse polarity. D1 is connected in parallel to the positive and negative terminals VCC12V and GND in the power supply circuit. The anode of D2 is connected to VCC12V, and the cathode is connected to pin 5 of V1, forming a network VCC-IN. Pins 5 and 4 of integrated circuit V1 are connected to the positive terminal VCC-IN protected by D1 and D2. Pin 2 of V1 is connected to the power supply GND, and capacitor C3 is connected in parallel between VCC-IN and GND to filter the power supply. The output SW of V1 is connected to the cathode of diode D3, one end of C9, and one end of L1. The other end of C9 is connected to pin 1 of V1, and the other end of L1 forms a 5.8V power supply network VCC5V8. C10 is connected in parallel between GND. The anode of D3 is connected to the power supply GND network. R4 and R5 are connected in series between the VCC5V8 network and the GND network, and pin 3 of V1 is connected in the middle of the series connection of R4 and R5 to form voltage feedback. Capacitors C3, C9, and C10, resistors R4 and R5, inductor L1, and integrated circuit V1 together form a Buck switching step-down circuit, which steps down the 12V DC power supply of the VCC-IN network to 5.8V, forming the VCC5V8 network. Pin 3 of V2 is connected to the VCC5V8 network, and pin 1 is connected to the GND network. Capacitor C11 is connected in parallel between pins 3 and 1 of V2. Capacitors C11 and C15, along with integrated circuit V2, form a linear differential voltage reduction circuit, which steps down the 5.8V voltage of the VCC5V8 network to 5V, forming the VCC5V network, while filtering out ripple noise in the circuit. Pins 1 and 3 of V3 are connected to the VCC5V network and connected in parallel with capacitor C15. Pin 2 of V3 is connected to the GND network, and pin 5 of V3 is connected to the VCC3V3 network and connected in parallel with capacitor C17. Capacitors C15 and C17, along with integrated circuit V3, form a linear differential voltage reduction circuit. This circuit reduces the 5V voltage of the VCC5V network to 3.3V, forming the power supply network VCC3V3. Simultaneously, it filters out ripple noise in the circuit for the second time. Ferrite bead FB1 is connected to the VCC5V network at one end and to the AVCC5V network at the other. Ferrite bead FB2 is connected to the GND network at one end and to the AGND network at the other. Capacitors C1 and C2 are connected in parallel between AVCC5V and AGND. Capacitors C1 and C2, along with ferrite beads FB1 and FB2, form an LC filter circuit. This circuit filters the 5V power supply in the VCC5V network, forming a dedicated analog DC power supply for the sensor chip and analog-to-digital converter circuit. The positive terminal is AVCC5V, and the negative terminal is AGND.

[0029] III. Pre-filter circuit, such as Figure 3As shown, the pre-filter circuit includes field capacitors C1, C2, C4, C5, and C6, and resistors R2 and R3. Specifically: capacitors C4 and C5 have the same model and parameters, with a capacitance of Cc; capacitor C6 has a capacitance of Cd; and resistors R2 and R3 have the same model and parameters, with a resistance of R. One end of R2 is connected to the S+ signal output terminal of the pressure sensor core, and the other end is connected to the S_P network. One end of R3 is connected to the S- signal output terminal of the pressure sensor core, and the other end is connected to the S_N network. One end of C4 and C5 are connected to the AGND network, the other end of C4 is connected to the S_P network, and the other end of C5 is connected to the S_N network. Capacitors C4, C5, and C6, and resistors R2 and R3 form a differential mode signal filtering circuit, with the filtering formula FilterFreqDIFF=1 / ((2πR(2C_d+C_c))). Capacitors C4 and C5, and resistors R2 and R3 form a differential mode signal filtering circuit, with the filtering formula FilterFreqCM=1 / (2πRC_c). In this way, a relatively small number of components can be used to simultaneously perform differential mode and common mode signal filtering on the differential pressure signals S+ and S- sensed by the pressure sensor core, and output them to the networks S_P and S_N.

[0030] IV. Gain amplifiers and analog-to-digital converters, such as Figure 3 As shown, the system consists of capacitors C7, C8, C12, and C16, resistor R6, and integrated circuit U1, which has a built-in integrated gain amplifier. Pin 10 of U1 is connected to the S_P network, and pin 7 is connected to the S_N network, introducing the filtered pressure differential signal. Pin 12 of U1 is connected to the AVCC5V network, and pins 5 and 6 are connected to the AGND network, with capacitors C7 and C8 connected in parallel. C7 and C8 are the filter capacitors for U1's analog power supply network. Pin 13 of U1 is connected to the VCC3V3 network, and pins 3 and 4 are connected to the GND network, with capacitors C12 and C16 connected in parallel. C12 and C16 are the filter capacitors for U1's 3.3V power supply network. Pin 2 of U1 is connected to the nSS1 network and connected to the VCC3V3 network via R6 to form a weak pull-up. Pin 1 is connected to the SCLK1 network, pin 16 is connected to the MOSI1 network, pin 15 is connected to the MISO1 network, and pin 14 is connected to the D(—)R(—)D(—)Y(—) network. The networks nSS1, SCLK1, MOSI1, and MISO1 together form an SPI communication bus. U1 uses this bus to provide the converted pressure core value signal to the integrated circuit U3 in the signal processor.

[0031] V. Signal processors and digital-to-analog converters, such as Figure 4As shown, the signal processor and digital-to-analog converter consist of capacitors C18 and C19, resistors R14 and R15, integrated circuit U3, and button S1. Integrated circuit U3 is the signal processor with a built-in digital-to-analog converter. One end of resistor R15 is connected to the VCC3V3 network to pull up a 3.3V power supply, and the other end is connected to pin 7 of U3 and one end of switch S1. The other end of S1 is connected to the GND network, forming a reset button circuit for U3. C18 and C19 connect one end to the VCC3V3 network and pins 1, 20, 21, 23, 35, and 48 of U3, and the other end to the GND network, forming the power supply network for the U3 digital power supply, providing filtered power to U3; R14 connects one end to the GND network and the other end to pin 46 of U2, always keeping the boot configuration pin (pin 46) of U2 low; pin 13 of U3 connects to the SCLK1 network, pin 15 to the MOSI1 network, pin 14 to the MISO1 network, pin 30 to the D(—)R(—)D(—)Y(—) network, and pin 31 to the nSS1 network, forming the SPI communication network. The line connection is used to communicate with U1 in the digital-to-analog converter and read data from the digital converter; pin 12 of U3 is connected to the DAC_OUT1 network, which is used to output the analog voltage output from the digital-to-analog converter inside U3 to the 4-20mA signal generator; pin 17 of U3 is connected to the HART_XCEN network, pin 18 is connected to the HART_OCD network, pins 19 and 28 are connected to the HART_RTS network, pin 41 is connected to the HART_DOUT network, and pin 42 is connected to the HART_DIN network, forming the connection network between U3 and the integrated circuit U2 in the HART transceiver, which is used to transmit digital signals to the digital converter.

[0032] VI. 4-20mA signal generator, such as Figure 5As shown, the 4-20mA signal generator circuit comprises capacitors C20, C21, and C22, resistors R9, R10, R12, and R13, transistor Q1, and integrated circuit U2. U2 has two built-in operational amplifiers, U4A and U4B. C20 and C21 are connected at one end to the VCC-IN network and at the other end to the GND network, forming a power supply filter for U4, which inputs the filtered power to U4. R9 is connected to the DAC1_OUT network at one end and to R11 and pin 3 of U4A at the other end, inputting the voltage signal to U4; R10 is connected to the GND network at one end and to pin 2 of U4A at the other end; R12 and C22 are connected in parallel to pins 1 and 2 of U4A, providing a negative feedback signal to U4A, and achieving a low-pass filtering effect in the feedback loop through C22; the output signal of pin 1 of U4A is connected to the base of Q1, the collector of Q1 is connected to the VCC-IN network to obtain a 12V power supply, and the emitter is connected to one end of R13. The other end of R13 is connected to pin 5 of U4B and the 4-20mA output terminal, forming a voltage-controlled constant current controller, and outputting the 4-20mA signal on R13 and feeding it back to U4B; pin 5 of U4B is connected to the 4-20mA output terminal, and pins 6 and 7 are connected to form a voltage follower, and sending the output signal of pin 7 of U4B to the other end of R11. Capacitors C20, C21, and C22, resistors R9, R10, R12, and R13, transistor Q1, and integrated circuit U2 form a Howland current source. The output current is controlled by the voltage signal generated by U3, forming a 4-20mA signal generator circuit.

[0033] 7. HART transceivers, such as Figure 6As shown, the HART transceiver circuit comprises capacitors C13 and C14, resistors R1, R7, and R8, crystal oscillator Y1, and integrated circuit U2. C13 is connected to the GND network at one end and the HT_RTS network at the other, forming the HART transceiver's reset circuit, and is connected to pin 13 of U2 via HART_RTS. C14 is connected to the FSK_IN input terminal of the external HART bus at one end and to the FSK_IN network at the other, and is connected to pin 14 of U2 via the FSK_IN network, forming the carrier input interface of the HART bus. R7 is connected in series between pins 13 and 14 of U2, and R8 is connected in series between pin 14 of U2 and the GND network, forming a reset potential release circuit. Y1 is connected to pins 7 and 8 of U2, providing a clock oscillation source for the HART transceiver. R1 is connected in series with pin 17 of U2. Between the pin and GND, pull pin 17 of U2 low to configure the HART transceiver's operating mode; pin 10 of U2 is connected to the HART_XCEN network, pin 5 to the HART_OCD network, pin 13 to the HART_RTS network, pin 19 to the HART_DOUT network, and pin 42 to the HART_DIN network, forming the connection network of integrated circuit U3 in the signal processor, used to transmit the data signals of HART transceiver U2 and the control signals of U3 to HART transceiver; pin 12 of U2 is connected to the 4-20mA output terminal of the 4-20mA signal generator, used to load the HART carrier signal onto the 4-20mA current signal for external communication.

[0034] The pressure sensor modulation circuit provided by this invention has the following characteristics:

[0035] The pressure sensor modulation circuit achieves excellent modulation: The pressure sensor modulation circuit communicates with the internal signal processing via the HART communication protocol and a dedicated HART transceiver. The internal signal processing uses a high-performance microcontroller with a digital processor, which can perform calibration processing and linearity fitting through the HART communication bus, ensuring modulation speed and communication stability.

[0036] High precision of the pressure sensor modulation circuit: The pressure sensor modulation circuit adopts multiple signal filtering circuits, high-precision analog-to-digital conversion, and high-precision digital-to-analog conversion. Through internal software, the signals collected by the pressure sensor are calibrated at multiple points, filtered by finite element method, and fitted with straight lines. This ensures the accuracy of the output signal and also guarantees the linearity of the sensor.

[0037] The pressure sensor modulation circuit achieves anti-vibration signal instability: In the pressure sensor modulation circuit, the zero point and full scale point of the sensor are calibrated entirely using digital signal processing methods, completely abandoning the previous method of adjusting the zero point and full scale point by adjusting the sliding resistor. At the same time, all components are surface-mount components and are assembled with high-strength printed circuit boards. This can completely ensure that the signal instability caused by poor contact due to the sliding rheostat or component assembly method under vibration is not caused.

[0038] This invention belongs to the fields of electronics, communications, and information engineering, and relates to a pressure sensor modulation circuit. It comprises an internal power supply processing circuit, a pre-filter circuit, a gain amplifier and analog-to-digital conversion signal processing circuit, a signal processing and digital-to-analog conversion circuit, a 4-20m signal generator circuit, and a HART transceiver circuit. The component parameters can be reselected according to actual needs.

[0039] The above description is only a limited embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pressure sensor modulation circuit comprising a power handling module for interfacing with a DC power supply and processing to provide power to other modules at a required voltage, characterised in that It comprises: a pre-filter, a gain amplifier, an analog-to-digital converter, a signal processor, a digital-to-analog converter, a 4-20mA signal generator and a HART transceiver; the pre-filter is connected to the pressure sensor core and is used to connect the differential signal output by the pressure sensor core and output to the gain amplifier after filtering; the gain amplifier is connected to the output signal of the pre-filter, amplifies the signal and outputs to the analog-to-digital converter; the analog-to-digital converter is connected to the output signal of the gain amplifier, converts the analog signal to a digital signal and outputs to the signal processor; the signal processor is connected to the output signal of the analog-to-digital converter and the HART transceiver, processes the data and outputs the processed data to the digital-to-analog converter and the HART transceiver; the digital-to-analog converter is connected to the signal processor, converts the digital signal to an analog voltage signal and outputs to the 4-20mA signal generator; the HART transceiver is connected to the input and output digital signals of the signal processor and outputs the HART bus signal and the 4-20mA constant current generated by the 4-20mA signal generator in parallel; the 4-20mA signal generator circuit is composed of capacitors C20, C21, C22, resistors R9, R10, R12, R13, a transistor Q1 and an integrated circuit U4, the U4 has two groups of operational amplifiers, namely U4A and U4B; one end of C20 and C21 is connected to the VCC-IN network and the other end is connected to the GND network, one end of R9 is connected to the DAC1_OUT network and the other end is connected to R11 and the 3 pin of U4A to input the voltage signal to U4A; one end of R10 is connected to the GND network and the other end is connected to the 2 pin of U4A; R12 and C22 are connected in parallel to the 1 and 2 pins of U4A to provide a negative feedback signal for U4A and achieve a low-pass filtering effect in the feedback loop through C22; the 1 pin of U4A is connected to the base of Q1, the collector of Q1 is connected to the VCC-IN network to obtain a 12V power supply, the emitter of Q1 is connected to one end of R13 and the other end of R13 is connected to the 5 pin of U4B and the 4-20mA output end to form a voltage-controlled constant current controller and output the 4-20mA signal on R13 to U4B; the 5 pin of U4B is connected to the 4-20mA output end, the 6 pin is connected to the 7 pin to form a voltage follower and send the output signal of the 7 pin of U4B to the other end of R11; the capacitors C20, C21, C22, the resistors R9, R10, R12, R13, the transistor Q1 and the integrated circuit U4 form a Gurand current source, the output current is controlled by the voltage signal generated by U3, the U3 is a digital-to-analog converter built in the signal processor and forms the 4-20mA signal generator circuit.

2. The pressure sensor modulation circuit according to claim 1, characterized in that: The HART transceiver circuit is composed of capacitors C13, C14, resistors R1, R7, R8, crystal oscillator Y1 and integrated circuit U2, wherein one end of C13 is connected to the GND network and the other end is connected to the HART_RTS network, forming the reset circuit of the HART transceiver and connected to pin 13 of U2 through the HART_RTS; one end of C14 is connected to the FSK_IN input terminal of the external HART bus and the other end is connected to the FSK_IN network and pin 14 of U2 through the FSK_IN network, forming the carrier input interface of the HART bus; R7 is connected in series between pin 13 and pin 14 of U2 and R8 is connected in series between pin 14 of U2 and the GND network, forming the reset potential release circuit; Y1 is connected between pin 7 and pin 8 of U2, providing the clock oscillation source for the HART transceiver; R1 is connected in series between pin 17 of U2 and the GND, pulling down pin 17 of U2 and configuring the working mode of the HART transceiver; pin 10 of U2 is connected to the HART_XCEN network, pin 5 is connected to the HART_OCD network, pin 13 is connected to the HART_RTS network, pin 19 is connected to the HART_DOUT network and pin 42 is connected to the HART_DIN network, forming the connection network of the integrated circuit U3 in the signal processor, used for transmitting the data signal of the HART transceiver U2 and the control signal of U3 to the HART transceiver; pin 12 of U2 is connected to the 4-20mA output terminal of the 4-20mA signal generator, used for loading the carrier signal of the HART onto the 4-20mA current signal and communicating with the outside.

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