A circuit for accelerating long trace setup time in a chip
By introducing BUFFER and KEEPER circuits and a series structure of MOS devices into the integrated circuit, the signal delay problem caused by long traces is solved, thereby accelerating the signal settling time and improving circuit performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2022-12-26
- Publication Date
- 2026-05-12
AI Technical Summary
In integrated circuits, RC loading caused by long traces seriously affects chip operation speed and circuit performance, especially in large-scale SoC circuits and high-frequency chip designs, where existing circuit designs struggle to effectively accelerate the settling time of long traces.
By employing a structure in series between the BUFFER and KEEPER circuits, and combining the first and second MOS devices, the influence of lingering signals on the signal lines is shielded by controlling the gate enable signal of the MOS devices, and the signal settling time is accelerated by using feedback design.
It effectively accelerates the signal settling time of long traces, reduces the impact of signal conflicts, saves layout area and cost, and improves circuit performance.
Smart Images
Figure CN116015278B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a circuit for accelerating the setup time of long traces in a chip. Background Technology
[0002] With the rapid development of electronic information technology, the density of integrated circuits and the number of conductor connections are constantly increasing, which in turn leads to the serious impact of resistor-capacitor delay (RCdelay) on the chip's operation speed, that is, it seriously affects the setup time of the next stage circuit.
[0003] Especially in the design of large-scale SoC circuits and high-frequency chip circuits, excessively long traces often lead to excessive RC loading, causing chip response delay, accuracy deviation, and even affecting the normal performance of the chip.
[0004] However, due to the large size of chips, long traces are often unavoidable in design. In layout design, increasing trace width, adding shielding lines, or using multi-layer metal stack-up traces can reduce RC loading. But when layout design can't solve the problem, the setup time of the next stage circuit can be accelerated by improving the circuit design. This way, the chip area is not increased too much, and the impact of long trace RC loading on circuit performance can be cleverly avoided.
[0005] Figure 1 It is a commonly used logic circuit design structure. The output terminal of inverter (11) is connected to the input terminal of inverter (12), the output terminal of inverter (12) is connected to the input terminal of inverter (13), and the output terminal of inverter (13) is the output terminal of the circuit. When the signal line (15) is too long, it will bring a large RC loading, which will cause the inverted signal of inverter (13) to arrive late, affecting the start-up of subsequent circuits and even affecting the circuit performance. Especially in large-scale SoC chip circuits or high-frequency circuits, the effect of RC loading is particularly significant.
[0006] Figure 2This is a schematic diagram of a long trace delay compensation circuit commonly used in chips. The output terminal of inverter (21) is connected to the input terminal of inverter (22), the output terminal of inverter (22) is connected to the input terminal of inverter (23), the output terminal of inverter (23) is the output terminal of the circuit, and the output terminal of inverter (23) is connected to the input terminal of inverter (26). The input terminal of inverter (26) is fed back to the input terminal of inverter (23). Through the feedback design of inverter (26), the signal of signal line (25) is strengthened and the settling time is accelerated. However, this circuit still has drawbacks. When the voltage level on the signal line (25) does not reach the switching voltage of the inverter (23), the signal on the signal line (27) is exactly the opposite of the desired signal. That is, when the signal on the signal line (27) is maintaining the state "1" of the previous stage, the signal on the signal line (25) cannot quickly establish from the "0" state to the "1" state due to RC loading. During this period, the output state of the inverter (26) is "0", while the signal on the signal line (25) needs to quickly establish from the "0" state to the "1" state. Therefore, during this period, the feedback signal conflicts with the signal that the signal on the signal line (25) wants to establish, which makes the establishment time of the signal state on the signal line (25) from the "0" state to the "1" state even longer, affecting the response of the subsequent circuit. Conversely, when the signal on signal line (27) is maintaining the state "0" of the previous stage, the signal on signal line (25) cannot quickly establish from the state "1" to the state "0" due to RC loading. During this period, the output state of inverter (26) is "1", while the signal on signal line (25) needs to quickly establish from the state "1" to the state "0". Therefore, during this period, the feedback signal and the signal that the signal on signal line (25) wants to establish conflict, which makes the establishment time of the signal state on signal line (25) from the state "1" to the state "0" even longer, affecting the response of the subsequent circuit. Summary of the Invention
[0007] The purpose of this invention is to provide a circuit that accelerates the setup time of long traces in a chip, thereby solving the problems in the background art.
[0008] To solve the above-mentioned technical problems, the present invention provides a circuit for accelerating the setup time of long traces in a chip, including a front-end BUFFER circuit, a back-end KEEPER circuit, a first MOS device, and a second MOS device; wherein the BUFFER circuit and the KEEPER circuit are connected in series.
[0009] The BUFFER circuit includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the input signal INPUT, and the output terminal is connected to the input terminal of the second inverter.
[0010] The KEEPER circuit includes a third inverter and a sixth inverter. The output terminal of the third inverter is connected to the input terminal of the sixth inverter, and the output terminal of the third inverter is the output terminal of the entire circuit.
[0011] The output terminal of the BUFFER circuit, i.e. the output terminal of the second inverter, is connected to the input terminal of the KEEPER circuit, i.e. the input terminal of the third inverter, via a signal line.
[0012] The source terminal of the second MOS device is connected to the GND signal, and the drain terminal is connected to the source terminal of the NMOS inside the sixth inverter; the source terminal of the first MOS device is connected to the Vcc signal, and the drain terminal is connected to the source terminal of the PMOS inside the sixth inverter; the gate terminals of the first MOS device and the second MOS device are respectively connected to separately supplied enable signals.
[0013] In one embodiment, the gate of the second MOS device is connected to an enable signal, and the gate of the first MOS device is connected to an enable_B signal; the enable signal and the enable_B signal are out of phase, meaning they cannot be turned on simultaneously.
[0014] In one embodiment, the first MOS device is a PMOS transistor, and the second MOS device is an NMOS transistor.
[0015] In one embodiment, in the KEEPER circuit, the output of the sixth inverter is fed back to the input of the third inverter to amplify the signal at the input of the third inverter.
[0016] In one embodiment, the power supply connected to the first inverter, the second inverter, the third inverter, and the sixth inverter is Vcc, and the ground is GND.
[0017] In one implementation, the internal structure of the first inverter, second inverter, third inverter, and sixth inverter does not limit the number and type of MOS transistors, as long as the inverter function is achieved.
[0018] In the circuit provided by this invention for accelerating the setup time of long traces in a chip, the conflicting effect of the previous state on the signal setup time on the signal line inside the KEEPER circuit can be eliminated by simply adding two switching MOS transistors. It is simple to operate, saves layout area, and saves costs. Attached Figure Description
[0019] Figure 1 The schematic diagram of an existing long-trace delay circuit;
[0020] Figure 2The schematic diagram of an existing long trace delay compensation circuit;
[0021] Figure 3 This invention provides a circuit schematic for accelerating the setup time of long traces in a chip. Detailed Implementation
[0022] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a circuit for accelerating the setup time of long traces in a chip according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0023] In large-scale SOC chip circuits or high-frequency chip circuits, when long transmission lines appear, in order to avoid excessive delay in the setup time of the input signal of the subsequent circuit due to RC loading caused by the long lines, this invention provides a circuit to accelerate the setup time of long lines in the chip. Its structure is as follows: Figure 3 As shown, it includes inverter 31, inverter 32, inverter 33, inverter 36, MOS device M1, and MOS device M2. The input terminal of inverter 31 is connected to the input signal 34, and the output terminal is connected to the input terminal of inverter 32. The output terminal of inverter 32 is connected to the input terminal of inverter 33 through signal line 35, and the output terminal of inverter 33 is the output terminal of the circuit. At the same time, the output terminal of inverter 33 is connected to the input terminal of inverter 36 through signal line 37, and the output terminal of inverter 36 is fed back to the input terminal of inverter 33. Through the feedback design of inverter 36, the signal of signal line 35 is strengthened. Meanwhile, MOS device M1 is a PMOS transistor. The source terminal of the PMOS transistor is connected to the power supply Vcc, the gate terminal 38 of the PMOS transistor is connected to the enable signal enable_B, and the drain terminal of the PMOS transistor is connected to the source terminal of the PMOS inside inverter 36. MOS device M2 is an NMOS transistor. The source terminal of the NMOS transistor is connected to ground GND, the gate terminal 39 of the NMOS transistor is connected to the enable signal enable, and the drain terminal is connected to the source terminal of the NMOS inside inverter 36.
[0024] The specific working principle of this invention is as follows:
[0025] When the input signal 34 is at a level of "1", after passing through the BUFFER circuit composed of inverters 31 and 32, the signal level remains at "1". Then, after passing through the long signal line 35, the large RC loading causes time for its transmission to the KEEPER circuit composed of inverters 33 and 36. Before the voltage level on signal line 35 rises to the threshold voltage Vth of the NMOS inside inverter 33, the signal level on signal line 37 remains at "1" (i.e., the lingering signal from the previous state). After passing through inverter 36, the signal level fed back to signal line 35 is "0". Signal line 35 needs to be pulled up to Vth (the threshold voltage Vth of the NMOS inside inverter 33) as quickly as possible for the entire circuit to function properly; therefore, this feedback signal is undesirable. The added NMOS transistor... M2, the source terminal of NMOS transistor M2 is connected to ground GND, and the drain terminal is connected to the source terminal of the NMOS inside inverter 36. Before the voltage level on signal line 35 rises to the threshold voltage Vth of the NMOS inside inverter 33, the gate terminal of NMOS transistor M2 is set to low level (enable), thereby turning off the feedback signal output of inverter 36 and shielding the influence of the previous state signal level on the feedback signal on signal line 37. When the voltage level on signal line 35 rises to the threshold voltage Vth, the gate terminal of NMOS transistor M2 is set to high level (enable). At this time, the signal level on signal line 37 is "0". After passing through inverter 36, the voltage level fed back to signal line 35 becomes "1", which accelerates the voltage level on signal line 35 and speeds up the signal establishment time on the long transmission line 35.Conversely, when the input signal 34 is at a level of "0", after passing through the BUFFER circuit, the signal level remains at "0". Then, after passing through the long signal line 35, the large RC loading causes time for its transmission to the KEEPER circuit. Before the voltage level on signal line 35 drops from the previous state "1" to the threshold voltage Vth of the PMOS inside inverter 33, the signal level on signal line 37 remains at "0" (a lingering signal from the previous state). After passing through inverter 36, the output signal fed back to signal line 35 is at a level of "1". Signal line 35 needs to drop below the threshold voltage Vth as quickly as possible for the entire circuit to function properly; therefore, this feedback signal is undesirable. This is addressed by adding the MOS device M1. The source terminal of PMOS transistor M1 is connected to ground GND, and the drain terminal is connected to the source terminal of the PMOS transistor inside inverter 36. The gate terminal of PMOS transistor M1 is set to a high level (enable_B), thereby turning off the feedback signal output of inverter 36 and shielding the influence of the previous state signal level on the feedback signal on signal line 37. When the voltage level on signal line 35 drops to the threshold voltage Vth, the gate terminal of PMOS transistor M1 is set to a low level (enable_B). At this time, the signal level on signal line 37 is "1". After passing through inverter 36, the voltage level fed back to signal line 35 becomes "0", which accelerates the voltage level on signal line 35 and speeds up the signal establishment time on the long transmission line 35.
[0026] This invention accelerates the signal establishment time on long trace signal line 35 by adding MOS devices M1 and M2 to inverter 36 and by reasonably designing the enable signals at their gate terminals to turn off inverter 36 during the delay period, thus shielding the influence of the lingering signal from the previous state at the signal line 37. Moreover, it only adds two MOS transistors and does not significantly increase the chip area.
[0027] In this invention, terms such as "connected," "linked," "connected," and "joined" indicate electrical connection, and unless otherwise specified, they refer to direct or indirect electrical connection. The power supply potential of all the inverters mentioned above is Vcc, and the ground potential is GND.
[0028] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A circuit for accelerating the setup time of long traces in a chip, characterized in that, It includes a front-end buffer circuit, a rear-end keeper circuit, a first MOS device, and a second MOS device; wherein the buffer circuit and the keeper circuit are connected in series. The BUFFER circuit includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the input signal INPUT, and the output terminal is connected to the input terminal of the second inverter. The KEEPER circuit includes a third inverter and a sixth inverter. The output of the third inverter is connected to the input of the sixth inverter, and the output of the third inverter is the output of the entire circuit. The output of the sixth inverter is fed back to the input of the third inverter to amplify the signal at the input of the third inverter. The output terminal of the BUFFER circuit, i.e. the output terminal of the second inverter, is connected to the input terminal of the KEEPER circuit, i.e. the input terminal of the third inverter, through the first signal line. The source terminal of the second MOS device is connected to the GND signal, and the drain terminal is connected to the source terminal of the NMOS inside the sixth inverter; the source terminal of the first MOS device is connected to the Vcc signal, and the drain terminal is connected to the source terminal of the PMOS inside the sixth inverter; the gate terminals of the first MOS device and the second MOS device are respectively connected to separately supplied enable signals. The gate of the second MOS device is connected to the enable signal, and the gate of the first MOS device is connected to the enable_B signal; the enable signal and the enable_B signal are inversely related, meaning they cannot be turned on simultaneously. The first MOS device is a PMOS transistor, and the second MOS device is an NMOS transistor; The gate of the second MOS device is connected to the enable signal, and the gate of the first MOS device is connected to the enable_B signal; the enable signal and the enable_B signal are inversely related and cannot be turned on simultaneously. When the input signal INPUT is at a level of "1", after passing through the BUFFER circuit, the signal level remains at "1". Then, it passes through the first signal line. Due to the large RC load, it takes time to transmit the signal to the KEEPER circuit. Before the voltage level on the first signal line rises to the threshold voltage Vth of the NMOS inside the third inverter, the signal level on the second signal line remains at "1". After passing through the sixth inverter, the signal level fed back to the first signal line is "0". The first signal line needs to be pulled high above Vth as soon as possible, as Vth is the threshold voltage of the NMOS inside the third inverter, for the entire circuit to function properly. The source terminal of the second MOS device is connected to ground (GND), and the drain terminal is connected to the first... Before the voltage level on the first signal line rises to the threshold voltage Vth of the NMOS inside the third inverter, the gate of the second MOS device is set to a low level, turning off the feedback signal output of the sixth inverter and shielding the influence of the previous state signal level on the feedback signal on the second signal line. When the voltage level on the first signal line rises to the threshold voltage Vth, the gate of the second MOS device is set to a high level. At this time, the signal level on the second signal line is "0". After passing through the sixth inverter, the voltage level fed back to the first signal line becomes "1", which accelerates the voltage level on the first signal line and speeds up the signal establishment time on the first signal line. Conversely, when the input signal INPUT level is "0", after passing through the BUFFER circuit, the signal level remains "0". Then, after passing through the first signal line, the large RC load causes time for the signal to reach the KEEPER circuit. Before the voltage level on the first signal line drops from the previous state "1" to the threshold voltage Vth of the PMOS inside the third inverter, the signal level on the second signal line remains "0". After passing through the sixth inverter, the output signal fed back to the first signal line is "1". The first signal line needs to drop below the threshold voltage Vth as quickly as possible for the entire circuit to function properly. This allows the power to be transmitted through the source of the first MOS device. The drain terminal is connected to ground (GND), and the drain terminal is connected to the source terminal of the PMOS inside the sixth inverter. The gate terminal of the first MOS device is set to a high level, turning off the feedback signal output of the sixth inverter and shielding the influence of the previous state signal level on the feedback signal on the second signal line. When the voltage level on the first signal line drops to the threshold voltage Vth, the gate terminal of the first MOS device is set to a low level. At this time, the signal level on the second signal line is "1". After passing through the sixth inverter, the voltage level fed back to the first signal line becomes "0", which accelerates the voltage level on the first signal line and speeds up the signal establishment time on the first signal line. The first signal line is the signal line between the second and third inverters, and the second signal line is the signal line between the third and sixth inverters.
2. The circuit for accelerating the setup time of long traces in a chip as described in claim 1, characterized in that, The power supply connected to the first inverter, the second inverter, the third inverter, and the sixth inverter is Vcc, and the ground connection is GND.
3. The circuit for accelerating the setup time of long traces in a chip as described in claim 1, characterized in that, The internal structure of the first inverter, second inverter, third inverter, and sixth inverter does not limit the number and type of MOS transistors, as long as the inverter function is achieved.