Analog-to-digital converter calibration method, device, equipment, storage medium and program product

Abstract

The present application relates to a method, apparatus, device, storage medium, and program product for calibrating an analog-to-digital converter. After initializing the capacitor array of a second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array via a control signal. Charge is injected into another row of capacitors in the capacitor array in sequence via a first set of capacitor preset control word signals and a second set of capacitor preset control word signals. The first result and the second result outputted in sequence by the second analog-to-digital converter are obtained. The second analog-to-digital converter is calibrated based on the first result and the second result. After calibrating the second analog-to-digital converter, the above steps are repeated to calibrate the first analog-to-digital converter. In the present application, since the minimum quantization accuracy of the capacitors included in the capacitor array is equal to #imgabs0#, capacitors with smaller quantization accuracy are used to reduce the quantization noise of the analog-to-digital converter, thereby achieving higher calibration accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital converters, and in particular to an analog-to-digital converter calibration method, apparatus, device, storage medium, and program product. Background Art

[0002] The analog-to-digital converter (ADC) is a core module that converts analog signals into digital signals. High-precision ADCs are widely used in fields such as military and electronics. Therefore, precise capacitor matching is required to achieve high ADC accuracy. For example, a two-stage pipelined successive approximation register (SAR) ADC must achieve a calibration accuracy of more than 16 bits.

[0003] Currently, ADC accuracy is calibrated by making the capacitors as symmetrical as possible on the layout to reduce the initial capacitance mismatch error of the calibration. However, this method has the problem of poor accuracy. Summary of the Invention

[0004] Based on this, it is necessary to provide an analog-to-digital converter calibration method, device, equipment, storage medium and program product that can improve calibration accuracy in response to the above technical problems.

[0005] In a first aspect, the present application provides an analog-to-digital converter calibration method, which is applied to an analog-to-digital converter calibration system, wherein the analog-to-digital converter calibration system includes a first analog-to-digital converter and a second analog-to-digital converter, wherein the output end of the first analog-to-digital converter is connected to the input end of the second analog-to-digital converter; the method includes:

[0006] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0007] Injecting charges into another row of capacitors of the capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of corresponding plates of the another row of capacitors;

[0008] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0009] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0010] In one embodiment, obtaining a first result and a second result sequentially output by the second analog-to-digital converter, and calibrating the second analog-to-digital converter according to the first result and the second result includes:

[0011] Obtaining a first result and a second result corresponding to each capacitor group outputted sequentially by the second analog-to-digital converter;

[0012] Determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group;

[0013] A first average value of mismatch results of a preset number of capacitor groups is determined, and the second analog-to-digital converter is calibrated according to the first average value.

[0014] In one embodiment, determining the mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group includes:

[0015] For each of the capacitor groups, determining a second average value of the first result and the second result corresponding to the capacitor group;

[0016] In one embodiment, the step of injecting charge into another row of capacitors in the capacitor array using the first group of capacitor preset control word signals and the second group of capacitor preset control word signals comprises:

[0017] generating a random code of a preset number of bits, and determining an interference signal according to the random code;

[0018] Charges are injected into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset control word signals and the determined second group of capacitor preset control word signals; the second group of capacitor preset control word signals includes the interference signal and the first group of capacitor preset control word signals.

[0019] In one embodiment, obtaining a first result and a second result sequentially output by the second analog-to-digital converter, and calibrating the second analog-to-digital converter according to the first result and the second result includes:

[0020] In a case where charges are sequentially injected into another row of capacitors of the capacitor array using the first group of capacitor preset control word signals and the second group of capacitor preset control word signals including the interference signal, obtaining a first result and a second result sequentially output by the second analog-to-digital converter, and removing a digital quantity corresponding to the interference signal from the second result to obtain a third result;

[0021] The second analog-to-digital converter is calibrated according to the first result and the third result.

[0022] In one embodiment, the analog-to-digital converter calibration system further includes an amplifier, wherein the amplifier is disposed between the first analog-to-digital converter and the second analog-to-digital converter; and the method further includes:

[0023] amplifying the signal output by the first analog-to-digital converter by the amplifier to obtain an amplified signal;

[0024] The amplified signal is input into the second analog-to-digital converter.

[0025] In a second aspect, the present application further provides an analog-to-digital converter calibration device, the device comprising:

[0026] Applicable to an analog-to-digital converter calibration system, the analog-to-digital converter calibration system includes a first analog-to-digital converter and a second analog-to-digital converter, the output end of the first analog-to-digital converter is connected to the input end of the second analog-to-digital converter; the device includes:

[0027] The first injection module is used to inject charge into one row of capacitors in the capacitor array through a control signal after initializing the capacitor array of the second analog-to-digital converter; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0028] a second injection module, configured to inject charges into another row of capacitors of the capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control connection conversion of corresponding plates of the another row of capacitors;

[0029] a first calibration module, configured to obtain a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0030] The second calibration module is configured to repeat the above steps to calibrate the first analog-to-digital converter after calibrating the second analog-to-digital converter.

[0031] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0032] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0033] Injecting charges into another row of capacitors of the capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of corresponding plates of the another row of capacitors;

[0034] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0035] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0036] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the following steps:

[0037] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0038] Injecting charges into another row of capacitors of the capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of corresponding plates of the another row of capacitors;

[0039] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0040] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0041] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the following steps:

[0042] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0043] Injecting charges into another row of capacitors of the capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of corresponding plates of the another row of capacitors;

[0044] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0045] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0046] The above-mentioned analog-to-digital converter calibration method, device, equipment, storage medium and program product, after initializing the capacitor array of the second analog-to-digital converter, injects charge into one row of capacitors in the capacitor array through a control signal, and injects charge into another row of capacitors in the capacitor array in sequence through a first group of capacitor preset control word signals and a second group of capacitor preset control word signals, obtains the first result and the second result outputted in sequence by the second analog-to-digital converter, calibrates the second analog-to-digital converter according to the first result and the second result, and after calibrating the second analog-to-digital converter, repeats the above steps to calibrate the first analog-to-digital converter; wherein the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1, and the first set of capacitor preset position control word signals and the second set of capacitor preset position control word signals are used to control the connection conversion of the corresponding plates of another row of capacitors. In this application, since the minimum quantization accuracy of the capacitors included in the capacitor array is equal to Using capacitors with smaller quantization precision reduces the quantization noise of the analog-to-digital converter, thereby achieving higher calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A diagram illustrating an application environment of an analog-to-digital converter calibration method according to an embodiment;

[0048] Figure 2 1 is a flow chart of a method for calibrating an analog-to-digital converter according to an embodiment;

[0049] Figure 3 is a schematic diagram of a second analog-to-digital converter in one embodiment;

[0050] Figure 4 is a schematic diagram of a flow chart of calibrating a second analog-to-digital converter in one embodiment;

[0051] Figure 5 FIG1 is a schematic diagram of a process of injecting charge into a capacitor according to an embodiment;

[0052] Figure 6 is a schematic diagram of a flow chart of calibrating a second analog-to-digital converter in another embodiment;

[0053] Figure 7 is a structural block diagram of an analog-to-digital converter calibration device in one embodiment;

[0054] Figure 8 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0056] The analog-to-digital converter calibration method provided in the embodiment of the present application can be applied to Figure 1 The ADC calibration system shown includes a first ADC 1 and a second ADC 2, wherein the output of the first ADC 1 is connected to the input of the second ADC 2. Both the first-stage ADC 1 and the second-stage ADC include a capacitor array. These can be two rows of capacitors, one row of which is N-terminal and the other is P-terminal, or multiple rows of capacitors can be used.

[0057] In one embodiment, Figure 2 As shown, a method for calibrating an analog-to-digital converter is provided. Figure 1 The analog-to-digital converter calibration system in FIG is taken as an example to illustrate the following steps:

[0058] S201, after initializing the capacitor array of the second analog-to-digital converter, injecting charge into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1.

[0059] In this embodiment, the second analog-to-digital converter is the above Figure 1 In ADC2, the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1. Figure 3As shown, the minimum quantization accuracy of the capacitor array of the second analog-to-digital converter is equal to 1 / 8, so the quantization noise can be reduced to 1 / 8LSB. LSB is the least significant bit, which is the minimum accuracy that the analog-to-digital converter can recognize.

[0060] In a possible implementation, the charge of each capacitor in the capacitor array of the second analog-to-digital converter is cleared first to complete the initialization process. Figure 3 As shown, the first plate of each capacitor in the capacitor array can be connected to any one of the common-mode voltage terminal, the first reference voltage terminal, and the second reference voltage terminal via a switch, and the second plate is connected to the common-mode voltage terminal via a switch. When both plates of the capacitor are connected to the common-mode voltage terminal at the same time, the capacitor array is initialized.

[0061] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors using a control signal. For example, the first plate of the 128LSB capacitor - 2LSB capacitor in one row is controlled to be connected to the first reference voltage terminal, and the first plate of the LSB capacitor - 1 / 8LSB capacitor in one row is controlled to be connected to the second reference voltage terminal. Alternatively, the first plates of all capacitors in one row may be connected to the first reference terminal voltage or the second reference terminal voltage.

[0062] S202, injecting charges into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of corresponding plates of the other row of capacitors.

[0063] Among them, first determine the capacitors in the other row that need to be converted into plates, such as Figure 3 As shown, the capacitor that needs to be plate-converted is the LSB capacitor-1 / 8LSB capacitor, or can be the 1 / 8LSB capacitor.

[0064] In this embodiment, charge is sequentially injected into another row of capacitors in the capacitor array using a first set of capacitor preset control word signals and a second set of capacitor preset control word signals. For example, the first set of capacitor preset control word signals connects all first plates of the capacitors in the other row to the first reference voltage terminal, resulting in a first output result. The first plates of the LSB capacitors - 1 / 8 LSB capacitors are then connected to the second reference voltage terminal, controlling the connection switching of the corresponding plates of the LSB capacitors - 1 / 8 LSB capacitors in the other row. The first plates of the remaining 128 LSB capacitors - 2 LSB capacitors remain connected to the first reference voltage terminal, resulting in a second output result.

[0065] It should be noted that the second set of capacitor preset control word signals only changes the charge state of the capacitors that require plate switching. If, when injecting charge into another row of capacitors in the capacitor array via the first set of capacitor preset control word signals, the first plate of the 128LSB capacitor - 2LSB capacitor is connected to the first reference voltage terminal, and the first plate of the LSB capacitor - 1 / 8LSB capacitor is connected to the second reference voltage terminal, then when performing the corresponding plate switching via the second set of capacitor preset control word signals, the first plate of the LSB capacitor - 1 / 8LSB capacitor is connected to the first reference voltage terminal.

[0066] S203 , obtaining a first result and a second result sequentially output by the second analog-to-digital converter, and calibrating the second analog-to-digital converter according to the first result and the second result.

[0067] In this embodiment, the first result and the second result are obtained before and after the above-mentioned plate conversion, respectively, and the mismatch result corresponding to the capacitor group undergoing the plate conversion is obtained according to the first result and the second result, so that the capacitor group undergoing the plate conversion is calibrated according to the mismatch result.

[0068] In one possible implementation, calibration is performed sequentially from the lower capacitors to complete the calibration of the second analog-to-digital converter. For example, if the capacitors to be converted are 1 / 8 LSB capacitors, the 1 / 8 LSB capacitors in both rows are calibrated simultaneously based on the first and second results.

[0069] S204: After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0070] In this embodiment, after the second analog-to-digital converter is calibrated, the first analog-to-digital converter is calibrated using the above steps. For example, after initializing the capacitor array of the first analog-to-digital converter, charge is injected into one row of capacitors, and then charge is injected into another row of capacitors in the capacitor array in sequence using the first set of capacitor preset control word signals and the second set of capacitor preset control word signals to obtain a first output result and a second output result of the first analog-to-digital converter. The first output result and the second output result are input into the second analog-to-digital converter for quantization to obtain a first result and a second result of the second analog-to-digital converter, and the first analog-to-digital converter is calibrated based on the first result and the second result.

[0071] Since the calibration accuracy of the first ADC is determined by the second ADC, the accuracy of the second ADC needs to be higher during calibration.

[0072] In the above-mentioned method for calibrating an analog-to-digital converter, after initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal, and charge is injected into another row of capacitors in the capacitor array in sequence through a first group of capacitor preset control word signals and a second group of capacitor preset control word signals, and a first result and a second result sequentially output by the second analog-to-digital converter are obtained. The second analog-to-digital converter is calibrated according to the first result and the second result. After calibrating the second analog-to-digital converter, the above-mentioned steps are repeated to calibrate the first analog-to-digital converter; wherein the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1, and the first set of capacitor preset position control word signals and the second set of capacitor preset position control word signals are used to control the connection conversion of the corresponding plates of another row of capacitors. In this application, since the minimum quantization accuracy of the capacitors included in the capacitor array is equal to Using capacitors with smaller quantization precision reduces the quantization noise of the analog-to-digital converter, thereby achieving higher calibration accuracy.

[0073] Figure 4 FIG. 1 is a flow chart of calibrating the second analog-to-digital converter in one embodiment. Figure 4 As shown, the embodiment of the present application relates to a possible implementation method of how to calibrate the second analog-to-digital converter according to the first result and the second result, including the following steps:

[0074] S401 , obtaining a first result and a second result corresponding to each capacitor group outputted sequentially by a second analog-to-digital converter.

[0075] The capacitor group can include two capacitors corresponding to 1 / 8 LSB, or two capacitors corresponding to 1 / 8 LSB and two capacitors corresponding to 1 / 4 LSB. This means that you can calibrate the two capacitors corresponding to 1 / 8 LSB at once, or you can calibrate the four capacitors, 1 / 8 LSB and 1 / 4 LSB, at the same time.

[0076] In this embodiment, after injecting charge into another row of capacitors through the first group of capacitor preset control word signals, the first result output by the analog-to-digital converter system is obtained; after injecting charge into another row of capacitors through the second group of capacitor preset control word signals, the second result output by the analog-to-digital converter system is obtained.

[0077] S402 : Determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group.

[0078] Determining the mismatch result of each capacitor group based on the first result and the second result corresponding to each capacitor group includes: determining, for each capacitor group, a second average value of the first result and the second result corresponding to the capacitor group; and determining the mismatch result of each capacitor group based on the second average value corresponding to each capacitor group.

[0079] In this embodiment, multiple first and second results can be obtained for each capacitor group, and the first and second results are averaged to obtain multiple second average values, which are used as the mismatch results of the capacitor group. For example, for the calibration of each capacitor group, 512 or more first and second results can be obtained, and a second average value is obtained for each first and second result, thereby obtaining multiple mismatch results for the capacitor group.

[0080] S403 , determining a first average value of mismatch results of a preset number of capacitor groups, and calibrating the second analog-to-digital converter according to the first average value.

[0081] In this embodiment, since multiple mismatch results can be obtained for each capacitor group, after obtaining multiple mismatch results for a capacitor group, an average is calculated to obtain a first average value, and the capacitor group is calibrated using the first average value. The above method is used to calibrate each capacitor group, thereby completing the calibration of the second analog-to-digital converter.

[0082] In the embodiment of the present application, a mismatch result is obtained by obtaining the first and second results corresponding to each capacitor group output sequentially by the second analog-to-digital converter, and the second analog-to-digital converter is calibrated based on a first average value of the mismatch results of a preset number of capacitor groups. In this embodiment, a method of multiple quantization and averaging is used to reduce the thermal noise of the calibration of the second analog-to-digital converter itself, thereby improving the calibration accuracy of the second analog-to-digital converter.

[0083] Figure 5 FIG. 1 is a flow chart of injecting charge into a capacitor in one embodiment. Figure 5 As shown, the embodiment of the present application relates to a possible implementation method of how to inject charges into another row of capacitors in a capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals, including the following steps:

[0084] S501: Generate a random code with a preset number of bits, and determine an interference signal according to the random code.

[0085] In this embodiment, a random code of a preset number of bits can be generated using a dither technique or a logic circuit. For example, a 4-bit random code can be fed into a dither DAC and the interference signal can be determined based on the random code.

[0086] S502 , injecting charges into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset control word signals and the determined second group of capacitor preset control word signals; the second group of capacitor preset control word signals includes an interference signal and the first group of capacitor preset control word signals.

[0087] In this embodiment, charge is sequentially injected into another row of capacitors in the capacitor array via a first set of capacitor preset control word signals. An interference signal generated by a random code of a preset number of bits can determine the capacitors that require plate switching. The charge state of the capacitors that require plate switching is determined by a second set of capacitor preset control word signals based on the interference signal and the first set of capacitor preset control word signals. For example, an interference signal generated by a 4-bit random code is input to the first plate of the LSB capacitor - 1 / 8 LSB capacitor, resulting in a switching of the first plate of the LSB capacitor - 1 / 8 LSB capacitor.

[0088] In an embodiment of the present application, a random code of a preset number of bits is generated, and an interference signal is determined based on the random code. Charge is then injected into another row of capacitors in the capacitor array in sequence using a first set of capacitor preset control word signals and a determined second set of capacitor preset control word signals; the second set of capacitor preset control word signals includes the interference signal and the first set of capacitor preset control word signals. In this embodiment, the dither technique can be used to break up the integral nonlinearity caused by the mismatch of the fixed capacitors, without affecting the effective number of bits (ENOB) and noise level of the second-stage analog-to-digital converter.

[0089] Figure 6 FIG. 1 is a flow chart of calibrating the second analog-to-digital converter in another embodiment. Figure 6 As shown, the embodiment of the present application relates to a possible implementation method of how to calibrate the second analog-to-digital converter according to the first result and the second result, including the following steps:

[0090] S601, while injecting charges into another row of capacitors in the capacitor array in sequence through a first group of capacitor preset control word signals and a second group of capacitor preset control word signals including an interference signal, obtain a first result and a second result output in sequence by a second analog-to-digital converter, and remove the digital value corresponding to the interference signal in the second result to obtain a third result.

[0091] In this embodiment, since the second group of capacitor preset position control word signals is determined based on the first group of capacitor preset position control word signals and the interference signal, when charges are injected into another row of capacitors in the capacitor array in sequence using the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals including the interference signal, the second result obtained by the second group of capacitor preset position control word signals includes the analog-to-digital conversion result corresponding to the interference signal, and the digital quantity corresponding to the interference signal in the second result is used to obtain the third result.

[0092] S602: Calibrate the second analog-to-digital converter according to the first result and the third result.

[0093] In this embodiment, a second average value of the first result and the third result is obtained, and the mismatch result of each capacitor group is obtained according to the second average value, so that the second analog-to-digital converter is calibrated according to the first average value of a preset number of mismatch results.

[0094] In one embodiment, the ADC calibration method further includes: amplifying the signal output by the first ADC by an amplifier to obtain an amplified signal; and inputting the amplified signal into the second ADC.

[0095] As mentioned above Figure 1 As shown, the analog-to-digital converter calibration system also includes an amplifier, which is arranged between the first analog-to-digital converter and the second analog-to-digital converter to increase the amplifier gain. The amplifier amplifies the signal output by the first analog-to-digital converter and inputs the amplified signal into the second analog-to-digital converter. This allows the output result of the analog-to-digital converter calibration system to be read more accurately, thereby reducing the requirements for quantization noise and thermal noise of the second analog-to-digital converter.

[0096] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0097] Based on the same inventive concept, embodiments of the present application also provide an analog-to-digital converter calibration device for implementing the aforementioned analog-to-digital converter calibration method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the analog-to-digital converter calibration device provided below can be found in the above-described limitations of the analog-to-digital converter calibration method and are not further elaborated here.

[0098] In one embodiment, Figure 7 As shown, an analog-to-digital converter calibration device is provided, comprising: a first injection module 11, a second injection module 12, a first calibration module 13 and a second calibration module 14:

[0099] The first injection module 11 is used to inject charge into one row of capacitors in the capacitor array through a control signal after initializing the capacitor array of the second analog-to-digital converter; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0100] A second injection module 12 is used to inject charges into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of the corresponding plates of the other row of capacitors;

[0101] A first calibration module 13 is configured to obtain a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0102] The second calibration module 14 is configured to repeat the above steps to calibrate the first analog-to-digital converter after calibrating the second analog-to-digital converter.

[0103] In one embodiment, the first calibration module includes:

[0104] a first acquiring unit, configured to acquire a first result and a second result corresponding to each capacitor group outputted sequentially by the second analog-to-digital converter;

[0105] a first determining unit, configured to determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group;

[0106] The second determining unit is configured to determine a first average value of mismatch results of a preset number of capacitor groups, and calibrate the second analog-to-digital converter according to the first average value.

[0107] In one embodiment, the first determining unit is further configured to determine, for each capacitor group, a second average value of the first result and the second result corresponding to the capacitor group; and determine a mismatch result of each capacitor group based on the second average value corresponding to each capacitor group.

[0108] In one embodiment, the second injection module includes:

[0109] A generating unit, configured to generate a random code of a preset number of bits and determine an interference signal according to the random code;

[0110] The injection unit is used to inject charges into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset position control word signals and the determined second group of capacitor preset position control word signals; the second group of capacitor preset position control word signals includes the interference signal and the first group of capacitor preset position control word signals.

[0111] In one embodiment, the first calibration module includes:

[0112] a second acquiring unit, configured to acquire, when charges are sequentially injected into another row of capacitors in the capacitor array using the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals including the interference signal, the first result and the second result sequentially output by the second analog-to-digital converter, and to obtain a third result by removing the digital quantity corresponding to the interference signal from the second result;

[0113] The calibration unit is configured to calibrate the second analog-to-digital converter according to the first result and the third result.

[0114] In one embodiment, the analog-to-digital converter calibration apparatus further comprises:

[0115] an amplifying module, configured to amplify the signal output by the first analog-to-digital converter by an amplifier to obtain an amplified signal;

[0116] The input module is used to input the amplified signal into the second analog-to-digital converter.

[0117] Each module in the analog-to-digital converter calibration device described above can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0118] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 8As shown. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store data related to the analog-to-digital converter. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements an analog-to-digital converter calibration method.

[0119] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0120] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0121] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0122] Injecting charges into another row of capacitors in the capacitor array sequentially through the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of the corresponding plates of the other row of capacitors;

[0123] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0124] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0125] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0126] Obtaining a first result and a second result corresponding to each capacitor group outputted sequentially by the second analog-to-digital converter;

[0127] Determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group;

[0128] A first average value of mismatch results of a preset number of capacitor groups is determined, and the second analog-to-digital converter is calibrated according to the first average value.

[0129] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0130] For each capacitor group, determining a second average value of the first result and the second result corresponding to the capacitor group;

[0131] The mismatch results of the capacitor groups are determined according to the second average values ​​corresponding to the capacitor groups.

[0132] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0133] Generate a random code of a preset number of bits, and determine the interference signal according to the random code;

[0134] Charges are injected into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset control word signals and the determined second group of capacitor preset control word signals; the second group of capacitor preset control word signals includes interference signals and the first group of capacitor preset control word signals.

[0135] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0136] In a case where charges are sequentially injected into another row of capacitors in the capacitor array using the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals including the interference signal, a first result and a second result sequentially output by the second analog-to-digital converter are obtained, and a digital quantity corresponding to the interference signal in the second result is removed to obtain a third result;

[0137] The second analog-to-digital converter is calibrated according to the first result and the third result.

[0138] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0139] amplifying the signal output by the first analog-to-digital converter by an amplifier to obtain an amplified signal;

[0140] The amplified signal is input into the second analog-to-digital converter.

[0141] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0142] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0143] Injecting charges into another row of capacitors in the capacitor array sequentially through the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of the corresponding plates of the other row of capacitors;

[0144] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0145] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0146] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0147] Obtaining a first result and a second result corresponding to each capacitor group outputted sequentially by the second analog-to-digital converter;

[0148] Determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group;

[0149] A first average value of mismatch results of a preset number of capacitor groups is determined, and the second analog-to-digital converter is calibrated according to the first average value.

[0150] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0151] For each capacitor group, determining a second average value of the first result and the second result corresponding to the capacitor group;

[0152] The mismatch results of the capacitor groups are determined according to the second average values ​​corresponding to the capacitor groups.

[0153] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0154] Generate a random code of a preset number of bits, and determine the interference signal according to the random code;

[0155] Charges are injected into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset control word signals and the determined second group of capacitor preset control word signals; the second group of capacitor preset control word signals includes interference signals and the first group of capacitor preset control word signals.

[0156] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0157] In a case where charges are sequentially injected into another row of capacitors in the capacitor array using the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals including the interference signal, a first result and a second result sequentially output by the second analog-to-digital converter are obtained, and a digital quantity corresponding to the interference signal in the second result is removed to obtain a third result;

[0158] The second analog-to-digital converter is calibrated according to the first result and the third result.

[0159] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0160] amplifying the signal output by the first analog-to-digital converter by an amplifier to obtain an amplified signal;

[0161] The amplified signal is input into the second analog-to-digital converter.

[0162] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0163] After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1;

[0164] Injecting charges into another row of capacitors in the capacitor array sequentially through the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals, wherein the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals are used to control the connection conversion of the corresponding plates of the other row of capacitors;

[0165] Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result;

[0166] After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

[0167] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0168] Obtaining a first result and a second result corresponding to each capacitor group outputted sequentially by the second analog-to-digital converter;

[0169] Determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group;

[0170] A first average value of mismatch results of a preset number of capacitor groups is determined, and the second analog-to-digital converter is calibrated according to the first average value.

[0171] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0172] For each capacitor group, determining a second average value of the first result and the second result corresponding to the capacitor group;

[0173] The mismatch results of the capacitor groups are determined according to the second average values ​​corresponding to the capacitor groups.

[0174] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0175] Generate a random code of a preset number of bits, and determine the interference signal according to the random code;

[0176] Charges are injected into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset control word signals and the determined second group of capacitor preset control word signals; the second group of capacitor preset control word signals includes interference signals and the first group of capacitor preset control word signals.

[0177] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0178] In a case where charges are sequentially injected into another row of capacitors in the capacitor array using the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals including the interference signal, a first result and a second result sequentially output by the second analog-to-digital converter are obtained, and a digital quantity corresponding to the interference signal in the second result is removed to obtain a third result;

[0179] The second analog-to-digital converter is calibrated according to the first result and the third result.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0181] amplifying the signal output by the first analog-to-digital converter by an amplifier to obtain an amplified signal;

[0182] The amplified signal is input into the second analog-to-digital converter.

[0183] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0184] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0185] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for calibrating an analog-to-digital converter, characterized in that: The method is applied to an analog-to-digital converter calibration system, the analog-to-digital converter calibration system comprising a first analog-to-digital converter and a second analog-to-digital converter, wherein the output end of the first analog-to-digital converter is connected to the input end of the second analog-to-digital converter; the method comprises: After initializing the capacitor array of the second analog-to-digital converter, charge is injected into one row of capacitors in the capacitor array through a control signal; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1; injecting charges into another row of capacitors in the capacitor array in sequence through a first group of capacitor preset position control word signals and a second group of capacitor preset position control word signals; Acquire a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result; After calibrating the second analog-to-digital converter, repeat the above steps to calibrate the first analog-to-digital converter.

2. The method according to claim 1, characterized in that The acquiring the first result and the second result sequentially output by the second analog-to-digital converter, and calibrating the second analog-to-digital converter according to the first result and the second result, includes: Obtaining a first result and a second result corresponding to each capacitor group outputted sequentially by the second analog-to-digital converter; Determine a mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group; A first average value of mismatch results of a preset number of capacitor groups is determined, and the second analog-to-digital converter is calibrated according to the first average value.

3. The method according to claim 2, characterized in that Determining the mismatch result of each capacitor group according to the first result and the second result corresponding to each capacitor group includes: For each of the capacitor groups, determining a second average value of the first result and the second result corresponding to the capacitor group; The mismatch result of each capacitor group is determined according to the second average value corresponding to each capacitor group.

4. The method according to claim 1, wherein The step of sequentially injecting charges into another row of capacitors in the capacitor array using the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals comprises: generating a random code of a preset number of bits, and determining an interference signal according to the random code; Charges are injected into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset control word signals and the determined second group of capacitor preset control word signals; the second group of capacitor preset control word signals includes the interference signal and the first group of capacitor preset control word signals.

5. The method according to claim 4, characterized in that The acquiring the first result and the second result sequentially output by the second analog-to-digital converter, and calibrating the second analog-to-digital converter according to the first result and the second result, includes: In a case where charges are sequentially injected into another row of capacitors of the capacitor array using the first group of capacitor preset control word signals and the second group of capacitor preset control word signals including the interference signal, obtaining a first result and a second result sequentially output by the second analog-to-digital converter, and removing a digital quantity corresponding to the interference signal from the second result to obtain a third result; The second analog-to-digital converter is calibrated according to the first result and the third result.

6. The method according to claim 1, characterized in that The analog-to-digital converter calibration system further includes an amplifier, which is arranged between the first analog-to-digital converter and the second analog-to-digital converter; the method further includes: amplifying the signal output by the first analog-to-digital converter by the amplifier to obtain an amplified signal; The amplified signal is input into the second analog-to-digital converter.

7. An analog-to-digital converter calibration device, characterized in that: Applicable to an analog-to-digital converter calibration system, the analog-to-digital converter calibration system includes a first analog-to-digital converter and a second analog-to-digital converter, the output end of the first analog-to-digital converter is connected to the input end of the second analog-to-digital converter; the device includes: The first injection module is used to inject charge into one row of capacitors in the capacitor array through a control signal after initializing the capacitor array of the second analog-to-digital converter; the minimum quantization accuracy of the capacitors included in the capacitor array is equal to n is an integer greater than or equal to 1; A second injection module is used to inject charges into another row of capacitors in the capacitor array in sequence through the first group of capacitor preset position control word signals and the second group of capacitor preset position control word signals; a first calibration module, configured to obtain a first result and a second result sequentially output by the second analog-to-digital converter, and calibrate the second analog-to-digital converter according to the first result and the second result; The second calibration module is configured to repeat the above steps to calibrate the first analog-to-digital converter after calibrating the second analog-to-digital converter.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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