A high-precision differential sample-and-hold circuit

Abstract

The application discloses a high-precision differential sample-and-hold circuit, which comprises a differential input voltage translation circuit, an auxiliary differential input buffer stage, auxiliary sample-and-hold switches SWX3 and SWX4, a differential gate voltage bootstrap sample-and-hold switch circuit and a high input impedance buffer output stage; when the circuit is in a sampling state, the sampling switches SW1 and SW2, the isolation switches SWX1 and SWX2, the auxiliary sample-and-hold switches SWX3 and SWX4 are all closed, and an input signal charges an anti-aliasing filter capacitor; when the circuit enters a holding state, the differential gate voltage bootstrap sample-and-hold switch circuit first turns off the sampling switches, and then the auxiliary sample-and-hold switches and the isolation switches are simultaneously turned off, so that the voltage signal at the end of the sampling state is held on the filter capacitor and is output to a subsequent stage through the buffer output stage; the circuit has high input impedance and can accept a higher signal source output impedance; the differential gate voltage bootstrap sample-and-hold circuit does not have significant clock feedthrough and charge injection errors, and the holding precision is ensured.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a high-precision differential sample-and-hold circuit. BACKGROUND

[0002] The sample-and-hold circuit is a common circuit in the field of signal chain processing, which is used to collect and hold the input signal, and then convert the input signal into a digital signal by a subsequent analog-to-digital converter (ADC). The differential signal avoids the influence of common-mode noise, and is beneficial to obtain higher precision.

[0003] The commonly used differential sample-and-hold circuit is usually a switched-capacitor sample-and-hold circuit composed of switches, holding capacitors and a fully differential amplifier. Due to the existence of gate-drain and gate-source parasitic capacitances of MOS transistors, clock feedthrough and charge injection effects will occur when the switches are switched. When the input signal is large, that is, the difference between the gate-source voltages of the two MOS switch tubes in the differential signal path is large, the non-linear error caused by these non-ideal characteristics significantly increases. With the help of the fully differential amplifier, the switch on the virtual ground side is closed first, and then the switch connected to the input signal is closed, which can effectively avoid the transmission of clock feedthrough and charge injection errors to the holding capacitor.

[0004] The sampling circuit based on switched capacitors needs a signal source or a buffer to charge and discharge the switched capacitors. When the output impedance of the signal source is high, a pre-buffer is necessary, so as to ensure the sampling accuracy. In addition, in order to improve the signal-to-noise ratio and reduce the Aliasing noise caused by sampling, an anti-aliasing filter is often added in the front stage.

[0005] It can be seen that the actual high-precision sample-and-hold circuit often includes an anti-aliasing filter, an input buffer stage and a subsequent sample-and-hold amplifier. In order to reduce the overall cost, the application realizes a high-precision differential sample-and-hold circuit without a fully differential amplifier, and integrates an anti-aliasing filter and a high-input-impedance buffer. SUMMARY

[0006] In order to overcome the shortcomings and deficiencies of the prior art, the application provides a high-precision differential sample-and-hold circuit.

[0007] The technical scheme adopted by the application is a high-precision differential sample-and-hold circuit, which comprises a differential input voltage translation circuit, an auxiliary differential input buffer stage, auxiliary sample-and-hold switches SWX3 and SWX4, a differential gate voltage bootstrap sample-and-hold switch circuit and a high-input-impedance buffer output stage.

[0008] The differential gate voltage bootstrap sample-and-hold switch circuit comprises a gate voltage bootstrap control circuit, sample switches SW1 and SW2, isolation switches SWX1 and SWX2, and an RC anti-aliasing filter.

[0009] When the circuit is in the sampling state, the sampling switches SW1 and SW2, the isolation switches SWX1 and SWX2, and the auxiliary sampling and holding switches SWX3 and SWX4 are closed, and the input signal charges the anti-aliasing filter capacitor; when the circuit enters the holding state, the differential gate voltage bootstrap sampling and holding switch circuit first turns off the sampling switch, and then the auxiliary sampling and holding switches and the isolation switches are turned off at the same time, and the voltage signal at the end of the sampling state is held on the filter capacitor and output to the subsequent stage through the buffer output stage.

[0010] Further, the differential gate voltage bootstrap control circuit is used to separate the gate-source voltage and the gate-drain voltage of the sampling switch in the on and off states from the amplitude of the differential signal, so as to avoid the non-linear problems caused by the asymmetric clock feedthrough and charge injection when the switch is turned off.

[0011] Further, the isolation switches SWX1 and SWX2 are used to isolate the input signal from the sampling and holding circuit during the holding state, so as to avoid the interference of the input signal through the parasitic capacitor of the sampling switch to the signal stored on the capacitor.

[0012] Further, the RC anti-aliasing filter is used to filter the circuit, and is also used as a storage unit and to hold the sampled signal in the holding state.

[0013] Further, the auxiliary differential input buffer stage is used to drive the gate voltage bootstrap control circuit, so as to avoid the interference of the switch action to the input signal source.

[0014] Further, when the sampling switch is turned off, the differential gate voltage bootstrap sampling and holding switch circuit no longer provides a ground voltage to the gate of the sampling switch, but provides a source voltage; after the differential gate voltage bootstrap sampling and holding switch circuit enters the holding state, the auxiliary sampling and holding circuit also enters the holding state, thereby isolating the input signal from the auxiliary differential input buffer stage, so that the gate-source voltage of the sampling switch is stabilized at 0V and always in the off state.

[0015] Further, the differential input voltage translation circuit is used to translate the input voltage by a gate-source voltage drop, so that the output voltage of the auxiliary differential input buffer stage is equal.

[0016] The high-precision differential sampling and holding circuit has the following effects:

[0017] This invention proposes a high-precision differential sample-and-hold circuit that eliminates the need for a fully differential amplifier, saving cost and power consumption of the common-mode feedback circuit. It also integrates an anti-aliasing low-pass filter and a hold circuit, further reducing costs. The circuit features high input impedance, allowing it to accept higher signal source output impedance. The invented differential gate voltage bootstrap sample-and-hold circuit does not exhibit significant clock feedthrough and charge injection errors, ensuring hold accuracy. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the high-precision differential sample-and-hold circuit structure of the present invention;

[0019] Figure 2 This is a schematic diagram of the preferred gate voltage bootstrap control circuit structure of the present invention. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 As shown, a high-precision differential sample-and-hold circuit includes a differential input voltage shifting circuit, an auxiliary differential input buffer stage, an auxiliary sample-and-hold switch, a differential gate voltage bootstrap sample-and-hold switch, and a high input impedance buffer output stage.

[0022] The core module of the invented solution is a differential gate voltage bootstrap sample-and-hold circuit, including a gate voltage bootstrap control circuit, sampling switches SW1 and SW2, isolation switches SWX1 and SWX2, and an RC anti-aliasing filter.

[0023] The function of the gate voltage bootstrap control circuit is to ensure that the gate-source and gate-drain voltages of the sampling switch are independent of the amplitude of the differential signal when the switch is on and off, thereby avoiding nonlinear problems caused by asymmetric clock feedthrough and charge injection when the switch is off.

[0024] An isolating switch is used to isolate the input signal from the sample-and-hold circuit during the hold state, thereby preventing the input signal from interfering with the signal stored on the capacitor through the parasitic capacitance of the sampling switch.

[0025] The RC anti-aliasing filter not only performs filtering functions, but also serves as a storage unit to maintain the sampled signal.

[0026] The adopted gate voltage bootstrap control circuit is different from the traditional gate voltage bootstrap circuit. The main purpose of the traditional gate voltage bootstrap circuit is to ensure that the on impedance of the sampling switch does not change with the change of the input voltage. However, there are two shortcomings: firstly, the bootstrap circuit directly collects voltage from the input signal, which requires the input signal source to have a low enough impedance, otherwise the switching action of the bootstrap circuit will interfere with the input signal; secondly, in the off state, the gate voltage of the sampling switch provided by the traditional bootstrap circuit is ground, which means that when a large differential input signal is to be maintained, the change amount of the gate-drain voltage of the differential switch tube is greatly different. This difference causes the difference in clock feedthrough and charge injection, thereby causing the accuracy of the hold voltage to decrease.

[0027] To solve the first drawback, the application adopts an auxiliary differential input buffer stage to drive the gate voltage bootstrap control circuit, avoiding the switching action from interfering with the input signal source.

[0028] To solve the second drawback, the application adopts an improved gate voltage bootstrap control circuit. In the off state (i.e. corresponding to the hold state of the sample and hold), the gate voltage of the sampling switch provided by the bootstrap control circuit is no longer ground, but the source voltage. In addition, when the differential gate voltage bootstrap sample and hold circuit enters the hold state, the auxiliary sample and hold circuit also enters the hold state, thereby isolating the input signal from the auxiliary differential input buffer stage and ensuring that the gate-source voltage of the sampling switch is stable at 0V and always in the off state. In this way, the gate-source and gate-drain voltages of the differential sampling tube are consistent before and after the hold state, avoiding significant clock feedthrough and charge injection errors.

[0029] The differential input voltage translation circuit translates the input voltage by a gate-source voltage drop, so that the output voltage of the auxiliary differential input buffer stage is equal.

[0030] The basic working state of the circuit is: when the circuit is in the sampling state, the sampling switches SW1 and SW2, the isolation switches SWX1 and SWX2, and the auxiliary sampling switches SWX3 and SWX4 are all closed, and the input signal charges the anti-aliasing filter capacitor; when the circuit enters the hold state, the gate voltage bootstrap control circuit first turns off the sampling switch, and then the auxiliary sampling switch and the isolation switch are turned off at the same time, and the voltage signal at the end of the sampling state is held on the filter capacitor and output to the next stage through the buffer output stage.

[0031] Figure 1 The circuit is a specific implementation method.

[0032] The voltage translation circuit adopts diode connection instead of source follower connection of the auxiliary differential input buffer stage. The advantage is to avoid the error caused by the drain-source voltage difference of IMIPAX1 / MPAX2 when the input signal is large. The auxiliary differential input buffer stage is only used to drive the gate voltage bootstrap control circuit, which can accept the error. The equivalent input impedance of the voltage translation circuit is the current source equivalent output impedance, which can easily reach more than 10 Mohm.

[0033] Figure 2 The preferred gate voltage bootstrap control circuit is shown in the figure. The circuit diagram is for the control circuit generated by the sampling switch SW1, and the principle is applicable to the sampling switch SW2. The inverter, N1, N2, N3, N4, N5, N7, P2, P3, bootstrap capacitor Cbt, and switch SW1DUP constitute a traditional gate voltage bootstrap circuit. The traditional circuit structure cooperates with P1, N6, N8 to generate the required new function.

[0034] When ENB_HOLD is high, switches N2, N5, N6, N7, N8 are turned off, and switches N4, P1, P2 are turned on. At this time, the output ENSWP of the control circuit is equal to the gate voltage of the switch SW1DUP, both connected to the upper plate of Cbt, and the drain voltage of the switch SW1DUP is equal to the lower plate voltage of Cbt. The gate-drain and gate-source voltages of the switch are maintained at the voltage on the bootstrap capacitor, and the switch is in the on state. At this time, the sampling switch is also in the on sampling state.

[0035] When ENB_HOLD is low, N2 switch is turned on, and the power supply voltage maintains the bootstrap capacitor Cbt in a full state. P1, P2 are turned off, the gate of the switch SW1DUP is pulled down to ground by switches N7 and N5, the switch SW1DUP is turned off, and the output ENSWP of the control circuit is pulled down to the input signal VIPX by switches N8 and N6 instead of the ground level. This ensures that when the sampling switches SW1 and SW2 are turned off, the voltage variation of the gate-source and gate-drain is consistent, avoiding the error caused by clock feedthrough and charge injection.

[0036] The single-ended output buffer output can use traditional source follower or super source follower and other low-cost circuits.

[0037] A high-precision differential sample-and-hold circuit, which does not require a full-differential amplifier, saves the cost and power consumption of the common-mode feedback circuit; combines the anti-aliasing low-pass filter and the holding circuit, saving cost; the circuit has high input impedance and can accept high signal source output impedance; the invented differential gate voltage bootstrap sample-and-hold circuit does not have significant clock feedthrough and charge injection error, ensuring the holding accuracy.

[0038] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "arranged", "mounted", "connected", "linked", "fixed" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, can be electrically connected; can be directly connected, can be indirectly connected through an intermediate medium, or can be internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0039] Although embodiments of the present application have been shown and described, it would be appreciated by those of ordinary skill in the art that various equivalents, modifications, replacements and variations of these embodiments can be made without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalent scope.

Claims

1. A high precision differential sample-and-hold circuit, characterized by The circuit comprises a differential input voltage translation circuit, an auxiliary differential input buffer stage, auxiliary sample-and-hold switches SWX3 and SWX4, a differential gate voltage self-boosting sample-and-hold switch circuit and a high input impedance buffer output stage. The differential gate voltage self-boosting sample-and-hold circuit comprises a gate voltage self-boosting control circuit, sample switches SW1 and SW2, isolation switches SWX1 and SWX2 and an RC anti-aliasing filter. When the circuit is in a sampling state, the sample switches SW1 and SW2, the isolation switches SWX1 and SWX2 and the auxiliary sample-and-hold switches SWX3 and SWX4 are closed, and the input signal charges the anti-aliasing filter capacitor; when the circuit enters a holding state, the differential gate voltage self-boosting sample-and-hold switch circuit first turns off the sample switches, and then the auxiliary sample-and-hold switches and the isolation switches are turned off at the same time, so that the voltage signal at the end of the sampling state is held on the filter capacitor and output to the subsequent stage through the buffer output stage. When the differential gate voltage self-boosting sample-and-hold switch circuit turns off the sample switches, the gate voltage of the sample switches is no longer ground but the source voltage; after the differential gate voltage self-boosting sample-and-hold switch circuit enters the holding state, the auxiliary sample-and-hold circuit also enters the holding state, thereby isolating the input signal from the auxiliary differential input buffer stage and stabilizing the gate-source voltage of the sample switches at 0V and always in the off state.

2. A high precision differential sample-and-hold circuit as claimed in claim 1, characterized in that, The differential gate voltage self-boosting control circuit is used to separate the gate-source and gate-drain voltages of the sample switches in the on and off states from the amplitude of the differential signal, so as to avoid the non-linear problems caused by the asymmetric clock feedthrough and charge injection when the switch is turned off.

3. A high precision differential sample-and-hold circuit as claimed in claim 1, characterized in that, The isolation switches SWX1 and SWX2 are used to isolate the input signal from the sample-and-hold circuit during the holding state, so as to avoid the input signal from disturbing the signal stored on the capacitor through the parasitic capacitor of the sample switches.

4. A high precision differential sample-and-hold circuit as claimed in claim 1, characterized in that, The RC anti-aliasing filter is used to filter the circuit, and also used as a storage unit in the holding state and to hold the sampled signal.

5. A high precision differential sample-and-hold circuit as claimed in claim 1, characterized in that, The auxiliary differential input buffer stage is used to drive the gate voltage self-boosting control circuit, so as to avoid the interference of switch action to the input signal source.

6. A high precision differential sample-and-hold circuit as claimed in claim 1, characterized in that, The differential input voltage translation circuit is used to translate the input voltage by a gate-source voltage drop, so as to be equal to the output voltage of the auxiliary differential input buffer stage.

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