A Phase Domain Quantization Residual Detection Module for Continuous-Time Sigma-Delta Modulator

Abstract

The present invention proposes a phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator, comprising a rising edge and a falling edge D flip-flop, a two-input NAND gate, a quantization phase detection circuit with positive and negative polarities, and a two-input AND gate. The quantization residual of each level is obtained by detecting the phase of a sampling clock and input data, and is converted into a square wave signal with different duty cycles in the time domain, so as to serve as the input of a subsequent cascaded Sigma-Delta modulator. A solution is provided for the MASH structure of a continuous-time Sigma-Delta modulator based on a voltage-controlled oscillator. The invention improves and retains the advantage of fast working speed of the phase domain quantization residual through a simple circuit, and effectively avoids the problem of inaccurate output residual due to relying on mutual reference of multi-level data.

Description

Technical Field

[0001] The invention discloses a phase domain quantization residual error detection module for a continuous-time Sigma-Delta modulator, belongs to the technical field of analog integrated circuits, and is mainly applied to a continuous-time Sigma-Delta analog-to-digital converter based on a voltage-controlled oscillator. Background Art

[0002] In the current era of social informatization and networking, the popularization and use of various electronic devices have brought great changes to people's daily life and social production methods. Especially during the epidemic, online office, registration and clocking in all rely on the popularization and use of electronic information products. The signals in nature exist in the form of analog quantities, and the data in electronic devices exist in the form of digital quantities. Among them, the analog-to-digital converter is the core circuit that converts analog quantities into digital quantities. The system architecture of the analog-to-digital converter is mainly divided into two categories, which are divided into Nyquist-like type and oversampling type according to the different ways of using the sampling theorem. As a common structure of oversampling analog-to-digital converters, Sigma-Delta analog-to-digital converters can be divided into two types in structure: discrete time type and continuous time type. Among them, the continuous-time Sigma-Delta analog-to-digital converter is widely used in various communication electronic products due to its high speed and high precision.

[0003] In recent years, with the advancement of process technology, higher requirements have been placed on the circuit power consumption and area of ​​analog-to-digital converters. The continuous-time Sigma-Delta analog-to-digital converter based on voltage-controlled oscillator has a voltage-controlled oscillator as its main structure. As the process size decreases, its operating frequency becomes higher, which can improve its ability to process analog signals in the phase domain. At the same time, the circuit area and power consumption are effectively reduced, meeting the development direction of lightweight chips and low power consumption.

[0004] However, the continuous-time Sigma-Delta modulator based on the voltage-controlled oscillator processes the analog signal in the phase domain, and the obtained quantization residual is expressed in the phase domain, which is difficult to directly serve as the input signal of the subsequent cascaded Sigma-Delta modulator, restricting the realization of high-precision cascade modulators.

[0005] Therefore, for the cascaded continuous-time Sigma-Delta modulator based on voltage-controlled oscillator, phase domain quantization residual detection between stages is necessary. By detecting the phase domain quantization residual of the previous stage and then converting the residual from the phase domain to a voltage domain signal, the cascading of multiple continuous-time Sigma-Delta modulators can be achieved. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and propose a phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator. By improving the structure of the circuit, the phase domain quantization residual detection function is realized. At the same time, the output phase residual is only determined by the sampling clock and the input data, which solves the problem that the ordinary structure needs to rely on multi-level data for mutual reference. The module can be widely used in continuous-time Sigma-Delta modulators with phase domain quantization.

[0007] The technical solution to achieve the purpose of the present invention is:

[0008] A phase domain quantization residual detection module for a continuous time Sigma-Delta modulator comprises rising edge and falling edge D flip-flops for obtaining input signals with different edges; a two-input NAND gate for resetting a detection circuit; a positive and negative polarity quantization phase detection circuit for obtaining a phase difference between a sampling clock and signals with different edges; and a two-input AND gate for obtaining a quantization residual in the phase domain of an input signal.

[0009] Among them, the input terminal of the rising edge trigger DFF1 of the positive polarity quantization phase detection circuit is connected to a fixed high level, the clock terminal is connected to the input port DATA, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; the input terminal of the rising edge trigger DFF2 is connected to a fixed high level, the clock terminal is connected to the input port CLK, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; one of the input terminals of the two-input NAND gate is connected to the output of DFF1, the other input terminal is connected to the output of DFF2, and the output terminal is connected to the reset of DFF1 and DFF2.

[0010] The input terminal of the falling edge trigger DFF3 of the negative polarity quantization phase detection circuit is connected to a fixed high level, the clock terminal is connected to the input port DATA, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; the input terminal of the rising edge trigger DFF4 is connected to a fixed high level, the clock terminal is connected to the input port CLK, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; one of the inputs of the two-input NAND gate is connected to the output of DFF3, the other input terminal is connected to the output of DFF4, and the output terminal is connected to the reset of DFF3 and DFF4.

[0011] The clock terminal of the positive polarity quantization phase detection module QPD_P1 of the first stage of the phase domain quantization residual detection circuit is connected to the external sampling clock port CLK, the input terminal is connected to the external first data input port DATA[1], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the negative polarity quantization phase detection module QPD_N1 of the first stage is connected to the external sampling clock port CLK, the input terminal is connected to the external first data input port DATA[1], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_P1, and the other input terminal is connected to the output of QPD_N1, and the output of the AND gate is the corresponding first-stage phase domain quantization residual Tq[1].

[0012] The clock terminal of the second-stage positive polarity quantization phase detection module QPD_P2 of the phase domain quantization residual detection circuit is connected to the external sampling clock port CLK, the input terminal is connected to the external second-bit data input port DATA[2], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the second-stage negative polarity quantization phase detection module QPD_N2 is connected to the external sampling clock port CLK, the input terminal is connected to the external second-bit data input port DATA[2], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_P2, and the other input terminal is connected to the output of QPD_N2, and the output of the AND gate is the corresponding second-stage phase domain quantization residual Tq[2].

[0013] By analogy, the clock terminal of the positive polarity quantization phase detection module QPD_Pn of the phase domain quantization residual detection circuit at the nth level is connected to the external sampling clock port CLK, the input terminal is connected to the external nth bit data input port DATA[n], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the negative polarity quantization phase detection module QPD_Nn of the nth level is connected to the external sampling clock port CLK, the input terminal is connected to the external nth bit data input port DATA[n], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_Pn, and the other input terminal is connected to the output of QPD_Nn, and the output of the AND gate is the corresponding nth level phase domain quantization residual Tq[n].

[0014] A phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator. The working steps of the circuit are briefly described as follows.

[0015] Step 1: When the rising edge of the external sampling clock port CLK arrives, the phase domain quantization residual detection circuit starts working. If the quantization residual occurs at the rising edge of the external data input port DATA next, the positive polarity quantization phase detection module QPD_P starts to output a high level after detecting the rising edge of CLK. When the rising edge of DATA appears, the NAND gate in the module is reset, and the output begins to convert to a low level until the end of the entire clock cycle, during which QPD_N always maintains an output high level; if the quantization residual occurs at the falling edge of the external data input port DATA next, the negative polarity quantization phase detection module QPD_N starts to output a high level after detecting the rising edge of CLK. When the falling edge of DATA appears, the NAND gate in the module is reset, and the output begins to convert to a low level until the end of the entire clock cycle, during which QPD_P always maintains an output high level.

[0016] Step 2: In step 1, the positive and negative polarity quantization phase detection modules have obtained corresponding output square waves for different edge conditions. The phase domain quantization residual detection circuit of each level can obtain the final phase domain quantization residual output by performing a logical AND operation on the outputs of the positive and negative polarity quantization phase detection modules of that level. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a structural diagram of the positive and negative polarity quantized phase detection circuit proposed by the present invention.

[0018] Figure 2 This is a structural diagram of the phase domain quantization residual detection circuit proposed by the present invention.

[0019] Figure 3 This is an exemplary circuit structure diagram of a phase domain quantization residual detection circuit proposed in the present invention for use in a continuous-time Sigma-Delta modulator based on a voltage-controlled oscillator. DETAILED DESCRIPTION

[0020] In order to make the purpose and technical advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of application of the present invention.

[0021] like Figure 1 The figure shows the structure of the positive and negative polarity quantized phase detection circuit proposed by the present invention, including rising edge and falling edge D flip-flops for obtaining input signals with different edges; and a two-input NAND gate for resetting the detection circuit.

[0022] Among them, the input terminal of the rising edge trigger DFF1 of the positive polarity quantization phase detection circuit is connected to a fixed high level, the clock terminal is connected to the input port DATA, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; the input terminal of the rising edge trigger DFF2 is connected to a fixed high level, the clock terminal is connected to the input port CLK, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; one of the input terminals of the two-input NAND gate is connected to the output of DFF1, the other input terminal is connected to the output of DFF2, and the output terminal is connected to the reset of DFF1 and DFF2.

[0023] The input terminal of the falling edge trigger DFF3 of the negative polarity quantization phase detection circuit is connected to a fixed high level, the clock terminal is connected to the input port DATA, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; the input terminal of the rising edge trigger DFF4 is connected to a fixed high level, the clock terminal is connected to the input port CLK, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; one of the inputs of the two-input NAND gate is connected to the output of DFF3, the other input terminal is connected to the output of DFF4, and the output terminal is connected to the reset of DFF3 and DFF4.

[0024] like Figure 2 The figure shows the structure diagram of the phase domain quantization residual detection circuit proposed by the present invention, a phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator, including positive and negative polarity quantization phase detection circuits for obtaining the phase difference between the sampling clock and different edge signals; a two-input AND gate for obtaining the quantization residual in the phase domain of the input signal.

[0025] Among them, the clock terminal of the positive polarity quantization phase detection module QPD_P1 of the first stage of the phase domain quantization residual detection circuit is connected to the external sampling clock port CLK, the input terminal is connected to the external first data input port DATA[1], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the negative polarity quantization phase detection module QPD_N1 of the first stage is connected to the external sampling clock port CLK, the input terminal is connected to the external first data input port DATA[1], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_P1, and the other input terminal is connected to the output of QPD_N1, and the output of the AND gate is the corresponding first-stage phase domain quantization residual Tq[1].

[0026] The clock terminal of the second-stage positive polarity quantization phase detection module QPD_P2 of the phase domain quantization residual detection circuit is connected to the external sampling clock port CLK, the input terminal is connected to the external second-bit data input port DATA[2], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the second-stage negative polarity quantization phase detection module QPD_N2 is connected to the external sampling clock port CLK, the input terminal is connected to the external second-bit data input port DATA[2], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_P2, and the other input terminal is connected to the output of QPD_N2, and the output of the AND gate is the corresponding second-stage phase domain quantization residual Tq[2].

[0027] By analogy, the clock terminal of the positive polarity quantization phase detection module QPD_Pn of the phase domain quantization residual detection circuit at the nth level is connected to the external sampling clock port CLK, the input terminal is connected to the external nth bit data input port DATA[n], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the negative polarity quantization phase detection module QPD_Nn of the nth level is connected to the external sampling clock port CLK, the input terminal is connected to the external nth bit data input port DATA[n], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_Pn, and the other input terminal is connected to the output of QPD_Nn, and the output of the AND gate is the corresponding nth level phase domain quantization residual Tq[n].

[0028] The circuit compares the sampling clock CLK with the input data DATA to obtain the phase domain quantization residual after sampling.

[0029] When the rising edge of the external sampling clock port CLK arrives, the phase domain quantization residual detection circuit starts working. If the quantization residual occurs at the rising edge of the external data input port DATA next, the positive polarity quantization phase detection module QPD_P starts to output a high level after detecting the rising edge of CLK. When the rising edge of DATA appears, the NAND gate in the module is reset, and the output begins to convert to a low level until the end of the entire clock cycle, during which QPD_N always maintains an output high level; if the quantization residual occurs at the falling edge of the external data input port DATA next, the negative polarity quantization phase detection module QPD_N starts to output a high level after detecting the rising edge of CLK. When the falling edge of DATA appears, the NAND gate in the module is reset, and the output begins to convert to a low level until the end of the entire clock cycle, during which QPD_P always maintains an output high level.

[0030] The positive and negative polarity quantization phase detection modules are used to obtain corresponding output square waves for different edge conditions. The phase domain quantization residual detection circuit of each level performs a logical AND operation on the outputs of the positive and negative polarity quantization phase detection modules of that level to obtain the final phase domain quantization residual output.

[0031] like Figure 3 The figure shows an example of the present invention being applied to a continuous-time Sigma-Delta modulator based on a voltage-controlled oscillator.

[0032] After the input signal Vin is quantized in the phase domain by the first-stage VCO1, each stage output of VCO1 is sampled by the clock CLK, and the obtained output signal is used as the input of the phase domain quantization residual detection circuit. Through the phase domain quantization residual detection circuit proposed in the present invention, the phase domain quantization residual φq1 generated by the quantization of VCO1 can be extracted, and then output as a square wave with different duty cycles in the time domain. Then, through the subsequent selection module PTR, the corresponding required residual signal is used as the input of the second-stage VCO2, thereby realizing the MASH structure of the continuous-time Sigma-Delta modulator based on the voltage-controlled oscillator.

Claims

1. A phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator, characterized in that: include: Rising edge and falling edge D flip-flops are used to obtain input signals with different edges; A two-input NAND gate for resetting the detection circuit; A quantized phase detection circuit with positive and negative polarities is used to obtain the phase difference between the sampling clock and different edge signals; A two-input AND gate is used to obtain the quantized residual of the input signal in the phase domain; Wherein, the input terminal of the rising edge trigger DFF1 of the positive polarity quantization phase detection circuit is connected to a fixed high level, the clock terminal is connected to the input port DATA, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; the input terminal of the rising edge trigger DFF2 is connected to a fixed high level, the clock terminal is connected to the input port CLK, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; one of the input terminals of the two-input NAND gate is connected to the output of DFF1, the other input terminal is connected to the output of DFF2, and the output terminal is connected to the reset of DFF1 and DFF2; The input terminal of the falling edge trigger DFF3 of the negative polarity quantization phase detection circuit is connected to a fixed high level, the clock terminal is connected to the input port DATA, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; the input terminal of the rising edge trigger DFF4 is connected to a fixed high level, the clock terminal is connected to the input port CLK, the reset terminal is connected to the output of the two-input NAND gate, and the output terminal is connected to one of the inputs of the two-input NAND gate; one of the inputs of the two-input NAND gate is connected to the output of DFF3, the other input terminal is connected to the output of DFF4, and the output terminal is connected to the reset of DFF3 and DFF4; The clock terminal of the positive polarity quantization phase detection module QPD_P1 of the first stage of the phase domain quantization residual detection circuit is connected to the external sampling clock port CLK, the input terminal is connected to the external first data input port DATA[1], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the negative polarity quantization phase detection module QPD_N1 of the first stage is connected to the external sampling clock port CLK, the input terminal is connected to the external first data input port DATA[1], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_P1, and the other input terminal is connected to the output of QPD_N1, and the output of the AND gate is the corresponding first-stage phase domain quantization residual Tq[1]; The clock terminal of the second-stage positive polarity quantization phase detection module QPD_P2 of the phase domain quantization residual detection circuit is connected to the external sampling clock port CLK, the input terminal is connected to the external second-bit data input port DATA[2], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the second-stage negative polarity quantization phase detection module QPD_N2 is connected to the external sampling clock port CLK, the input terminal is connected to the external second-bit data input port DATA[2], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_P2, and the other input terminal is connected to the output of QPD_N2, and the output of the AND gate is the corresponding second-stage phase domain quantization residual Tq[2]; By analogy, the clock terminal of the positive polarity quantization phase detection module QPD_Pn of the phase domain quantization residual detection circuit at the nth level is connected to the external sampling clock port CLK, the input terminal is connected to the external nth bit data input port DATA[n], and the output terminal is connected to one of the inputs of the two-input AND gate; the clock terminal of the negative polarity quantization phase detection module QPD_Nn of the nth level is connected to the external sampling clock port CLK, the input terminal is connected to the external nth bit data input port DATA[n], and the output terminal is connected to the other input of the two-input AND gate; one of the input terminals of the two-input AND gate is connected to the output of QPD_Pn, and the other input terminal is connected to the output of QPD_Nn, and the output of the AND gate is the corresponding nth level phase domain quantization residual Tq[n].

2. The phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator according to claim 1, characterized in that: When the rising edge of the external sampling clock port CLK arrives, the phase domain quantization residual detection circuit starts working. If the quantization residual occurs at the rising edge of the external data input port DATA next, the positive polarity quantization phase detection module QPD_P starts to output a high level after detecting the rising edge of CLK. When the rising edge of DATA appears, the NAND gate in the module is reset, and the output begins to convert to a low level until the end of the entire clock cycle, during which QPD_N always maintains an output high level; if the quantization residual occurs at the falling edge of the external data input port DATA next, the negative polarity quantization phase detection module QPD_N starts to output a high level after detecting the rising edge of CLK. When the falling edge of DATA appears, the NAND gate in the module is reset, and the output begins to convert to a low level until the end of the entire clock cycle, during which QPD_P always maintains an output high level.

3. The phase domain quantization residual detection module for a continuous-time Sigma-Delta modulator according to claim 1, characterized in that: The positive and negative polarity quantization phase detection modules are used to obtain the corresponding output square waves for different edge conditions. The phase domain quantization residual detection circuit of each level then performs a logical AND operation on the outputs of the positive and negative polarity quantization phase detection modules of that level to obtain the final phase domain quantization residual output.

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