A long-delay channel simulation method based on hardware resource constraints

Abstract

This invention discloses a long-delay channel simulation method under hardware resource constraints. The channel simulation method includes a signal input / output module, a decimation filter module, a delay simulation module, and an interpolation filter module. The input signal of the signal input / output module is processed by the decimation filter module, the delay simulation module, and the interpolation filter module before outputting the signal. The decimation filter module is used to filter and fractionally sample the signal. The delay simulation module is used to simulate large delays. The interpolation filter module is used to fractionally interpolate the delayed signal. This invention's long-delay channel simulation method uses a decimation filter to decimate the input signal, uses the decimated output signal as the input to the delay system for large-delay simulation, and then inputs the delayed signal into an interpolation filter to improve its accuracy before outputting the signal. This ensures the accuracy of the delayed signal while reducing the complexity of the delay system.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, specifically a long-delay channel simulation method based on hardware resource constraints. Background Technology

[0002] With the continuous development of technology and the enrichment of application scenarios, the number of channels and multipath propagation in channels has increased significantly, requiring more space to store data such as channel coefficients and input signals. However, the resources of channel simulators are limited. Therefore, it is necessary to improve the resource utilization rate within the channel simulator while ensuring performance requirements are met.

[0003] Common methods for simulating long-delay channels include the counter method and the register method. The counter method is implemented using basic combinational and sequential logic units, offering the advantage of simple implementation. However, supporting channels with large dynamic ranges requires multiple counters, significantly increasing control and implementation complexity. The register method primarily utilizes the RAM and DDR memory within the FPGA. RAM resources are limited, making it difficult to implement long delays. Therefore, using DDR for long delays and RAM for coarse delays slightly shorter than long delays has become the main method for implementing integer delays. However, as channels become increasingly complex and diverse, DDR needs to store more channel coefficients, and the required simulation delay length has increased. Therefore, improving utilization to achieve long delays is a critical task. Thus, this paper proposes a long-delay channel simulation method based on hardware resource constraints to address these issues. Summary of the Invention

[0004] The purpose of this invention is to provide a long-delay channel simulation method based on hardware resource constraints. First, the input signal is decimated using a decimation filter, and the decimated output signal is used as the input of a time-delay system to simulate a large time delay. Then, the delayed signal is input into an interpolation filter to improve its signal accuracy, and then the signal is output. This method achieves high-precision long-delay channel simulation by using a Farrow arbitrary sampling filter. This method can reduce resource consumption while ensuring signal accuracy.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A long-delay channel simulation method based on hardware resource constraints is disclosed. The channel simulation method includes a signal input / output module, a decimation filter module, a delay simulation module, and an interpolation filter module. The input signal of the signal input / output module is processed by the decimation filter module, the delay simulation module, and the interpolation filter module before being output. The decimation filter module is used to filter and fractionally sample the signal. The delay simulation module is used to simulate long delays. The interpolation filter module is used to fractionally interpolate the delayed signal.

[0007] Furthermore, the channel simulation method specifically includes the following steps:

[0008] Step 1: Process and output the signal through the signal input / output module.

[0009] Step 2: Filter the signal and perform fractional sampling using the decimation filter module.

[0010] Step 3: Delay the signal extracted in Step 2.

[0011] Step 4: Recover and improve the accuracy of the signal delayed in Step 3 by using a Farrow fractional interpolation filter.

[0012] Furthermore, the signal input / output module outputs a data sequence x(k) after the signal requiring time delay is passed through the ADC, inputs the x(k) sequence to the input side of the decimation filter module, and outputs the signal after passing through the decimation filter module, the time delay simulation module, and the interpolation filter module.

[0013] Furthermore, the decimation filter module includes an integer decimation and a Farrow resampling filter, which decimates the digital sequence x(k) by integer multiples to obtain x(k). m ), and then x(k m The signal is input to a Farrow filter for filtering and fractional sampling, at which point the sampling rate of the signal is T. o1 The aim is to reduce the amount of data by lowering the sampling rate in order to improve the utilization of hardware resources.

[0014] Furthermore, the time delay simulation module mainly performs long time delay simulation. The signal after appropriate decimation is input into the time delay simulation module. The long time delay method uses a dual-port RAM. The principle of dual-port RAM is to use a high-speed clock to sample the input pulse and store the sampling result in a FIFO. At the same time, the output of the FIFO is controlled by the delay control module to generate the required pulse.

[0015] Furthermore, the interpolation filter module includes a Farrow fractional interpolation filter, which is used to improve the accuracy of the signal. Interpolation is performed by using a Farrow structure low-pass filter. Since the Farrow structure is suitable for situations where the interpolation factor is dynamic, the time-delayed signal is interpolated by integer and then input into the Farrow filter for fractional interpolation.

[0016] Furthermore, the principle of arbitrary multiple resampling is as follows:

[0017] Let the frequency of the input signal be f. s1 The sampling time interval is Tin The frequency of the output signal is f s2 The sampling time interval is T out If we want to find the sample output value y(n0T) after sampling rate conversion at a certain time point (n=n0), out ), let n0T out =(m0+u0)T in Where m0 is a positive integer, representing the relationship between n0T and n0T. out The discrete time point of the nearest input sample to the output sample at time t. u0∈[0,1), represents the normalized fractional interval between the two samples. Let r=f s1 / f s2 Let represent the reciprocal of the sampling rate conversion factor, then:

[0018] m0 = [n0 * r]

[0019] u0=(n0*r)-m0

[0020] The sampling rate conversion algorithm is used to calculate the impulse response h(t) of the delayed low-pass filter, as well as the parameters m0 and u0.

[0021] When the value of r is less than 1, the range of u0 is [0, 1), and h(t)| t = (k+u0)Tin The coefficient value is calculated to obtain y(n0T) out ).

[0022] The sampling principle of the channel simulation method utilizes polynomial approximation to fit h(kT) in ) and h((k+1)T in The interpolation between the two values ​​is obtained using the following formula:

[0023]

[0024] Where j = 0, 1, ..., M represents the j-th order of the polynomial, and h0(k) ~ h j (k) represents the coefficient of the polynomial, and the coefficient value at any position is h((k+u0)T). in y(nT) can be directly calculated from the parameter u0 and the polynomial coefficients, and can be calculated using the following formula. out ):

[0025]

[0026] The above equation is the Farrow filter structure, which can be expressed in h. j If (k) remains unchanged, interpolation can be completed by changing only the parameter u.

[0027] The channel simulation method uses Lagrange interpolation to calculate the coefficients, and the filter coefficients are calculated using an improved method of the Lagrange interpolation algorithm. Given Y(z) = H(z)X(z), from:

[0028] Y(z)=z -u X(z) and

[0029] Conclusion:

[0030]

[0031] It can be represented as:

[0032] Vc = z

[0033] Where V is an M+1*M+1 Vandermonde matrix.

[0034]

[0035] c = [C0(z),C1(z),...,C M (z)] T z = [1, z -1 ,z -2 ,...,z -M ]

[0036] Find the filter coefficients:

[0037] c = V -1 z

[0038] The above describes the method for calculating the filter function using the Lagrange interpolation algorithm. The improved steps include: assuming...

[0039]

[0040] C(z)=TV -1 z

[0041] C(z) represents the coefficients of the Farrow structure filter.

[0042] Furthermore, the delay control module performs the following control:

[0043] When the data time length written to the FIFO is equal to the delay value, the FIFO read signal is started until the data in the FIFO is read out. The output of the FIFO is the delayed pulse.

[0044] Two FIFOs are used to delay the input pulse in turn, so as to achieve pulse delay control with continuously variable delay value.

[0045] When the delay value is updated, the FIFO is switched, and the outputs of the two FIFOs are ORed together to form the final output pulse. By strictly designing the timing of the "input switching control" module, seamless connection between the two FIFOs is achieved, completing the delay control of the input pulse.

[0046] Furthermore, the depth of the RAM determines the length of the stored signal, which is the duration of the delay:

[0047]

[0048] Where ΔT is the minimum sampling interval, the required simulated delay D is the signal length N that needs to be stored for the duration D, and therefore the depth of RAM determines the length of the stored signal, which is the duration that can be delayed.

[0049] The beneficial effects of this invention are:

[0050] 1. The long-delay channel simulation method of the present invention reduces resource consumption by extracting the input digital signal and then delaying it, so as to complete the simulation of a long-delay channel (greater than 10ms) under the premise of limited hardware resources;

[0051] 2. The long-delay channel simulation method of the present invention ensures the accuracy of the signal after the delay by extracting the input signal and then inserting it.

[0052] 3. The long-delay channel simulation method of this invention utilizes the high precision of the Farrow structure resampling filter to reduce the complexity of the delay system while ensuring that the data is not distorted;

[0053] 4. Due to the special nature of the Farrow structure in the long-delay channel simulation method of the present invention, the fractional delay changes will not affect its Farrow filter coefficients. Therefore, the present invention can complete a dynamic delay channel with delay varying with time. Attached Figure Description

[0054] The invention will now be further described with reference to the accompanying drawings.

[0055] Figure 1 This is a system flowchart of the long-delay channel simulation method of the present invention;

[0056] Figure 2 This invention provides a diagram showing the corresponding sampling points before and after sampling rate conversion.

[0057] Figure 3 This is a structural diagram of the Farrow filter of the present invention;

[0058] Figure 4 This is the amplitude response of the Farrow filter of this invention;

[0059] Figure 5This is the phase response of the Farrow filter of this invention;

[0060] Figure 6 This is an FPGA structure diagram of the third-order Farrow filter of this invention;

[0061] Figure 7 This is a simulation result diagram of the long-delay channel of the FPGA of the present invention (po_data1 is the original input data sequence, out1 is the result after data extraction and passing through the Farrow filter, and out2 is the result after data interpolation and passing through the Farrow filter for accuracy restoration). Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] A long-delay channel simulation method based on hardware resource constraints is proposed. The channel simulation method includes a signal input / output module, a decimation filter module, a delay simulation module, and an interpolation filter module, such as... Figure 1 As shown, the input signal of the signal input / output module is output after passing through the decimation filter module, the time delay simulation module, and the interpolation filter module. The decimation filter module is used to filter and fractionally sample the signal, the time delay simulation module is used to simulate large time delays, and the interpolation filter module is used to perform fractional interpolation on the delayed signal.

[0064] The channel simulation method specifically includes the following steps:

[0065] Step 1: Process and output the signal through the signal input / output module.

[0066] The signal input / output module outputs a data sequence x(k) after the signal requiring time delay is passed through the ADC. The x(k) sequence is then input to the input side of the decimation filter module. The input signal is then passed through the decimation filter module, the time delay simulation module, and the interpolation filter module before being output.

[0067] Step 2: Filter the signal and perform fractional sampling using the decimation filter module.

[0068] The decimation filter module includes integer decimation and Farrow resampling filters, while the interpolation filter module mainly consists of integer interpolation and Farrow fractional interpolation filters, which decimate the digital sequence x(k) by integer multiples to obtain x(k). m ), and then x(km The signal is input to a Farrow filter for filtering and fractional sampling, at which point the sampling rate of the signal is T. o1 The aim is to reduce the amount of data by lowering the sampling rate in order to improve the utilization of hardware resources.

[0069] The principle of arbitrary multiple resampling is as follows: Let the frequency of the input signal be f. s1 The sampling time interval is T in The frequency of the output signal is f s2 The sampling time interval is T out If we want to find the sample output value y(n0T) after sampling rate conversion at a certain time point (n=n0), out ), let n0T out =(m0+u0)T in Where m0 is a positive integer, representing the relationship between n0T and n0T. out The discrete time point of the nearest input sample to the output sample at time t; u0∈[0,1), representing the normalized fractional interval between the two samples, such as Figure 2 As shown, Figure 2 To show the corresponding sampling points before and after the sampling rate conversion, let r = f s1 / f s2 Let represent the reciprocal of the sampling rate conversion factor, then:

[0070] m0 = [n0 * r]

[0071] u0=(n0*r)-m0

[0072] The sampling rate conversion algorithm is used to calculate the impulse response h(t) of the delayed low-pass filter, as well as the parameters m0 and u0.

[0073] When the value of r is less than 1, the range of u0 is [0, 1), and h(t)| t＝(k+u0)Tin The coefficient value is calculated to obtain y(n0T) out ), in h(kT in ) and h((k+1)T in Interpolation between (k+u0)T yields the coefficient h((k+u0)T) in It is difficult to complete this task. The smaller the value of u0, the more interpolation points are required. When u0 is infinitely small, the interpolation factor is infinite. If a finite interpolation factor is used for interpolation, it is difficult to guarantee its accuracy. If the interpolation factor is increased, the amount of hardware consumed increases, resulting in resource waste. Therefore, the sampling principle of the channel simulation method uses a polynomial to approximate h(kT) in ) and h((k+1)T in The interpolation between the two values ​​is obtained using the following formula:

[0074]

[0075] Where j = 0, 1, ..., M represents the j-th order of the polynomial, and h0(k) ~ h j (k) represents the coefficient of the polynomial, and the coefficient value at any position is h((k+u0)T). in y(nT) can be directly calculated from the parameter u0 and the polynomial coefficients, and can be calculated using the following formula. out ):

[0076]

[0077] The above equation is the Farrow filter structure, which can be applied to h. j (k) If the parameter u is changed while keeping it constant, interpolation can be completed. Since this meets the requirement that the channel delay is dynamically changing, it is easier to change the interpolation factor than other filters. Therefore, this filter is chosen as the interpolation filter. The Farrow structure is as follows: Figure 3 As shown.

[0078] The channel simulation method uses Lagrange interpolation to calculate the coefficients. Lagrange interpolation involves constructing a function whose derivative with the transfer function of the ideal sinc filter is equal to 0 at ω = ω0, where ω0 = 0.

[0079] Since the Lagrange interpolation filter is simpler to implement and more accurate than the window function method, the filter coefficients are calculated using an improved method of the Lagrange interpolation algorithm. Given Y(z) = H(z)X(z), the coefficients are calculated using:

[0080] Y(z)=z -u X(z) and

[0081] Conclusion:

[0082]

[0083] It can be represented as:

[0084] Vc = z

[0085] Where V is an M+1*M+1 Vandermonde matrix.

[0086]

[0087] c = [C0(z),C1(z),...,C M (z)] T z = [1, z -1 ,z -2 ,...,z -M ]

[0088] Find the filter coefficients:

[0089] c = V -1 z

[0090] The above describes the method for calculating the filter function using the Lagrange interpolation algorithm. The improved steps include: assuming...

[0091]

[0092] C(z)=TV -1 z

[0093] C(z) represents the coefficients of the Farrow structure filter, such as Figure 4 As shown, the amplitude-frequency curve of the filter reveals that it is approximately flat (similar to an ideal sinc filter) when the frequency approaches 0, indicating high accuracy and a wider bandwidth with higher order. Figure 5 The phase-frequency curves shown demonstrate that the higher the order, the more pronounced the linear phase and the less distortion.

[0094] like Figure 6 As shown, each FIR is a 4th-order filter. The 4th-order filter processes the output signal. A 3rd-order Farrow filter consists of four 4th-order sub-filters, i.e., M = N = 4, as shown by the Farrow filter formula:

[0095]

[0096] Horner's Law:

[0097]

[0098] The transfer function of the third-order Farrow filter can be obtained as follows:

[0099] H(z)=C0+μ(C1+μ(C2+μC3))

[0100] The above formula represents the structural principle of a 3rd-order Farrow filter FPGA.

[0101] Step 3: Delay the signal extracted in Step 2.

[0102] The time delay simulation module is mainly used for long time delay simulation. The signal after being decimated by an appropriate factor is input into the time delay simulation module. The long time delay method uses a dual-port RAM. The principle of dual-port RAM is to use a high-speed clock to sample the input pulse and store the sampling result in a FIFO. At the same time, the output of the FIFO is controlled by the delay control module to generate the required pulse.

[0103] The depth of the FIFO depends on the maximum delay. The delay control module performs the following control: when the data writing time to the FIFO equals the delay value, the FIFO read signal is initiated until the data in the FIFO is emptied. The output of the FIFO is the delayed pulse. To achieve pulse delay control with continuously variable delay values, two FIFOs should be used to delay the input pulse alternately. When the delay value is updated, the FIFO is switched, and the outputs of the two FIFOs are ORed together to obtain the final output pulse. By strictly designing the timing of the "input switching control" module, seamless connection between the two FIFOs can be achieved to complete the delay control of the input pulse.

[0104] The depth of RAM determines the length of the stored signal, which is the duration that can be delayed.

[0105]

[0106] Here, ΔT is the minimum sampling interval, and the required simulation delay D is the signal length N that needs to be stored for time D. Therefore, the depth of the RAM determines the length of the stored signal, which is the duration that can be delayed. The channel simulation method reduces the signal length by using a polyphase decimation filter, thereby achieving the goal of requiring less RAM space when performing delay simulation. Since this will reduce accuracy, a Farrow fractional interpolation filter is used to improve accuracy.

[0107] Step 4: Recover and improve the accuracy of the signal delayed in Step 3 by using a Farrow fractional interpolation filter.

[0108] like Figure 6 , Figure 7 As shown, the interpolation filter module includes a Farrow fractional interpolation filter. The Farrow fractional interpolation filter is used to improve the accuracy of the signal. It uses multipliers and adders to process the fractional interpolation signal and output the signal. Interpolation is performed by using a Farrow structure low-pass filter. Since the Farrow structure is suitable for cases where the interpolation multiple is dynamic, the signal after time delay is interpolated by integers and then input into the Farrow filter for fractional interpolation. The purpose is to restore the original or required data accuracy.

[0109] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0112] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0113] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for simulating a long-delay channel based on hardware resource constraints, the method comprising: The channel simulation method comprises a signal input / output module, an extraction filter module, a time delay simulation module and an interpolation filter module. The channel simulation method comprises the following steps: Step 1: processing and outputting signals through the signal input / output module; Step 2: filtering and fractional multiple sampling of the signals through the extraction filter module; The decimation filter module includes an integer decimation and a Farrow resampling filter, which decimates the digital sequence x(k) by an integer to obtain x(k m ), and then inputs x(k m ) into the Farrow filter for filtering and fractional sampling, at this time, the sampling rate of the signal is T o1 , and the purpose is to reduce the data amount by reducing the sampling rate to improve the utilization rate of hardware resources; Step 3: time delay of the signals extracted in step 2; Step 4: after the time-delayed signals in step 3 are subjected to integer interpolation, the signals are input into a Farrow filter for fractional interpolation to restore and improve precision.

2. The method of claim 1, wherein, The signal input / output module outputs data sequences x(k) after the signals requiring time delay are subjected to ADC, and inputs the x(k) sequences into the input side of the extraction filter module, and outputs the signals after the input signals are subjected to the extraction filter module, the time delay simulation module and the interpolation filter module.

3. The method of claim 1, wherein, The time delay simulation module mainly simulates long time delay, and inputs the signals subjected to appropriate multiple extraction into the time delay simulation module. The method for long time delay is to use a dual-port RAM. The principle of the dual-port RAM is to sample input pulses by using a high-speed clock, and store the sampling results in a FIFO. Meanwhile, the output of the FIFO is controlled by a delay control module to generate required pulses.

4. The method of claim 1, wherein, The interpolation filter module comprises a Farrow fractional multiple interpolation filter. The Farrow fractional multiple interpolation filter is used for improving the precision of signals, and interpolates by using the method of Farrow structure low-pass filter. Since the Farrow structure is suitable for the case that the interpolation multiple is dynamic, the time-delayed signals are subjected to integer interpolation and then input into the Farrow filter for fractional interpolation.

5. The method of claim 3, wherein the long time delay channel simulation is based on hardware resource constraints. The delay control module completes the following controls: When the time length of the data written into the FIFO is equal to the delay value, the FIFO reading signal is started until the data in the FIFO is read empty. The output of the FIFO is the delayed pulse. Two-way FIFO is used to delay the input pulse alternately to realize the continuous variable pulse delay control of the delay value. When the delay value is updated, the FIFO is switched, and the outputs of the two-way FIFO are in phase or after the switching as the final output pulse. By strictly designing the timing of the "input switching control" module, the two-way FIFO is seamlessly connected to complete the delay control of the input pulse.

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