An efficient and repeatable address allocation method for RS-485 bus based on bit competition mechanism

Abstract

The present invention discloses an efficient and repeatable RS-485 bus address allocation method based on a bit competition mechanism. The host in the present invention starts address allocation after sending a broadcast instruction, and the slave responds to the instruction and prepares to compete for the address according to the UUID bit, and after receiving the first U instruction, enters the bit competition mechanism judgment; each time a U instruction is responded to, the slave with a small UUID value stays to continue to compete for the address, and the large one exits, and finally only the one with the smallest UUID among all the slaves is left, thereby completing the allocation of the first address; subsequently, the second address is allocated according to the allocation method of the first place until all addresses are allocated. Compared with the existing automatic address allocation method, the millisecond-level address allocation speed of the present invention is significantly higher than the existing method, and there is no conflict in the bus in the address allocation method, which greatly increases the stability of the bus compared to the bus address allocation method with random time collision.

Description

Technical Field

[0001] The invention belongs to the technical field of communication, and in particular relates to an RS-485 bus address efficient and repeatable allocation method based on a bit competition mechanism. Background Art

[0002] RS-485 bus is a two-wire differential signal bus. In industrial sites, RS-485 bus has the advantages of good anti-interference (stable signal), simple wiring, low cost, etc. It is the most widely used serial bus standard. In particular, when there are many decentralized industrial network control units and the industrial equipment is far apart, the advantages of RS-485 bus are particularly prominent.

[0003] In actual applications, the RS-485 bus only specifies the electrical characteristics of the interface, but does not define the software protocol, so users can establish relevant software communication protocol standards according to their own needs. The most important first step in the connection and communication between various bus devices is that the host automatically assigns communication addresses to each slave through the RS-485 bus.

[0004] There are two main types of automatic address allocation methods in existing applications: 1) The random number generated by the slave is converted into a random delay time to achieve a delayed response to the host addressing, so that the host can allocate addresses to the slaves at random different time points. Although this method has a relatively high success rate in automatically allocating addresses, it is inefficient. It usually takes several minutes or even longer to complete the address allocation of the slave, and there are still bus conflicts. At the same time, the random time causes each slave address to have no repeatability guarantee. 2) The host automatically allocates addresses by introducing control cables outside the bus, adding additional controllers, or adding step-by-step control ports between slaves. This method is generally used in specific application scenarios, and the wiring is relatively complex, the scalability is poor, and there is an extra layer of topology, which is more complex, less robust, and more expensive.

[0005] There are many distributed nodes in industrial sites, but the wiring requirements are simple, especially in some places where the space is relatively cramped but the reliability requirements are high, such as dummies or flexible legs in automobile collision tests. There are multiple distributed nodes with sensor data collection requirements, and the nodes and host devices need to be simply connected. Summary of the invention

[0006] The invention aims at the deficiencies of the prior art and provides a method for efficiently and repeatedly allocating RS-485 bus addresses based on a bit competition mechanism.

[0007] The technical solution adopted by the present invention is:

[0008] The invention discloses an efficient and repeatable RS-485 bus address allocation method based on a bit competition mechanism, which is applicable to the communication between a host and a plurality of slaves, wherein the slaves include at least one memory module for storing a unique identification code; the method comprises the following steps:

[0009] Step 1: Synchronize the clocks between the host and the slave.

[0010] Step 2: The host sends a broadcast command to the slave to start the automatic allocation of the first address. All slaves are ready to compete for the address upon receiving the broadcast command.

[0011] Step 2.1, the host sends the first ASCII code U command. After sending the command, the host on the RS-485 bus is a high-impedance input. The host configures the TX line and RX line from the serial port as IO input. The host reads and records the bus status at 75T. This process continues until 150T. After that, the host changes to output, configures the TX line and RX line to the serial port mode, and sends the next ASCII code U command, where T represents the time base.

[0012] After receiving the ASCII code U command, the slave divides the 150T time interval into three equal segments. In the first 50T period, each slave determines whether the last bit of its own identification code is 1 or 0, and executes the bit competition mechanism based on the determination result.

[0013] Step 2.2: After the slave completes the response to the first ASCII code U command of the host, the host starts to send the second U command;

[0014] After receiving the second ASCII code U instruction, the slave selected to be retained by the bit competition mechanism begins to continue to judge whether the second to last bit of its own identification code is 1 or 0 in the first 50T time, and executes the bit competition mechanism again according to the judgment result.

[0015] Step 2.3, each time after sending the ASCII code U instruction, the slave's own identification code judgment bit moves forward by one bit until only one slave is left that has not withdrawn from the competition. At the end of this last comparison, the slave assigns itself an address of 1.

[0016] Step 3: The host sends the next broadcast command to the slave to start the automatic allocation of the second address. Except for the slave that has been allocated the address, other slaves with address 0 respond to the broadcast command to perform the second address allocation, and still perform multiple ASCII code U command processing to complete the automatic allocation of the second address.

[0017] Step 4: Repeat step 3 above until all addresses are automatically allocated.

[0018] The bit contention mechanism described in some embodiments is specifically:

[0019] If the slave determines that its own identification code is 0, the slave will configure the TX line as IO output 0 and the RX line as IO input before the second 50T time interval, and the RS-485 bus node of the slave will be output, so as to pull down the RS-485 bus until the second 50T ends; until the third 50T time starts, the RS-485 bus node of the slave will be changed to high-impedance input, and the slave will configure the TX line and RX line as serial port mode, waiting for the next host ASCII code U instruction, and will not exit the competition;

[0020] If the slave determines that its own identification code is 1, the slave configures the TX and RX lines of the slave's CPU as IO inputs before the second 50T time interval, the RS-485 bus node of the slave is a high-impedance input, and at 75T, reads the status of the RS-485 bus:

[0021] When the read RS-485 bus status is low, the slave exits the address competition. When exiting, the slave configures the TX line and RX line to serial port mode.

[0022] When the read RS-485 bus state is high, then at the beginning of the third 50T time, the slave configures the TX line and RX line to serial port mode.

[0023] Beneficial effects of the present invention:

[0024] 1. Compared with the existing automatic address allocation method (allocation time is tens of minutes), the millisecond-level address allocation speed of the present invention is significantly higher than the existing technology.

[0025] 2. In the address allocation method of the present invention, there is no conflict in the bus, which greatly increases the stability of the bus compared to the bus address allocation method of random time collision.

[0026] 3. If any one of the slaves in the present invention is damaged, it will not affect other RS-485 buses. Compared with the method of controlling the slaves by the slave (in this method, if only one slave is damaged, the subsequent slaves in series will not work), the present invention has better robustness.

[0027] 4. Compared with other control methods, such as allocating addresses by each slave bus, or adding other monitoring or control systems to automatically allocate addresses, the present invention has a wider range of usage scenarios, simpler wiring, and low cost, and truly achieves the characteristics of distributed point control.

[0028] 5. In the existing random time collision method, the random time number is different each time, which will cause the address of a single slave in the bus to be different each time. However, the address of the slave allocated by the present invention is highly repeatable each time. For example, if the address allocated this time is 1, then the address allocated next time will also be 1, ensuring the one-to-one feature of the host controlling the slave in distributed point control each time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is an application environment for RS-485 bus.

[0030] Figure 2 It is another application environment for RS-485 bus.

[0031] Figure 3 It is a schematic diagram of the configuration of the slave device in the present invention.

[0032] Figure 4 It is a schematic diagram of the configuration of the host in the present invention.

[0033] Figure 5 The figure is a flow chart of the method of the present invention.

[0034] Figure 6 Schematic diagram of clock pulse.

[0035] Figure 7 This is a schematic diagram of a short break after synchronization clock calibration.

[0036] Figure 8 Assign timing diagram to addresses. DETAILED DESCRIPTION

[0037] The application environment of this embodiment is as follows Figure 1 and Figure 2 shown. Figure 1 It represents that the host and multiple slaves communicate through the RS-485 bus, and two power lines are added to the RS-485 two-core bus, and the host supplies power to each slave. The advantages of this implementation are: no other redundant auxiliary equipment is required to assist the host to automatically assign addresses to slaves, and no additional power is required to power each slave. Only one 4-core line is needed to complete the power supply and communication between the host and each slave. A single slave node is powered and communicated by the host to complete the host command.

[0038] Figure 2 For another application environment, the host communicates with multiple slaves through the bus, assigns addresses and gives instructions. This scenario requires a single slave to be powered by itself (it can be connected to the power supply at the node).

[0039] The above two scenarios basically cover the application scenarios of all distributed nodes, and the wiring is simple without unnecessary auxiliary equipment.

[0040] Slave structure, such as Figure 3 As shown in the figure, the slave structure has 5 modules. The power module supplies power to the slave and can accept external power (power supply at the host or node); the CPU is generally an STM32G0 series microcontroller, and its speed can reach 64MHz after the internal crystal oscillator is configured. The CPU connects to the RS-485 module through the TX and RX signal lines (the TX and RX signal lines are configured by the CPU and can be configured as serial port, pulse capture and IO input and output modes respectively), and converts the TX and RX signals into bus differential signals through the RS-485 module to respond to bus host commands and address allocation. Each slave has a memory module, which is an EEPROM, which can store a universal unique identification code (UUID). Each device has a UUID. Other functional modules are the functions that each node needs to implement, such as collecting sensor data.

[0041] In some embodiments, the UUID of each slave device is N bytes, a total of 8*N bits. It can be assumed that all different devices can have a total of 2 8*N In this example, N is 10. It can be assumed that the UUID of each device is different.

[0042] like Figure 4 As shown, in this embodiment, the host is an FPGA module, and the FPGA has a fast speed. The FPGA is connected to the RS-485 module through two signal lines, TX and RX (the two signal lines, TX and RX, can be configured as three modes, namely serial port, PWM mode and IO input and output, through the FPGA configuration mode). The host gives instructions to the slave and assigns addresses through the RS-485 bus.

[0043] According to the host and slave structure given in the above embodiment, after the host and multiple slaves (n slaves) are connected, all are powered on and stabilized, the address automatic allocation process is as follows:

[0044] Before this process, a time base (referred to as time base) is agreed upon first. The time required for each process is the time base T*coefficient. For example, if the time base is 1us, the address of each slave when it is powered on is 0. After powering on, the RS-485 bus node of the host is output, and the RS-485 bus node of the slave is high-impedance input.

[0045] 1. Synchronous clock (the slave is calibrated according to the synchronous clock)

[0046] During this process, the TX line between the PFGA and the RS-485 module of the host is configured as PWM output mode, and the RX line is set as IO input. The RX line between the internal CPU and the RS-485 module of the slave is configured as pulse capture mode, and the TX line is set as IO input.

[0047] The host sends N clock pulses, where N is a large enough number to ensure that each slave measures the relationship between the known time and the slave's own timer count time through pulse capture, and performs step calibration (STM32G0 can calibrate its own internal RC oscillator (HSI) based on pulse capture): At this time, the slave's CPU configures the TX line and RX line to pulse capture mode, and the host FPGA configures the TX line and RX line to PWM mode first.

[0048] If N is 500, the host sends 500 clock pulses, and each slave captures the pulse through the timer, calculates the pulse period and duty cycle calibration, compares it with the known agreed pulse, and performs step calibration 500 times. After the calibration is completed, the host and slave clocks are sufficiently synchronized, and the error is small enough relative to the time base. This step is a key step. Only when the error between the host and slave clocks is small enough can each step of the subsequent automatic address allocation be synchronized and will not be confused due to time errors. Figure 6 The clock pulse is shown. Each clock pulse cycle is 5T high levels and 45T low levels, that is, one clock pulse cycle is 50T (the period and duty cycle of the calibration pulse are adjusted according to the time base, and the accuracy of the time base level is guaranteed between FPGA and CPU).

[0049] 2. The host briefly stops

[0050] like Figure 7 As shown, after the synchronous clock calibration is completed, the TX line and RX line between the PFGA and the RS-485 module are configured in serial port mode (the serial port speed mentioned later is 1.152M), and the host keeps the pause time at 1000T. During this time, the slave calibrates the internal clock crystal according to the synchronous clock, and the TX line and RX line between the slave's internal CPU and the RS-485 module are configured in serial port mode. After the 1000T time is over, the host starts the automatic address allocation process.

[0051] 3. Logical address allocation

[0052] At the beginning, the addresses of all slaves are 0 (the TX and RX lines between the CPU and the RS-485 module have been configured in serial mode in the previous step). All slaves in address 0 mode will respond to this command (XXID0 and U) (these two commands are sent through the FPGA configuration TX and RX lines to serial mode, and the TX and RX lines of the slave CPU are also serial), and they will begin to compete through the bit comparison of UUID to obtain the address sent by the host. Each slave has a unique UUID, which consists of 10 bytes of data, a total of 80 bits. Therefore, 80 steps (80 bit comparisons) are required for one address allocation.

[0053] 3.1 After the pause, the host sends a broadcast command to the slave: XXID0 (the host TX line and RX line are serial ports)

[0054] Among them: the construction of the instruction "XXID0" is an ASCII string construction, and its specific meaning is as follows:

[0055] Broadcast instruction XXID0, XX = logical address from 1 to XX, then the number of logical addresses can be up to 254, XX is the plain text of ASCII code, up to FF (but the last address is not used, so it is 254 addresses. Since the RS-485 bus can carry up to 128 devices at the hardware layer in a strict sense, the logical address here is enough); ID is used as the label of the ID command, and 0 is used as the broadcast address;

[0056] All slaves will not respond when receiving the broadcast command, but will prepare to compete for the address by UUID bit (the slave TX and RX lines are serial ports).

[0057] 3.2 The host waits for 200T to give all slaves enough time to wait for commands and prepare to start competing for addresses according to the UUID bit.

[0058] 3.3 Host: Send the first ASCII code "U" command. After sending the command, the RS-485 bus node of the host is high-impedance input, and the FPGA configures the TX line and RX line from the serial port as IO input. The bus level status can be read in each U interval. The host reads and records the bus status at 75T. This high-impedance input process lasts for 150T, and then the RS-485 bus node of the host is changed to output. The FPGA configures the TX line and RX line to serial port mode, and proceeds to send the next ASCII code "U" command.

[0059] Slaves in 0-address mode: After receiving the U command, (the RS-485 bus node of the slave is high-impedance input or output, and the CPU configures the TX and RX lines from the serial port as IO input or output, depending on the UUID of each slave), the 150T time interval is evenly divided into three sections. In the first 50T period, each slave determines whether the 80th bit (binary number) of its own UUID is 1 or 0, and enters the bit competition mechanism:

[0060] A. If this bit is 0, the slave CPU configures TX as IO output 0 and RX as IO input before the second 50T time interval, and the RS-485 bus node of the slave is output, so as to pull down the RS-485 bus (multiple nodes output low level at the same time, there is no pure conflict in the circuit, and the bus is still low level). At the end of the second 50T and until the third 50T time begins, the bus RS-485 node of the slave is changed to high-impedance input, and the CPU configures the TX line and RX line as serial port, waiting for the next host ASCII code U instruction, and does not exit the competition;

[0061] B. If this bit is 1, the slave configures the TX and RX lines of the CPU as IO inputs before the second 50T time interval, and the RS-485 bus node of the slave is a high-impedance input. At 75T, the status of the RS-485 bus is read. If the bus status read at this time is low, it means that the UUID of this bit of other slaves is 0, which is smaller than the UUID of this slave. This slave exits the competition for this address (address 1) (80 times U). The slave is still in 0 address mode and waits for the next XXID0 cycle (before exiting, the slave CPU configures the TX and RX lines to the serial port mode and waits for the serial port instruction XXID0). If the bus status read is high (high impedance), it means that the UUID of this bit of all slaves is 1. Then at the beginning of the third 50T time, the slave CPU configures the TX and RX lines to the serial port mode. After this "U" ends, it continues to wait for the next host U command and starts the next bit comparison of all slaves. (It is equivalent to comparing the UUIDs of all slaves. The slave with the smaller UUID will have priority in competing for the address).

[0062] 3.5 After completing the host's first U response, that is, 150T after the host sends the first U, the FPGA configures the TX line and RX line to serial port mode to send the second U, and repeats the process within the 150T time interval after sending U.

[0063] After receiving the second U instruction, the slaves that have exited the address competition in the first U (01ID0) no longer determine whether the 79th bit of the UUID is 0 or 1. Only the slaves that have just stayed will continue to determine whether the 79th bit (binary number) of their own UUID is 1 or 0 in the first 50T period, and continue to execute the bit competition mechanism:

[0064] A. If this bit is 0, the CPU of the slave configures TX as IO output 0 and RX as IO input before the second 50T time interval, and the RS-485 bus node of the slave is output, so as to pull down the RS-485 bus. When the second 50T ends and the third 50T begins, the bus RS-485 node of the slave is changed to high-impedance input, and the CPU configures TX and RX lines as serial port mode, waiting for the next host ASCII code U instruction, and does not exit the competition;

[0065] B. If this bit is 1, the slave configures the TX and RX lines of the CPU as IO inputs before the second 50T time interval, and the RS-485 bus node of the slave is a high-impedance input. At 75T, the RS-485 bus status is read. If the bus status read is low at this time, it means that the UUID of this bit of other slaves is 0, which is smaller than the UUID of this slave. This slave exits the competition for this address (address 1) (80 times U). The slave is still in 0 address mode and waits for the next XXID0 cycle (before exiting, the slave CPU configures the TX and RX lines as serial port mode and waits for the serial port instruction XXID0). If the bus status read is high (high impedance), it means that the UUID of this bit of all slaves is 1. Then at the beginning of the third 50T time, the slave (CPU configures the TX and RX lines as serial port) will be removed, and after this "U" ends, it will continue to wait for the next host U command and start the next bit comparison of all slaves. (It is equivalent to comparing the UUIDs of all slaves. The slave with the smaller UUID will have priority in competing for the address).

[0066] 3.6 Repeatedly, in this embodiment, the U command sent by the host is performed 80 times in total.

[0067] This is equivalent to each slave comparing its own UUID digits once each time (the first time is the 80th digit, the second time is the 79th digit...). In this case, there are only two situations:

[0068] A. All slaves have this bit set to 0 or 1, and all remain to compete for the next bit.

[0069] B. Some slaves have this bit set to 0, while other slaves have this bit set to 1 to exit the address competition

[0070] According to the concept of this embodiment, the slave with a smaller UUID value will continue to compete for the address, and the slave with a larger UUID will exit. Finally, by the 80th time, only the slave with the smallest UUID will remain.

[0071] For example, if UUID-A>UUID-B, then UUID-B will definitely have a higher bit position of 0 earlier than UUID-A. At this time, the bit of UUID-A is 1, so UUID-A exits the address competition and UUID-B enters the next bit comparison.

[0072] 3.7 Finally, at the end of the 80th comparison, there is only one slave left that has not withdrawn from the competition. Then at the end of the 80th comparison, the slave assigns itself an address of 1. The slave with address 1 no longer responds to the 0 address mode command of XXID0.

[0073] 3.8 After completing 80 "U" commands, the host pauses for 50T time to allow the slave that has just been assigned address 1 to end the 0 address mode.

[0074] 3.9 The host starts the next XXID0 command, 02ID0, to start the automatic allocation of the second address. Except for the slave that has been allocated an address, other slaves with address 0 respond to this command to allocate the address for the second time, and still issue 80 "U" commands to complete the allocation of the second address.

[0075] 3.10 If all slaves have completed address allocation, for example, there are 48 slaves in total, and the addresses are allocated to 1-48, then after the address allocation of 30ID0 is completed (hexadecimal 30 is address 48).

[0076] The host will send 31ID0 again. At this time, all slaves have been assigned addresses, so no slave will respond to the 0-address mode command, and no slave will pull down the RS-485 bus during these 80 "U" processes; because during each "U", the host will also detect the bus at 75T in the middle of 150T, which will cause the 80 "U" buses to detect a high level. There are two types of this situation. One is that all slaves have been assigned addresses, there is no 0-address mode slave, and all slaves will not pull down the RS-485 bus; the other is that there is only one largest UUID left, which is FFFFFFFFFF, and each one is 1. The UUID of the slave in the present invention does not set this value.

[0077] Therefore, when the host detects 80 "U"s for the nth time and the 75T time point is high, the automatic address allocation ends, and the number of allocated addresses is n-1, so the slave addresses are from 1 to n-1, see Figure 8 .

[0078] For example, if there are 40 slaves in total, the time base is 1us (for the STM32G0 CPU, the clock is 64MHz, which is fully capable of achieving this speed), the UUID in the embodiment is 10 bits,

[0079] The initial synchronization clock calibration time is: 50T*500+pause time 1000T=25ms+1ms=26ms

[0080] Then the time for allocating a single address is approximately equal to (assuming that a single bit of the serial port command sent is 1us (1.152M)): 1us*40+200T+(8us+150T)*80+50T=240us+12640us+50us≈13ms

[0081] Then the time to allocate 40 slaves is 26ms+13ms*41=559ms, which is much more efficient than the existing minute-level allocation method.

[0082] In summary, the present invention designs a method for automatic address allocation of RS-485 bus based on bit competition mechanism in an efficient and repeatable manner. The advantages of the present invention are that no other control equipment is required for assistance, and there is no connection between slaves. After the host and multiple slaves are connected, as long as the power is turned on, the address allocation can be completed in a short time (tens of milliseconds). The wiring is simple, and the device scalability is strong. As long as the hardware supports it, it can be expanded to more than 100 devices. At the same time, as long as the master-slave device connection is completed, the automatic allocation of multiple slave addresses can be repeated and will not be randomly allocated. In this case, the corresponding device, the address is always unique, which is convenient for the host to determine the slave device object.

Claims

1. An efficient and repeatable RS-485 bus address allocation method based on a bit competition mechanism is applicable to communication between a host and a plurality of slaves, wherein the slaves include at least one memory module for storing a unique identification code; Features The method comprises the following steps: Step 1: Synchronize the clocks between the host and the slave; Step 2: The host sends a broadcast command to the slave to start the automatic allocation of the first address. All slaves are ready to compete for the address upon receiving the broadcast command. Step 2.1, the host sends the first ASCII code U command. After sending the command, the host on the RS-485 bus is a high-impedance input. The host configures the TX line and RX line from the serial port to IO input. The host reads and records the bus status at 75T. This process continues until 150T, and then the host changes to output, and configures the TX line and RX line to the serial port mode, and proceeds to send the next ASCII code U command, where T represents the time base; After receiving the ASCII code U command, the slave divides the 150T time interval into three equal segments. In the first 50T period, each slave determines whether the last bit of its own identification code is 1 or 0, and executes the bit competition mechanism based on the judgment result. Step 2.2: After the slave completes the response to the first ASCII code U command of the host, the host starts to send the second U command; After receiving the second ASCII code U instruction, the slave selected by the bit competition mechanism continues to judge whether the second to last bit of its own identification code is 1 or 0 in the first 50T period, and executes the bit competition mechanism again according to the judgment result; Step 2.3, each time after sending the ASCII code U command, the slave's own identification code judgment bit moves forward by one bit until only one slave is left that has not withdrawn from the competition. At the end of this last comparison, the slave assigns itself an address of 1; Step 3, the host sends the next broadcast command to the slave to start the automatic allocation of the second address. Except for the slave that has been allocated the address, other slaves with address 0 respond to the broadcast command to perform the second address allocation, and still perform multiple ASCII code U command processing, thereby completing the automatic allocation of the second address; Step 4: Repeat step 3 above until all addresses are automatically allocated.

2. The method according to claim 1, characterized in that: During the clock synchronization process, the TX and RX lines of the host and slave need to be configured to meet the synchronization requirements.

3. The method according to claim 2, characterized in that: The host sends N clock pulses, where N is a sufficiently large number to ensure that each slave measures the relationship between a known time and the slave's own timer counting time through pulse capture, and performs step calibration.

4. The method according to claim 1, characterized in that: After completing the synchronization of the clock, the TX line and RX line of the host are configured as serial port mode, and the host remains suspended for a certain period of time, during which time the slave calibrates the internal clock crystal according to the synchronization clock.

5. The method according to any one of claims 1 to 4, characterized in that: The bit competition mechanism is specifically as follows: If the slave determines that its own identification code is 0, the slave will configure the TX line as IO output 0 and the RX line as IO input before the second 50T time interval, and at the same time, the RS-485 bus node of the slave will be output, so as to pull down the RS-485 bus until the second 50T ends; until the third 50T time starts, the RS-485 bus node of the slave will be changed to high-impedance input, and the slave will configure the TX line and RX line to serial port mode, waiting for the next host ASCII code U instruction, and will not exit the competition; If the slave determines that its own identification code is 1, the slave configures the TX line and RX line of the slave's CPU as IO input before the second 50T time interval, the RS-485 bus node of the slave is a high-impedance input, and reads the status of the RS-485 bus at the moment of 75T; When the read RS-485 bus status is low, the slave exits the address competition. When exiting, the slave configures the TX line and RX line to serial port mode. When the read RS-485 bus state is high, then at the beginning of the third 50T time, the slave configures the TX line and RX line to serial port mode.

6. The method according to claim 1, characterized in that: The total number of times the ASCII code U instruction is sent is related to the number of bits of the identification code.

7. The method according to claim 1, characterized in that: The host is an FPGA module, and the slave is a STM32G0 series single-chip microcomputer.

8. The method according to claim 1 or 6, characterized in that: The ASCII code U instruction is expressed in the form of XXID0, where XX represents a logical address, and the number of logical addresses is at most 254; ID represents a label of an ID command, and 0 represents a broadcast address.

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