A display system and a reference monitor

Abstract

The present application discloses a display system and a reference monitor for shortening the startup time of an 8K reference monitor. The system includes: a signal transfer board that receives video data and converts the video data from SDI signal to HDMI signal; a first FPGA that receives the HDMI video signal, parses it into a digital signal, performs image processing on the digital signal, and then sends it to the display screen for display; a FLASH that stores the netlist program of the second FPGA, the first netlist required by the first FPGA in function mode one, and the second netlist required by the first FPGA in function mode two; the data volume of the first netlist is smaller than that of the second netlist; when starting up, the first FPGA enters function mode one; a second FPGA that, after switching the system to the FLASH startup mode and powering on the system, enters the working state by loading the netlist program; in function mode one, configures the first netlist for the first FPGA, and in function mode two, configures the second netlist for the first FPGA.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display system and a reference monitor. Background Art

[0002] In order to improve the display effect of images or videos, reference monitors have gradually emerged in the prior art. Different from common ordinary monitors, reference monitors have extremely high requirements for brightness, contrast ratio, color gamut, product reliability, etc., and are the basis for professionals to measure, judge, and make decisions on images. Therefore, reference monitors are also regarded as the "prototype meter" in the field of image quality in the industry, and are a scale for image quality. Among them, there are already some reference monitors that support a brightness of up to 1000 nits in the full screen range, a contrast ratio of not less than 100,000:1, and can perfectly restore the video signal content of 4K and High Dynamic Range Imaging (HDR). Summary of the Invention

[0003] Embodiments of this application provide a display system and a reference monitor, which are used to improve the data processing speed through two FPGAs, realize the fast display of complex 8K images by the reference monitor, and at the same time, accelerate the startup speed by adopting a smaller netlist, thereby shortening the startup time of the 8K reference monitor.

[0004] In a first aspect, a display system provided by an embodiment of this application includes:

[0005] A signal transfer board, configured to receive video data sent by an input device, convert the video data from a Serial Digital Interface (SDI) signal to a High-Definition Multimedia Interface (HDMI) signal, and then send it to a first FPGA;

[0006] The first FPGA is configured to receive the HDMI video signal sent by the signal transfer board, parse it into a digital signal, and after performing image processing on the digital signal, send it to a display screen for display;

[0007] A FLASH is configured to store the netlist program of the second FPGA, the first netlist required by the first FPGA in a preset function mode one, and the second netlist required by the first FPGA in a preset function mode two; wherein, the data volume of the first netlist is smaller than that of the second netlist; when starting up, the first FPGA enters the function mode one;

[0008] A second FPGA, which is used to enter the working state by loading the netlist program after the system is switched to the FLASH startup mode and the system is powered on; and, in the first function mode, configure the first netlist for the first FPGA, and in the second function mode, configure the second netlist for the first FPGA.

[0009] In the embodiment of the present application, by setting two FPGAs, the data processing speed is improved, and the benchmark monitor can quickly display complex 8K images. Moreover, by using a smaller first netlist to start up the system, the startup speed is accelerated, and the startup time of the 8K benchmark monitor is shortened.

[0010] In a second aspect, a benchmark monitor provided by an embodiment of the present application includes the display system described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a schematic diagram of an application scenario of a benchmark monitor provided by an embodiment of the present application;

[0013] Figure 2 It is a schematic diagram of the structure of a 4K benchmark monitor in the prior art;

[0014] Figure 3 It is a schematic diagram of the overall framework structure of the display system provided by an embodiment of the present application;

[0015] Figure 4 It is a schematic diagram of the structure of the display system in the first function mode provided by an embodiment of the present application;

[0016] Figure 5 It is a schematic diagram of the upgrade process of the display system provided by an embodiment of the present application;

[0017] Figure 6 It is a schematic diagram of the startup process of the display system provided by an embodiment of the present application;

[0018] Figure 7 It is a schematic diagram of the process for the first FPGA in the display system provided by an embodiment of the present application to enter the first function mode;

[0019] Figure 8 It is a schematic diagram of the structure of the display system in the second function mode provided by an embodiment of the present application;

[0020] Figure 9 Schematic diagram of the first FPGA in the display system provided by the embodiment of the present application entering function mode two;

[0021] Figure 10 Schematic diagram of the 2SI format provided by the embodiment of the present application;

[0022] Figure 11 Schematic diagram of the SQD format provided by the embodiment of the present application;

[0023] Figure 12 Schematic diagram of the complete 8K image output composed of 4 HDMI signals with a delay of 0 frames in the display system provided by the embodiment of the present application;

[0024] Figure 13 Schematic diagram of caching 0.5 frames of the input 4 HDMI signals and then displaying them in the display system provided by the embodiment of the present application;

[0025] Figure 14 Schematic diagram of the signal relative position of HDMI_1 lagging behind that of HDMI_2 in the display system provided by the embodiment of the present application;

[0026] Figure 15 Schematic diagram of the maximum delay of the HDMI_2 signal = 0.5 frames + the difference in the relative position between HDMI_1 and HDMI_2 in the display system provided by the embodiment of the present application;

[0027] Figure 16 Schematic diagram of the relative position of the display on the screen being swapped due to the swapping of the relative positions of HDMI_1 and HDMI_2 in the display system provided by the embodiment of the present application;

[0028] Figure 17 Block diagram of the dynamic adjustment of the input delay scheme of the HDMI receiving data processing module in the display system provided by the embodiment of the present application;

[0029] Figure 18 Schematic diagram of the conventional design scheme for data splicing in the display system provided by the embodiment of the present application;

[0030] Figure 19 Schematic diagram of performing different processing in different signal regions in the display system provided by the embodiment of the present application;

[0031] Figure 20 Block diagram of the regional processing of the 8K image signal in the display system provided by the embodiment of the present application;

[0032] Figure 21 Schematic diagram of the conventional regional processing method flow in the display system provided by the embodiment of the present application;

[0033] Figure 22 Overall structure schematic diagram of the display system provided by the embodiment of the present application. Detailed implementation manners

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0035] The terms "first", "second", etc. (if any) in the description and claims of the embodiments of the present application and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0036] The following examples and embodiments are only to be understood as illustrative examples. Although the present specification may refer to "one", "a", or "some" examples or embodiments in several places, this does not mean that each such reference is related to the same example or embodiment, nor does it mean that the feature only applies to a single example or embodiment. The individual features of different embodiments can also be combined to provide other embodiments. In addition, terms such as "include" and "comprise" should be understood not to limit the described embodiments to only the features that have been mentioned; such examples and embodiments may also include features, structures, units, modules, etc. that have not been specifically mentioned.

[0037] The various embodiments of the present application will be described in detail below with reference to the accompanying drawings of the specification. It should be noted that the display order of the embodiments of the present application only represents the sequence of the embodiments, and does not represent the superiority or inferiority of the technical solutions provided by the embodiments.

[0038] Figure 1 FIG. [FIG. number not provided in the original] is a schematic diagram of an application scenario shown according to some embodiments of the present application. The schematic diagram is intended to illustrate a type of scenario in which there are multiple reference monitors, and a server that can communicate with the reference monitors. These reference monitors include, but are not limited to, devices having data transceiver and processing functions, image display functions, and / or sound output functions. In Figure 1 the scenario shown, it includes a control device 100, a reference monitor 200, a mobile device 300, and a server 400.

[0039] Based on the Internet of Everything technology, communication connections can be established between multiple reference monitors in the above scenarios. For example, communication occurs between the mobile device 300 and the reference monitor 200, thereby projecting the screen displayed on the mobile device 300 onto the reference monitor 200. It should be noted that the number of similar terminal devices is not limited here.

[0040] In some embodiments, the control between different display devices can be achieved through the control device 100. For example Figure 1 As shown, the user can control or operate the reference monitor 200 through the control device 100 to switch the display mode, switch the data reception function, etc.

[0041] In some embodiments, the control device 100 can be a remote control. The communication between the remote control and the reference monitor 200 includes infrared protocol communication or Bluetooth protocol communication, and other short-distance communication methods, and the reference monitor 200 is controlled wirelessly or wiredly. The user can input user instructions in ways such as pressing keys on the remote control, voice input, control panel input, and keys on the reference monitor 200 to control the reference monitor 200.

[0042] In some embodiments, the user can switch the display function of the reference monitor 200 through the control device 100, thereby realizing the display of media data in the display mode corresponding to the display function.

[0043] For example, the display scenarios include but are not limited to: movies, sports, news, anime, variety shows, etc. Different display modes are used to display media data in the corresponding display scenarios. For example, the display modes include a game mode and a movie mode; the game mode is suitable for the display scenario of game screens, and the movie mode is suitable for the display scenario of movie video screens. The parameter characteristics of different display modes are different. By switching the display mode to display the display screen corresponding to the display scenario, the display effect is improved.

[0044] Among them, the parameter characteristics of the display mode are reflected in video picture quality parameters and audio sound quality parameters; the video picture quality parameters include but are not limited to: resolution (the number of pixels displayed on the screen of the display device. For example, a resolution of 1920×1080 means that there are 1920 pixels in the horizontal direction and 1080 pixels in the vertical direction. When the screen size of the display device is the same, the higher the resolution, the clearer the picture), brightness (the display brightness of the display device), contrast (the greater the contrast, the clearer the image on the display device and the more vivid and colorful the colors; the smaller the contrast, the more blurred the image on the display device and the grayer the display effect), screen refresh rate (which refers to the number of times the display device screen refreshes the picture per second, such as screen refresh rates: 60Hz, 120Hz, 144Hz, 165Hz, 240Hz, etc. The higher the screen refresh rate, the smoother the picture), color gamut (which refers to the color range area that the display device can display. In the same color space, the higher the color gamut percentage, the wider the color range that can be displayed).

[0045] The audio sound quality parameters include volume (the volume of the sound, that is, the intensity and amplitude of the audio), pitch (the pitch of the sound, that is, the frequency of the audio or the number of changes per second), and timbre (the timbre of the sound, that is, the overtones of the audio).

[0046] For example, when the display scene is an animation, in the corresponding display mode (i.e., the animation mode), the screen refresh rate is 144Hz; when the display scene is news, in the corresponding display mode (i.e., the news mode), the screen refresh rate is 120Hz. In summary, for different display scenes, using the corresponding display mode for display can improve the playback effect of the display screen. It should be noted that the above description of the screen refresh rate is only an example. In any two display modes, there may be multiple different parameter characteristics, which are not specifically limited here.

[0047] The term "remote control" used in the embodiments of the present application refers to a component of an electronic device (such as the reference monitor disclosed in the present application), which can usually wirelessly control the electronic device within a relatively short distance range. Generally, it is connected to the electronic device using infrared and / or radio frequency (RF) signals and / or Bluetooth, and may also include functional modules such as WiFi, wireless USB, Bluetooth, and motion sensors. For example: a handheld touch remote control replaces most of the physical built-in hard keys in a general remote control device with a user interface on the touch screen.

[0048] The term "gesture" used in the embodiments of the present application refers to a user behavior in which a user expresses an intended idea, action, purpose / or result through a change in hand shape or a hand movement, etc.

[0049] See Figure 2, the 4K reference monitor in the prior art is designed based on the architecture of "FPGA (Field Programmable Gate Array) + SOC (System on Chip) + display screen". Among them, the SOC needs a lot of time to complete the loading and initialization of the software program before it can start normal operation, which restricts the startup screen speed of the power-on display. Moreover, with the increase in the amount of data processing, this architecture can no longer meet the requirements of the 8K reference monitor display system. Currently, there is no reference monitor that can receive 8K signal input and display 8K at the same time. Next, the embodiment of the present application proposes a solution for an 8K reference monitor display system with a simple architecture and fast startup speed.

[0050] The overall display system framework is as Figure 3 shown. The embodiment of the present application adopts the system architecture of "SDI to HDMI adapter board + dual FPGA + display screen". The video data is transmitted from the input device to the SDI to HDMI adapter board (i.e., Figure 3 the SDI to HDMI 2.0 module in it), and converts the SDI (Serial Digital Interface) signal into an HDMI (High-Definition Multimedia Interface) signal and sends it to the inside of the first FPGA. Inside the first FPGA, the HDMI receiving data processing module parses the video signal into a digital signal and sends it to the data processing function module. The data processing function module performs image overlay or picture quality processing such as HDR on the signal. The signal processed by the data processing function module is sent to the backend through the sending module and finally displayed on the display screen. The second FPGA, as an FPGA with an ARM core, mainly plays a system control role, such as including: netlist configuration of the first FPGA, parameter configuration, menu generation, and system control, etc.

[0051] Next, a more specific example of the display system provided by the embodiment of the present application is given.

[0052] As Figure 3 shown, in some embodiments, the SDI to HDMI adapter board, the first FPGA, the second FPGA, FLASH (flash memory), SD card (Secure Digital Memory Card), and DDR (Double Data Rate synchronous dynamic random access memory) together constitute the display system provided by the embodiment of the present application. Among them:

[0053] In some embodiments, the SDI-to-HDMI adapter board (i.e., the signal conversion board) realizes the conversion of SDI signals to HDMI signals. This adapter board increases the number of input interfaces. The interior of this adapter board is jointly composed of 4 SDI-to-HDMI chips, namely SDI2HMI_1, SDI2HMI_2, SDI2HMI_3, and SDI2HMI_4 as shown in Figure 3 . Each chip supports up to 4 SDI inputs (for example, SDI2HMI_1 has 4 SDI_1 inputs), and can support up to 16 SDI signal inputs in total. This design simplifies the implementation solution for 8K signal transmission. Because the implementation of the SDI protocol inside the FPGA is relatively complex, if 16 SDI protocols are implemented, it will consume too many resources inside the FPGA. The SDI interface is commonly used in professional recording and broadcasting equipment. SDI signal transmission has rich transmission protocols. For example, 4K video data can be transmitted through a 12G SDI signal, or through 2 6G SDI signals, or 4 3G SDI signals.

[0054] In the embodiments of the present application, 4 SDI-to-HDMI chips are used, and each chip has 4 SDI signal interfaces. It can be compatible with playback devices that receive single-channel, dual-channel, and four-channel SDI signals, making the technical solution provided by the embodiments of the present application more generally applicable and suitable for more client devices. Multiple similar interfaces can be directly switched for display through buttons. This avoids the trouble caused by frequently manually changing interfaces. For example, a single chip has 4 SDI signals. Then 4 SDI signal lines can be connected to 4 single-channel SDI playback devices. These four single-channel SDI playback devices can be switched and displayed in real time. Similarly, there are a total of 16 SDI signals in the embodiments of the present application, which can be connected to four 4-channel SDI playback devices. Then the output signals of these four 4-channel SDI playback devices can be displayed on the screen end simultaneously or separately.

[0055] In summary, through the above form of signal conversion, it not only enriches the interface resources and increases the application scenarios, but also saves the resource consumption inside the FPGA. Due to the SDI-to-HDMI adapter board, which converts diverse SDI protocols into a single HDMI signal, the FPGA only needs to parse out 4 single HDMI signals internally, without having to consider the complex 16 SDI protocols. Therefore, compared with the prior art, the embodiments of the present application save approximately 75% of the resource consumption of the input interface under the premise of achieving the same function. Thus, it achieves the beneficial effects of streamlining the internal design architecture of the FPGA and reducing the product cost.

[0056] In some embodiments, the first FPGA reserves an HDMI 2.1 interface, facilitating the access of professional playback devices. The HDMI 2.1 interface can transmit data at 8K@60hz, while the HDMI 2.0 interface can transmit up to 4K@60hz. The maximum resolution of each output HDMI 2.0 signal can support up to 4K. Thus, 4 HDMI channels can transmit 8K image data.

[0057] The first FPGA: The system core chip, responsible for parsing the input image, sending the image data to the display screen, processing the image quality, image overlay, etc.

[0058] The second FPGA: An FPGA with an ARM core, mainly performing system control functions and providing system auxiliary functions.

[0059] The chips in the second FPGA are divided into two parts:

[0060] The PL part, i.e., Programmable Logic, the logic function part.

[0061] The PS part, i.e., Processing System, the processor system part, containing an ARM core.

[0062] FLASH: Stores the netlist required for the startup of the first FPGA, and the netlist program, configuration parameters, startup pictures, and other data required by the second FPGA.

[0063] SD card: Reserved for system version upgrade, storing the data required for system upgrade.

[0064] DDR: Used for data caching to improve the efficiency of data transmission.

[0065] Regarding the above first FPGA and second FPGA, further examples are given below:

[0066] HDMI received data processing module: Performs serial-to-parallel conversion of HDMI data, converting the serial data of the front-end device, such as Figure 3 HDMI_1, HDMI_2, HDMI_3, HDMI_4 shown in, into parallel digital signals, and splicing these 4 4K HDMI signals into one 8K signal. For example, arranging and combining the data according to the transmission protocol; or, amplifying a single HDMI signal into an 8K signal. For example, using a scaling algorithm to magnify the image from 4K to 8K.

[0067] Data processing function module: performs different processes on images, such as data superposition, selection, and image quality processing, so as to display different effects. For example, it can display effects such as HDR (High-Dynamic Range), HLG (Hybrid Log Gamma), and SDR (Standard Dynamic Range). Transmission module: performs parallel-to-serial conversion of data, converts parallel digital signals into serial signals, and sends them to the display screen at the back end for display.

[0068] Parameter configuration module: receives externally configured parameter data and configures the parameters into the data processing function module. The parameter data includes, for example, selection parameters for displaying different effects, parameter information for when to select the HDR effect or the HLG effect, or lookup table (LUT) parameters required inside HDR and HLG.

[0069] In some embodiments, the data processing function module includes, for example, an image quality processing module (which includes an HDR function module, an HLG function module, etc.), a data superposition module, a data selection module, etc. Each module corresponds to its own corresponding parameters. For example, the HDR module needs to be configured with resolution parameters, lookup table parameters, etc. These parameters can be sent to the corresponding function modules through the parameter configuration module to achieve parameter configuration. The internal function modules of the FPGA are configurable modules. For example, by simply changing the resolution parameters, it can process image data of 1080P, 4K, or 8K.

[0070] In some embodiments, the second FPGA includes:

[0071] PL part: performs fast data transfer processing.

[0072] PS part: draws menus, controls the system, etc.

[0073] In some embodiments, as Figure 4 shown, the PL part of the second FPGA adopts a modular design.

[0074] Among them:

[0075] Netlist configuration module, used for configuring the netlist of the first FPGA.

[0076] FLASH read / write module, used for operations such as reading, writing, and erasing FLASH.

[0077] SD card read module, used for reading data in the SD card.

[0078] The menu sending module is used to send the menu drawn by PS to the first FPGA for data superposition processing. The menu sending module will send the menu image data to the data superposition module in the first FPGA. The data superposition module will superpose the menu image data onto the full-screen image obtained from the front-end HDMI receiving data processing module, such as to achieve the picture-in-picture effect or the effect of a computer menu.

[0079] The startup screen sending module is used to send the startup picture data saved in the FLASH to the first FPGA.

[0080] The DDR read-write module is a module for reading and writing to the DDR, which performs data caching. It is an intermediary between other modules inside the PL and the DDR particles.

[0081] In some embodiments, as Figure 4 shown, in the first FPGA:

[0082] The data superposition module is used to superpose the menu image data sent by the menu sending module onto the full-screen image to generate, for example, a picture-in-picture or a computer menu, etc.

[0083] The data selection module is used to select which path of data to transmit to the subsequent sending module as needed. The selected data comes from the startup screen sending module in the second FPGA or the data superposition module.

[0084] Figure 4 In functional mode 1 shown in

[0085] Similarly, Figure 8 in functional mode 2 shown in

[0086] In some embodiments, when the entire system needs to be upgraded, refer to Figure 5 , which includes the following steps:

[0087] 501. Output a user interface, obtain a user instruction through this user interface, and in response to this user instruction, set the system to the SD card upgrade mode;

[0088] 502. Power on the system;

[0089] 503. The second FPGA automatically loads the netlist program from the SD card;

[0090] 504. The second FPGA enters the working state. Among them, the PL needs to configure the netlist file, and the PS needs to load the menu and control program.

[0091] 505. The FLASH read / write module erases the original data in the FLASH.

[0092] 506. The SD card read module reads the data to be upgraded in the FLASH from the SD card.

[0093] 507. The FLASH read / write module writes the data to be upgraded into the FLASH.

[0094] 508. Complete the update and upgrade of the data version in the FLASH.

[0095] In some embodiments, the boot process of the display system provided in the embodiments of the present application is introduced as follows:

[0096] Since it is necessary to process 8K data volume, the chip scale of the first FPGA is relatively large. Correspondingly, as the internal function of the first FPGA becomes more powerful, the netlist file of the first FPGA is also increasing. And the size of the first FPGA netlist file is the main factor affecting the boot speed of the display system provided in the embodiments of the present application. When the internal function of the first FPGA is simple, the generated netlist file will be reduced. On the contrary, when the internal function of the FPGA is complex, the netlist file will become larger. The complex image quality processing function will consume most of the resources inside the FPGA. Based on this, the technical solution provided in the embodiments of the present application generates two groups of netlists according to different main function modes inside the FPGA:

[0097] The first netlist corresponds to the first FPGA function mode 1. At this time, the internal processing of the first FPGA is simple, the scale of the first netlist is small, and the configuration speed is fast.

[0098] The second netlist corresponds to the second FPGA function mode 2. At this time, the internal processing of the first FPGA includes complex image quality processing functions, the scale of the second netlist is large, and it takes a longer time to load the netlist.

[0099] In order to shorten the boot time, when booting, set the first FPGA to enter function mode 1 to reduce the time corresponding to the configuration netlist of the first FPGA. Correspondingly, the time for the first FPGA to enter the working state will be shortened, the time required for the entire system to enter the working state will be shorter, and the entire boot process will also be accelerated.

[0100] As Figure 6 shown, the system boot process (at this time the first FPGA is in function mode 1) includes the following steps:

[0101] 601. Output the user interface, and receive user instructions through the user interface, and switch the entire system to the FLASH startup mode in response to the user instructions;

[0102] 602. Power on the system;

[0103] 603. The second FPGA automatically loads the netlist program from the FLASH;

[0104] 604. The PL and PS in the second FPGA enter the working state.

[0105] 605. The FLASH read / write module reads the first netlist of the first FPGA from the FLASH.

[0106] 606. The netlist configuration module configures the first netlist for the first FPGA.

[0107] 607. Complete the configuration of the first FPGA;

[0108] 608. The FLASH read / write module reads the startup picture data from the FLASH.

[0109] 609. The write module in the DDR read / write module writes the startup picture into the DDR for caching.

[0110] 610. The read module in the DDR read / write module reads the startup picture;

[0111] 611. The startup screen sending module sends the startup picture to the data selection module.

[0112] 612. The data selection module selects the startup picture and sends it to the backend display for display.

[0113] 613. Complete the startup power-on display process.

[0114] Since the menu design occupies a large amount of internal resources of the FPGA, in order to save the internal resources of the FPGA and increase the design flexibility, in the embodiment of the present application, the menu design part is completed in the PS part of the second FPGA. Through the menu sending module in the second FPGA, the menu data is sent to the first FPGA for superposition.

[0115] In some embodiments, as Figure 7 shown, the process for the first FPGA to enter the function mode one, for example, includes:

[0116] 701. The first FPGA completes the configuration of the first netlist;

[0117] 702. The startup screen ends;

[0118] 703. The menu sending module sends the menu image data to the data superposition module.

[0119] 704. The HDMI received data processing module analyzes the data received from the front end.

[0120] 705. The data overlay module overlays the menu image data onto the image data output by the front-end HDMI receiving data processing module.

[0121] 706. The data selection module selects the image data after data overlay and sends it to the sending module.

[0122] 707. The sending module sends the data with the menu image data overlaid at the front end to the back-end display screen for output display;

[0123] 708. The first FPGA enters the function mode one state. The user can see the image input by the front-end input device, switch the channel mode through the menu button, etc., and can select the input channel through the menu. For example, an 8K image from HDMI 2.1 channel 1 can be selected for display, or an image from 4 HDMI 2.0 channels can be selected for display.

[0124] Function mode one can provide the function of an ordinary display screen for the user. When professional display functions are required, the reference monitor function needs to be switched to the function mode two state.

[0125] In some embodiments, the display system structure in function mode two is as Figure 8 shown. It can be seen that the difference from function mode one is that, at this time, among the data processing function modules in the first FPGA, the modules in the working state include the image quality processing module and the data overlay module.

[0126] In some embodiments, as Figure 9 shown, the process of entering function mode two includes:

[0127] 901. When the startup screen is displayed, the user interface is output, and the user instruction is received through this user interface. In response to this user instruction, the first FPGA is set to enter working mode two.

[0128] 902. The FLASH read / write module in the second FPGA reads the second netlist and configuration parameters of the first FPGA from the FLASH;

[0129] 903. The DDR read / write module writes the second netlist and configuration parameters of the first FPGA into the DDR. Prepare in advance for the first FPGA to enter function mode two.

[0130] 904. Through the menu sending module, an instruction to switch from function mode one to function mode two is sent to the first FPGA.

[0131] 905. The DDR read / write module reads the second netlist of the first FPGA from the DDR.

[0132] 906. The second netlist is configured for the first FPGA through the netlist configuration module.

[0133] 907. The first FPGA completes the configuration of the second netlist.

[0134] 908. The DDR read / write module reads configuration parameters from the DDR.

[0135] 909. Send the configuration parameters to the parameter configuration module in the first FPGA. Specifically, the DDR read / write module reads the parameters from the DDR and sends them to the PS (ARM) side. The PS side sends the parameters to the parameter configuration module through the SPI transmission protocol.

[0136] 910. The parameter configuration module completes the parameter configuration of the image quality processing module.

[0137] 911. The data overlay module overlays the menu onto the front-end image.

[0138] 912. The sending module sends the overlaid data to the back-end display for display.

[0139] 913. The first FPGA enters function mode two.

[0140] In some embodiments, the delay requirements for signals are very strict, especially when relaying programs such as high-speed sports events and e-sports competitions. When multiple HDMI signals are input, there are situations of synchronous and asynchronous multiple signals. For example, when 4 HDMI signals jointly transmit 8K signals, the 4 HDMI signals are transmitted from the same device to the FPGA, and it can be considered that these 4 HDMI signals are frame start synchronous signals. When these 4 HDMI signals come from different devices respectively, it can be considered that the frame start positions of these 4 HDMI signals are asynchronous. Therefore, in order to reduce the delay of video signals, the embodiments of the present application also propose a scheme for dynamically adjusting the input delay.

[0141] Case 1: When the frame start signals of 4 HDMI signals are synchronous. For example, when using 4 SDI lines to transmit 8K signals, according to the SDI protocol, there are two basic data combination methods: as Figure 10 shown in the 2SI format, and as Figure 11 shown in the SQD format.

[0142] When the 4 HDMI signals are transmitted in the 2SI format, each signal transmits 2 pixels, as Figure 10 shown, and they are arranged according to a certain rule. At this time, the input image data can be combined in real time to form an 8K image, and the 4 HDMI signals form a complete 8K image output, with only a few clock delays, so it can be represented by a delay of 0 frames, as Figure 12 shown.

[0143] When the 4-channel HDMI signals are transmitted in the SQD format, each channel transmits a complete 1 / 4 part of the 8K signal, arranged in a "field" shape. In order to completely splice the 8K image "from left to right, from top to bottom", it is necessary to buffer the input 4-channel HDMI signals for 0.5 frames and then display them, as Figure 13 shown.

[0144] Case 2: When the frame start signals of the 4-channel HDMI signals are asynchronous, for example, each channel is connected to a different playback device, and the four regions on the screen are displayed independently.

[0145] The situation is as shown in 15. The frame start signals of the 4-channel HDMI signals are not synchronized. In order to reduce the delay of data combination, first sort according to the relative positions of the frame starts of each channel signal. As Figure 14 shown, the relative position of the HDMI_1 signal lags behind that of the HDMI_2. Then, through relative position adjustment, the relative positions of HDMI_1 and HDMI_2 are swapped. The start positions of all signals are arranged in order.

[0146] Then, at this time, the 4-channel signals form a complete 8K signal data.

[0147] See Figure 15 , the maximum delay of the HDMI_2 signal = 0.5 frame + the difference in relative positions between HDMI_1 and HDMI_2;

[0148] The delay of the HDMI_1 signal = 0.5 frame;

[0149] The delays of the HDMI_3 and HDMI_4 signals < 0.5 frame;

[0150] Since the relative positions of HDMI_1 and HDMI_2 are swapped, the relative display positions at the screen end will also be swapped, as Figure 16 shown.

[0151] Figure 17 It is a block diagram of the dynamic adjustment input delay scheme of the above HDMI received data processing module. After the 4-channel HDMI signals are parsed by the HDMI parsing module, they are sent to the phase comparison and detection module to detect the relative positions of the frame start signals of each data. According to the relative positions and processing types of each channel signal, the data of each channel signal is buffered and delayed through the data buffer module. In the data alignment and splicing module, the 8K image is completely spliced "from left to right, from top to bottom" and output to the backend data processing function module.

[0152] For the splicing of the corresponding data, the conventional design scheme is as Figure 18As shown in the figure, first cache all input data for one frame time, and then perform image stitching. The advantage of this method is its simple design. However, there is a large data delay and it occupies a large data cache space. The above solution provided by the embodiments of the present application performs dynamic input adjustment on different signals through signal classification, ensuring the real-time performance of the display signal to the greatest extent.

[0153] When four HDMI signals are independently displayed on the display screen, in some embodiments, different processing needs to be performed in different signal areas. For example Figure 19 As shown in the figure, Picture 1 calls the Gamm 2.2 curve, Picture 2 calls the Gamma 2.4 curve, Picture 4 calls the Gamm 2.6 curve, and Picture 4 calls the Gamma 2.2 curve.

[0154] In some embodiments, the form of coordinate area division is adopted for image processing. For example Figure 20 As shown in the figure, the data processing module receives the input of 8K image signals. According to the relative positions of the vertical and horizontal pixel parameters of the displayed image, the image is positioned by coordinates. Each rectangular area is composed of four coordinates. For example Figure 19 For Picture 1 in the figure, the rectangular area can be determined by the four vertices (a, b), (a, c), (d, b), and (d, c). Among them, the a and d coordinates represent the row numbers of the vertex pixels, and the b and c represent the column numbers of the pixel points.

[0155] For example Figure 20 is the block diagram of sub-region processing. The 8k image signal is input to the data processing function module. The coordinate allocation module receives the settings from the outside, for example, including: Picture 1 realizes the Gamma 2.2 function, and the vertex coordinates of the rectangular area of Picture Area 1 are (a, b), (a, c), (d, b), and (d, c) respectively. Then when it is detected that the pixel position of the 8K image signal satisfies the condition: (d >= row number >= a) & (c >= column number >= b), the parameter call module calls the Gamma 2.2 parameters in the parameter storage module for data configuration, so that the image in Picture Area 1 shows the Gamma 2.2 effect.

[0156] For example Figure 21 is a conventional sub-region processing method. This method calls the data processing module once for one data path. Then, the data is stitched and combined through the data superposition module. This method consumes a large amount of resources and has a high cost. Compared with the conventional method, the above solution provided by the embodiments of the present application saves a large amount of logic resources and can save about 75% of the resource consumption.

[0157] In summary, referring to Figure 22 a display system provided by the embodiments of the present application includes:

[0158] The signal transfer board 11 is used to receive the video data sent by the input device, convert the video data from the Serial Digital Interface (SDI) signal to the High-Definition Multimedia Interface (HDMI) signal, and then send it to the first FPGA.

[0159] The first FPGA 12 is used to receive the HDMI video signal sent by the signal transfer board, parse it into digital signals, and after performing image processing on the digital signals, send them to the display screen for display.

[0160] The FLASH 13 is used to store the netlist program of the second FPGA, the first netlist required for the first FPGA to be configured in a preset function mode 1, and the second netlist required for the first FPGA to be configured in a preset function mode 2; wherein, the data volume of the first netlist is smaller than that of the second netlist; when powered on, the first FPGA enters the function mode 1.

[0161] The second FPGA 14 is used to enter the working state by loading the netlist program after switching the system to the FLASH startup mode and powering on the system; and, in the function mode 1, configure the first netlist for the first FPGA, and in the function mode 2, configure the second netlist for the first FPGA.

[0162] A reference monitor provided by an embodiment of the present application includes the above display system.

[0163] It can be seen that in the existing 4K reference monitor, the SOC chip needs a lot of time to complete the loading and initialization of the software program before it can start normal operation, which restricts the startup screen speed of the startup display, and there is no dedicated 8K monitor SOC chip on the market yet. Compared with the existing 4K reference monitor, the embodiment of the present application has the following beneficial effects:

[0164] Using the second FPGA with a faster data processing speed to replace the SOC chip not only simplifies the system but also speeds up the data processing speed;

[0165] In the design of loading the FPGA netlist, an active configuration method is adopted. When powered on, a smaller netlist (the first netlist) is used to speed up the startup speed and shorten the startup time;

[0166] In terms of the startup screen display, the internal hardware logic (PL part) of the second FPGA is directly used to transfer data, and complex 8K images can be quickly displayed. It is faster than the method of using software by the SOC to transfer data and display the startup screen.

[0167] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. A display system, characterized in that, the system includes: A signal transfer board, which is used to receive the video data sent by the input device, convert the video data from the Serial Digital Interface (SDI) signal to the High-Definition Multimedia Interface (HDMI) signal, and then send it to the first FPGA; The first FPGA is used to receive the HDMI video signal sent by the signal transfer board, parse it into digital signals, and after performing image processing on the digital signals, send them to the display screen for display; FLASH is used to store the netlist program of the second FPGA, the first netlist required for the first FPGA to be configured in a preset function mode one, and the second netlist required for the first FPGA to be configured in a preset function mode two; wherein, the data volume of the first netlist is smaller than that of the second netlist; when powered on, the first FPGA enters the function mode one; The second FPGA is used to enter the working state by loading the netlist program after switching the system to the FLASH startup mode and powering on the system; and, in the function mode one, configure the first netlist for the first FPGA, and in the function mode two, configure the second netlist for the first FPGA; wherein, the first FPGA includes: An HDMI received data processing module, which is used to convert the serial HDMI video signal input by the signal transfer board into a parallel digital signal; A data processing function module, which is used to perform image processing on the digital signal; A sending module, which is used to convert the parallel digital signal processed by the data processing function module into a serial video signal and then send it to the display screen for display; A parameter configuration module, which is used to configure parameters for the data processing function module under the control of the second FPGA; The data processing function module includes: a data overlay module, a data selection module, and a picture quality processing module; wherein, In the function mode one, the data overlay module overlays the menu image data from the second FPGA with the digital signal output by the HDMI received data processing module to obtain the overlaid image data; the data selection module selects to output the startup screen from the second FPGA or the image data output by the data overlay module to the sending module; In the function mode two, the picture quality processing module performs picture quality processing on the digital signal output by the HDMI received data processing module; the data overlay module overlays the menu image data from the second FPGA with the image data output by the picture quality processing module to obtain the overlaid image data.

2. The system according to claim 1, characterized in that, the second FPGA includes: A logic function module, which is used to enter the working state by loading the netlist program after the system is switched to the FLASH startup mode and the system is powered on; and, in Function Mode 1, configure the first netlist for the first FPGA, and in Function Mode 2, configure the second netlist for the first FPGA; A processor system module, which is used to draw menu image data.

3. The system according to claim 2, wherein, the system further includes: an SD card, which is used to store data required for system upgrade; a DDR, which is used to cache data; the logic function module includes: a netlist configuration module, which is used to configure the first netlist for the first FPGA in Function Mode 1 and configure the second netlist for the first FPGA in Function Mode 2; a FLASH read / write module, which is used to perform read / write / erase operations on the FLASH; an SD card read module, which is used to read data in the SD card; a menu sending module, which is used to send the menu image data drawn by the processor system module to the first FPGA, and the first FPGA performs image data superposition processing on the menu image data; a startup screen sending module, which is used to send the startup picture saved in the FLASH to the first FPGA; a DDR read / write module, which is used to perform data read / write operations on the DDR.

4. The system according to claim 3, wherein, when the system is switched to the FLASH startup mode and the system is powered on, when the second FPGA enters the working state: the FLASH read / write module reads the first netlist from the FLASH; the netlist configuration module configures the first netlist for the first FPGA; the FLASH read / write module reads the startup picture from the FLASH; the DDR read / write module writes the startup picture into the DDR for caching; and reads the startup picture from the DDR and sends it to the sending module; the sending module sends the startup picture to the data selection module; the data selection module selects to send the startup picture to the display screen for display.

5. The system according to claim 3, wherein, when the display screen displays the startup screen, the FLASH read / write module reads the second netlist and configuration parameters from the FLASH; the DDR read / write module writes the second netlist and configuration parameters into the DDR; the menu sending module is further used to send an instruction to switch from Function Mode 1 to Function Mode 2 to the first FPGA; the DDR read / write module reads the second netlist from the DDR; the netlist configuration module configures the second netlist for the first FPGA; the DDR read / write module reads the configuration parameters from the DDR and sends the configuration parameters to the parameter configuration module in the first FPGA; the parameter configuration module completes the parameter configuration of the image quality processing module according to the configuration parameters; The data overlay module overlays the menu image data onto the image processed and output by the image quality processing module; The sending module sends the overlaid image data to the display screen for display.

6. The system according to claim 3, wherein, when the system needs to be upgraded: the second FPGA enters the working state by loading the netlist program from the SD card; the FLASH read / write module erases the original data in the FLASH; the SD card read module reads the data that the FLASH needs to be upgraded from the SD card; the FLASH read / write module writes the data that the FLASH needs to be upgraded into the FLASH, completing the update and upgrade of the data version in the FLASH.

7. The system according to claim 1, wherein, the signal transfer board includes 4 SDI-to-HDMI chips, each of which supports 4-channel SDI signal input, and the 4 chips output 4-channel HDMI signals to the first FPGA in total; the HDMI signals output by the chips are HDMI 2.0 signals, and the interface between the first FPGA and the signal transfer board is an HDMI 2.0 signal interface; the first FPGA further includes an HDMI 2.1 signal interface for receiving HDMI 2.1 signals input by an input device.

8. The system according to claim 1, wherein, the HDMI received data processing module includes: an HDMI parsing module, a phase comparison and detection module, a data caching module, and a data alignment and splicing module; among them, after the HDMI parsing module parses the input multi-channel HDMI signals, it sends them to the phase comparison and detection module to detect the relative positions of the frame start signals of each channel of HDMI signals, and according to the relative positions and processing types, performs data caching and delay on each channel of HDMI signals through the data caching module. In the data alignment and splicing module, a complete image is spliced according to a preset rule and output to the data processing function module.

9. The system according to claim 1, wherein, the first FPGA further includes: a coordinate allocation module, a parameter calling module, and a parameter storage module; among them, when an image signal is input to the data processing function module, the coordinate allocation module receives setting information from the outside, and the setting information includes the effect that the picture needs to display and the vertex coordinate positions of the rectangular area of the picture; when it is determined according to the vertex coordinate positions of the rectangular area of the picture that the pixel position of the image signal input to the data processing function module is within the rectangular area, the parameter calling module calls the parameters corresponding to the effect in the parameter storage module for data configuration, so as to realize the display of the effect of the image within the rectangular area of the picture.

10. A reference monitor, wherein, the reference monitor includes the display system according to any one of claims 1-9 above.

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