Feature extraction and quality evaluation method for plugging vias on integrated chip substrates and related devices

Abstract

The present invention discloses a method for extracting and evaluating the features of plugged vias on integrated chip substrates and related devices, which are applied to the processor of an optical inspection system for integrated chip substrates. The method comprises: scanning a target integrated chip substrate with multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip substrate; determining the defect type and defect quantification degree of the target plugged vias based on the 2D and 3D image data of the target integrated chip substrate; and obtaining a quality evaluation result of the plugged vias on the integrated chip substrate based on the defect type and defect quantification degree of the plugged vias on the target integrated chip substrate. This method solves the problem of manual re-evaluation costs caused by the limitations of 2D images in traditional 2D automatic optical inspection technology, and realizes a high-speed, high-coverage automated defect summarization and quantitative analysis method for plugged vias on integrated chip substrates with micron precision.

Description

Technical Field

[0001] The present invention relates to the general field of image data processing in optical measurement, and in particular to a method for extracting and evaluating the characteristics of plug holes on an integrated chip carrier board and a related device. Background Art

[0002] Integrated circuit (IC) substrates have evolved with the continuous advancement of semiconductor packaging technology. In the high-end packaging sector, IC substrates have become an indispensable component of chip packaging. They not only provide support, heat dissipation, and protection for the chip, but also provide the electronic connection between the chip and the printed circuit board (PCB) motherboard, acting as a bridging link. They can even embed passive and active components to enable certain system functions. IC substrates are relatively high-end PCBs. Evolved from high-density interconnect (HDI) boards, they feature high density, high precision, miniaturization, and thinness. IC substrate products are broadly categorized into five categories: memory chip IC substrates, micro-electromechanical system IC substrates, radio frequency module IC substrates, processor chip IC substrates, and high-speed communication IC substrates. They are primarily used in mobile smart devices, services / storage, and other applications. Currently, IC substrate via defects are typically detected using 2D optical inspection systems, a method known as 2D automated optical inspection (AOI) systems. The 2DAOI system uses multiple light sources and one or more stationary industrial cameras for inspection. The light sources illuminate the IC substrate vias from various angles. The cameras then capture still images or videos of the board, compiling them to create a complete picture of the device. Finally, the system compares these captured images with the design specifications or approved complete units to obtain defect information for the vias, such as irregular vias, air bubbles, sunken vias, and voids.

[0003] 2DAOI is a mature and accurate technology that can detect many faults in PCBs and is very useful at many stages of the PCB production process. However, 2DAOI has considerable limitations. The 2DAOI system extracts features from 2D images and re-evaluates defects based on image grayscale information, which is inevitably affected by dirt. When dirt is present in the hole, it is easily detected as a false defect point, increasing the cost of manual re-evaluation. Both hole bubbles and hole voids have quasi-circular image features, and defect summarization suffers from classification anomalies. It is impossible to quantitatively determine the depth of hole bubbles, hole voids, and hole depressions, nor can it provide information on the quality of the plugged hole morphology. How to achieve accurate summarization and quantitative analysis of integrated chip substrate plugged hole defects in a fully automated manner with micron precision, high speed, and high coverage is one of the important issues that need to be addressed in this field. Summary of the Invention

[0004] In response to the above problems, the example of this application provides a feature extraction and quality evaluation method and related device for integrated chip substrate plug holes, which solves the problem of manual re-judgment costs caused by the limitations of 2D images in traditional 2DAOI technology, and realizes an automated defect induction and quantitative analysis method for integrated chip substrate plug holes with high speed and large coverage under micron precision.

[0005] To achieve the above objectives, in a first aspect, embodiments of the present application provide a method for extracting and evaluating the features of plugged vias on an integrated chip carrier, which is applied to a processor of an optical inspection system for an IC carrier, the optical inspection system including multiple scanning cameras and a processor. The method comprises:

[0006] The target integrated chip carrier is scanned by multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier; the defect type and defect quantification degree of the target plugged hole are obtained based on the 2D and 3D image data of the target integrated chip carrier; and the quality evaluation result of the plugged hole of the integrated chip carrier is obtained based on the plugged hole defect type and defect quantification degree of the target integrated chip carrier.

[0007] It can be seen that in the real-time example of the present application, multiple scanning cameras scan to obtain 2D and 3D image data of the target integrated chip carrier, which solves the limitations of 2D images in traditional 2DAOI technology, resulting in low automatic detection precision and low accuracy resulting in manual re-judgment cost problems. The defects of the plug holes of the target integrated chip carrier are classified and quantitatively analyzed based on the 2D and 3D image data, realizing an automated defect summarization and quantitative analysis method for the plug holes of the integrated chip carrier with high speed and large coverage under micron precision.

[0008] In combination with the first aspect, in a possible embodiment, height plane fitting is performed on the 3D image data of the plug hole center of the target plug hole in the target integrated chip carrier to obtain the height plane coefficient of the target plug hole; the flatness of the target plug hole is obtained based on the height plane coefficient and the 3D image data of the target integrated chip carrier, and the smaller the flatness, the flatter the 3D plane of the corresponding target plug hole; if the flatness of the target plug hole is less than a first preset threshold, the 2D image data of the target plug hole is segmented to obtain a segmented area of ​​the 2D image data of the target plug hole; the first grayscale information of the segmentation and the second grayscale information of the 2D image of the target integrated chip carrier are obtained, and the difference value between the first grayscale information and the second grayscale information is calculated; if the difference value is greater than the second preset threshold, the defect type of the target plug hole is determined to be hole dirtiness.

[0009] In combination with the first aspect, in a possible embodiment, if the flatness of the target plugged hole is greater than a first preset threshold, the method further includes: extracting pixel points that are greater than a first preset number of pixel points from all pixel points of the target plugged hole based on the height plane coefficient and the position coordinates of the extracted pixel points of the target plugged hole in the 3D image data; calculating the difference between the actual height value and the fitted value of all position coordinates of the target plugged hole in the 3D image data to obtain a concave-convex data set of the target plugged hole; recording all values ​​in the concave-convex data set that are greater than a third preset threshold as a convex data set, and recording all values ​​that are less than a fourth preset threshold as a concave data set; if the values ​​in the convex data set are greater than the values ​​in the concave data set, determining that the defect type of the target plugged hole is a hole bubble.

[0010] In combination with the first aspect, in a possible embodiment, if the values ​​in the concave data set exceed the values ​​in the convex data set, the method further includes: performing spatial sphere fitting based on the values ​​in the concave data set to obtain a spatial sphere equation; solving the spatial sphere equation in combination with the 3D data image data of the target plugged hole to obtain a goodness of fit corresponding to the concave data set, and determining whether the concave data set of the target plugged hole satisfies a spherical morphology based on the goodness of fit; segmenting the 2D image data of the target plugged hole to obtain a planar image corresponding to the target plugged hole; performing elliptical feature extraction on the planar image corresponding to the target plugged hole to obtain a major axis and a minor axis included in the elliptical feature, and judging the defect type of the target plugged hole based on the ratio of the major axis to the minor axis; if it is determined that the concave data set of the target plugged hole satisfies a spherical morphology and the target plugged hole meets the elliptical feature, then determining that the defect type of the target plugged hole is a hole void; if it is determined that the concave data set of the target plugged hole meets the non-spherical morphology and the target plugged hole does not meet the elliptical feature, then determining that the defect type of the target plugged hole is a hole concave.

[0011] In the embodiments of the present application, it can be seen that a data set of the flatness and concave-convexity of the target integrated chip carrier via plane is obtained based on the 2D and 3D image data of the target integrated chip carrier. Based on the data set of the flatness and concave-convexity of the via plane, it can be accurately determined whether the target via has defects and the type of defects. This improves the recognition accuracy and efficiency of the optical inspection system for integrated chip carrier vias, thereby reducing the manual re-judgment costs in traditional 2D optical inspection systems.

[0012] In combination with the first aspect, in a possible embodiment, the defect quantification degree of the target plugged hole includes any one of the contamination area, protrusion height, and depression depth of the hole contamination, and the defect quantification degree of the target plugged hole is obtained based on the 2D and 3D image data of the target integrated chip carrier, including: if the defect type of the target plugged hole is hole contamination, the contamination area of ​​the target plugged hole is obtained based on the 2D image data of the target plugged hole, and the contamination area of ​​the target plugged hole is used as the defect quantification degree of the target plugged hole; if the defect type of the target plugged hole is hole bubble, the protrusion height of the target plugged hole is obtained based on the 2D image data of the target plugged hole, and the contamination area of ​​the target plugged hole is used as the defect quantification degree of the target plugged hole. A spatial sphere fitting is performed on the data set to obtain the coordinates of the highest vertex corresponding to the bubble of the target plugged hole, and the protrusion height of the target plugged hole is calculated based on the coordinates of the highest vertex, and the protrusion height of the target plugged hole is used as the defect quantification degree of the target plugged hole; if the defect type of the target plugged hole is hole void and hole depression, a spatial sphere fitting is performed on the protrusion data set of the target plugged hole to obtain the coordinates of the lowest vertex corresponding to the bubble of the target plugged hole, and the depression depth of the target plugged hole is calculated based on the coordinates of the lowest vertex, and the depression depth of the target plugged hole is used as the defect quantification degree of the target plugged hole.

[0013] In an embodiment of the present application, the defect quantification degree corresponding to the target integrated chip carrier plugging hole defect type can be obtained based on the 2D and 3D image data of the target integrated chip carrier, thereby scientifically and accurately reflecting the defect degree of the target integrated chip carrier plugging hole through specific data, thereby improving the recognition accuracy and recognition efficiency of the optical detection system of the integrated chip carrier plugging hole.

[0014] In combination with the first aspect, in a possible embodiment, a quality evaluation result of the plugging hole of the integrated chip carrier is obtained according to the plugging hole defect type and defect quantification degree of the target integrated chip carrier, including: determining the defect degree of all defective plugging holes of the plugging hole carrier according to the defect type and defect quantification degree of the target integrated chip carrier, the defect degree including serious, general and minor defects; obtaining the overall defect ratio of the target integrated chip carrier according to the proportion of defective plugging holes of each defect degree in all plugging holes of the plugging hole carrier; calculating the repeatability and reproducibility of the normal plugging hole depth according to the normal plugging hole depth of the target integrated chip carrier; and performing quality evaluation of the target integrated chip carrier according to the overall defect ratio of the target integrated chip carrier and the repeatability and reproducibility of the plugging hole depth, the lower the overall defect ratio and the higher the repeatability and reproducibility, the higher the quality of the target integrated chip carrier.

[0015] In combination with the first aspect, in a possible embodiment, the repeatability and reproducibility of the plug hole depth are calculated based on the normal plug hole depth of the target plug hole board, including: calculating the normal plug hole depth of the target integrated chip carrier based on the 2D and 3D image data of the target integrated chip carrier, the normal plug hole depth is the plug hole depth of the normal plug hole excluding the defective plug hole, the repeatability of the normal plug hole depth represents the degree of consistency of the normal plug hole depth in different calculation areas of the target integrated chip carrier, and the reproducibility of the plug hole depth represents the degree of consistency of the normal plug hole depth in the same calculation area of ​​different target integrated chip carriers; the normal plug hole depth is divided into multiple calculation areas according to the process processing sequence of the target integrated chip carrier; and the repeatability and reproducibility of the plug hole depth of multiple calculation areas are calculated based on the normal plug hole depth of the target integrated chip carrier.

[0016] In an embodiment of the present application, the overall defect ratio of the target integrated chip carrier is obtained based on the plugging hole defect type and the corresponding defect depth of the target integrated chip carrier, and the quality of the target integrated chip carrier is scientifically and objectively evaluated in combination with the repeatability and reproducibility of the normal plugging hole depth, thereby improving the recognition credibility, accuracy and objectivity of the optical detection system of the plugging hole of the integrated chip carrier.

[0017] In a second aspect, embodiments of the present application provide a device for extracting and evaluating the characteristics of plugged vias on an integrated chip carrier, which is applied to a processor of an optical inspection system for the integrated chip carrier. The optical inspection system for the integrated chip carrier includes multiple scanning cameras and a processor. The device includes:

[0018] Scanning unit: used to scan the target integrated chip carrier board through multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier board;

[0019] Calculation unit: used to obtain the defect type of the target plug hole and the defect quantification degree of the defect type based on the 2D and 3D image data of the target integrated chip carrier;

[0020] Evaluation unit: used for obtaining a quality evaluation result of the plugging hole of the integrated chip carrier according to the plugging hole defect type of the target integrated chip carrier and the defect quantification degree of the defect type.

[0021] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and one or more instructions are suitable for being loaded by the processor and executing part or all of the method of the first aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A schematic diagram of the structure of a plug hole feature extraction and quality evaluation system for an integrated chip carrier provided in an embodiment of the present application;

[0025] Figure 2 A schematic flow chart of a method for extracting plug hole features and evaluating quality of an integrated chip carrier provided in an embodiment of the present application;

[0026] Figure 3 A schematic structural diagram of a scanning camera of an optical inspection system for an integrated chip carrier provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of a dirty communication area of ​​a target plug hole provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the computing area division of an integrated chip carrier provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of the structure of a device for extracting and evaluating plug hole features of an integrated chip carrier provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0033] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] The embodiments of the present application are described below with reference to the accompanying drawings.

[0035] How to achieve accurate summarization and quantitative analysis of plugging defects on integrated chip substrates under the premise of full automation, micron precision, high speed and large coverage is one of the important issues that need to be solved urgently in this field.

[0036] To address the above issues, this application proposes a method and device for capturing and processing 2D and 3D images of PCBs. This method effectively addresses the limited field of view associated with high-precision single-camera measurements, improving the imaging quality of large-format, high-precision measurements. This is described below with reference to the accompanying figures.

[0037] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a plug hole feature extraction and quality evaluation system for an integrated chip carrier provided in an embodiment of the present application, as shown in FIG. Figure 1The system 100 shown includes a scanning camera 101 and a processor 102. The scanning camera 101 is used to scan a target integrated chip carrier, obtain a raw image of the target integrated chip carrier, and send the raw image of the target integrated chip carrier to the processor 102. The processor 102 is used to acquire the raw image of the target integrated chip carrier, obtain 2D image data and 3D image data of the target integrated chip carrier, and calculate and classify the defect type and quantitative data of the target integrated chip carrier based on the 2D image data and 3D image data of the target integrated chip carrier to evaluate the quality of the target integrated chip carrier.

[0038] See Figure 2 , Figure 2 A flow chart of a method for extracting plug hole features and evaluating quality of an integrated chip carrier provided in an embodiment of the present application is shown as follows: Figure 2 As shown, steps S201-S203 are included.

[0039] S201: Scanning a target integrated chip carrier board by multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier board.

[0040] Specifically, see Figure 3 , Figure 3 This is a schematic diagram of the structure of a scanning camera of an optical detection system for an integrated chip carrier provided in an embodiment of the present application. Figure 3 As shown, the target integrated chip carrier is placed in the placement area. The scanning camera can be composed of multiple scanning camera units, each of which includes a scanning camera and a light source assembly. The scanning camera scans the target integrated chip carrier illuminated by the light source assembly to obtain image data of the target integrated chip carrier. The image data obtained by irradiating and scanning with a natural light source is 2D image data, and the image data obtained by irradiating and scanning with a line laser light source is 3D image data. The multiple scanning camera units capture partial 2D image data and 3D image data of the target integrated chip carrier, which are then fused and synthesized to obtain the entire 2D image data and 3D image data of the target integrated chip carrier.

[0041] S202: Obtaining a defect type of a target plugged via and a defect quantification degree of the defect type based on the 2D and 3D image data of the target integrated chip carrier.

[0042] Specifically, the target plugging involves plugging certain vias on an integrated chip carrier board with materials such as resin to prevent tin from penetrating the vias and causing short circuits on the component surface, and to avoid residual flux in the vias. Computational analysis based on 2D and 3D image data of the target integrated chip carrier board can determine the target integrated chip carrier board plugged via defect type and defect quantification level. The defect quantification level here generates target integrated chip carrier board plugged via defect data to indicate the corresponding defect level, such as sink depth or bubble height.

[0043] In a possible embodiment, the defect type of the target plugged hole is obtained based on the 2D and 3D image data of the target integrated chip carrier, including: performing height plane fitting on the plugged hole center 3D image data of the target plugged hole in the target integrated chip carrier to obtain the height plane coefficient of the target plugged hole; obtaining the flatness of the target plugged hole based on the height plane coefficient and the 3D image data of the target integrated chip carrier, the smaller the flatness, the flatter the 3D plane of the corresponding target plugged hole; if the flatness of the target plugged hole is less than a first preset threshold, segmenting the 2D image data of the target plugged hole to obtain a segmented area of ​​the 2D image data of the target plugged hole; obtaining first grayscale information of the segmentation and second grayscale information of the 2D image of the target integrated chip carrier, and calculating a difference value between the first grayscale information and the second grayscale information; if the difference value is greater than the second preset threshold, determining the defect type of the target plugged hole as hole contamination.

[0044] Specifically, based on the center of the target plug hole, a flat theoretical plane can be obtained. Fitting the real 3D image data of the target plug hole to the theoretical plane, obtaining the height plane fitting parameters, that is, the deviation between the actual 3D data of the target plug hole and the theoretical data can be obtained. According to the plane fitting parameters, the errors caused by plate warping, process expansion and contraction, and uneven plate thickness can be eliminated. Flatness represents the flatness of the actual 3D plane of the target plug hole. The smaller the flatness, the flatter the 3D plane of the corresponding target plug hole. If the flatness is greater than the first preset threshold, it means that there are large depressions or convexities in the actual 3D plane of the target plug hole. When the flatness is less than the first preset threshold, it proves that there are no large depressions or convexities in the actual 3D plane of the target plug hole. At this time, only the defect type of dirtiness of the target plug hole is considered. Segment the 2D image data of the target plug hole to obtain the dirty connected area. Please refer to Figure 4 , Figure 4 This is a schematic diagram of a dirty communication area of ​​a target plug hole provided in an embodiment of the present application. Figure 4As shown in the figure, the rectangular area represents the integrated chip carrier plane, the circular area represents the target plugged via area, and the dark area within the circular area represents the dirty interconnected area. The dirty interconnected area is a complete region with a grayscale value difference from the background, obtained based on the 2D image data of the target plugged via. The difference in grayscale value between the dirty interconnected area and the background can be used to determine whether the dirty interconnected area is a dirty area. When the difference in grayscale value between the dirty interconnected area and the background exceeds a second preset threshold, the dirty interconnected area is determined to be a dirty plugged via defect. The first and second preset thresholds can be adjusted based on the specific detection criteria.

[0045] For example, the full-scale 2D / 3D topography of the IC carrier under test is first acquired through a distributed camera 2D+3D system scanning process; in the 3D data, a height plane fitting is performed on the 3D data of the hole center, and the fitting plane is fitted using the least squares plane fitting algorithm. The least squares plane fitting method is as follows: The mathematical expression of the spatial plane can be written as: z = a0x + a1y + a2, for a series of n points {n> = 3, (x i ,y i ,z i ),i=0,1,...,n-1}, just need to make Minimum, where a0, a1, and a2 are the height plane coefficients. Find the values ​​of a0, a1, and a2 coefficients when S is minimized; take the partial derivative of S to get the values ​​of a0, a1, and a2. Substitute the x and y coordinates of the 3D data in the plug hole into the spatial plane equation to get the 3D height fitting value, and then make the difference between the true value and the fitting value to get the data set {z0, z1, ..., z n}, calculate the standard deviation, mode, and range of the set; finally, use the multiple weighting method to set different weights for the three to obtain the flatness of the plugged hole 3D plane. When the flatness of the 3D plane is less than the first preset threshold, perform binary segmentation based on adaptive variance on the plugged hole 2D image, and calculate the cumulative mean M of the gray level K and the global mean MG of the image: Solve The value of K at the maximum value is the desired segmentation threshold. Using the segmentation threshold calculated in step 1, the 2D image within the via is segmented. Then, using the region production method, a point within the segmented region is randomly selected and, using image texture logic, a complete, connected region of contamination is derived. The grayscale information G1 of the connected contamination region and the grayscale information G2 of the contamination-free region within the via are calculated. When |G1-G2| is greater than a second preset threshold, the defect type of the target integrated circuit board via is determined to be contaminated.

[0046] In one possible embodiment, if the flatness of the target plugged hole is greater than a first preset threshold, the method further includes: extracting pixel points that are greater than a first preset number of pixel points from all pixel points of the target plugged hole based on the height plane coefficient and the position coordinates of the extracted pixel points of the target plugged hole in the 3D image data; calculating the difference between the actual height value and the fitted value of all position coordinates of the target plugged hole in the 3D image data to obtain a concave-convex data set of the target plugged hole; recording all values ​​in the concave-convex data set that are greater than a third preset threshold as a convex data set, and recording all values ​​that are less than a fourth preset threshold as a concave data set; if the number of values ​​in the convex data set is greater than the number of values ​​in the concave data set, determining that the defect type of the target plugged hole is a hole bubble.

[0047] Specifically, if the flatness of the target via exceeds a first preset threshold, it indicates that the target via's 3D surface has a concavity or convexity greater than a preset standard. The target via's defect type includes at least one of concavity, bubble, and void. The location coordinates here can be the location coordinates corresponding to each pixel in the target via's 3D image. The number of location coordinates varies depending on the required detection accuracy. The target via's concave-convex data set includes the difference between the height values ​​of the pixel points on the target via's 3D plane and the fitted values, reflecting the degree of undulation in the target via's 3D surface topography. Values ​​in the concave-convex data set that exceed a third preset threshold are designated as the convex data set, while all values ​​that fall below a fourth preset threshold are designated as the concave data set. The third and fourth preset thresholds can be adjusted based on the detection standard and accuracy requirements. If there are more values ​​in the convex data set than in the concave data set, it indicates that the target via's convex defects are greater than its concave defects. In this case, only the convex defects of the target via are considered. The defect type of the target plugging hole is determined to be hole bubbles, which are air bubbles caused by uneven heating during the plugging process.

[0048] In a possible embodiment, if the values ​​in the concave data set exceed the values ​​in the convex data set, the method further includes: performing spatial sphere fitting based on the values ​​in the concave data set to obtain a spatial sphere equation; solving the spatial sphere equation in combination with the 3D data image data of the target plugged hole to obtain a goodness of fit corresponding to the concave data set, and determining whether the concave data set of the target plugged hole satisfies a spherical morphology based on the goodness of fit; segmenting the 2D image data of the target plugged hole to obtain a plane image corresponding to the target plugged hole; performing elliptical feature extraction on the plane image corresponding to the target plugged hole to obtain the major axis and minor axis included in the elliptical feature, and judging the defect type of the target plugged hole based on the ratio of the major axis to the minor axis; if it is determined that the concave data set of the target plugged hole satisfies a spherical morphology and the target plugged hole meets the elliptical feature, then determining that the defect type of the target plugged hole is a hole void; if it is determined that the concave data set of the target plugged hole meets the non-spherical morphology and the target plugged hole does not meet the elliptical feature, then determining that the defect type of the target plugged hole is a hole concave.

[0049] Specifically, when the 3D plane of the target plug hole presents a concave defect, the concave defect includes impurities in the plug hole process, pore voids and hole depressions caused by process drying. The goodness of fit between the target plug hole concave area and the sphere can be obtained by performing spatial sphere fitting based on the 3D data. The goodness of fit refers to the degree of fit of the theoretical equation to the observed value. The statistic that measures the goodness of fit is the coefficient of determination (also known as the coefficient of determination) R 2 . R 2 The maximum value is 1. 2 The closer the value of R is to 1, the better the theoretical equation fits the observed value; on the contrary, 2 The smaller the value of R, the worse the fitting degree of the theoretical equation to the observed value. 2 It measures the overall fit of the regression equation and expresses the overall relationship between the dependent variable and all independent variables. 2 This is equal to the ratio of the regression sum of squares to the total sum of squares, that is, the percentage of the dependent variable's variability that the regression equation can explain. A higher goodness of fit for a hole defect indicates a closer spherical morphology, while a lower goodness of fit indicates a less spherical shape. The concave morphology of a hole void is spherical, while the concave morphology of a hole depression is non-spherical, with significant differences in goodness of fit between the two. Furthermore, the 2D image of a hole void conforms to an elliptical characteristic, while the 2D image of a hole depression does not. A comprehensive analysis of the target plugged hole's 3D and 2D images can be used to determine the defect type of the target plugged hole.

[0050] For example, the height plane coefficient is obtained according to the above embodiment, and the real data in the plug hole is subtracted from the fitting value to obtain the data set {z0, z1, ..., z n}, the statistical set of values ​​greater than the third preset threshold is the protruding data set, recorded as set Z 正If it is less than the fourth preset threshold, it is a concave data set, recorded as set Z 负 When Z 正 >Z 负 When Z 正 <Z 负 When the 3D data is concave, the main direction set is fitted with a space ball according to the convex and concave directions. The space ball equation can be x 2 +y 2 +z 2 -Ax-By-Cz+D=0,solve V=∑(x 2 +y 2 +z 2 -Ax-By-Cz+D) 2 When V is the smallest, the values ​​corresponding to the coefficients A, B, C, and D need to be derived from the above formula to easily obtain the coefficient matrix:

[0051]

[0052] Solving the above matrix equation yields the values ​​of the coefficients A, B, C, and D. Based on the step-by-step spatial sphere equation and the 3D data, the goodness-of-fit of the regression square in the total sum of squares is calculated. Adaptive image segmentation is performed on the 2D image of the target via to extract elliptical features and calculate the ratio of the ellipse's major axis to its minor axis. A ratio of less than 2:1 satisfies the elliptical feature; a ratio greater than 2:1 does not. This ratio can be adjusted based on the required detection accuracy.

[0053] In the embodiments of the present application, it can be seen that a data set of the flatness and concave-convexity of the target integrated chip carrier via plane is obtained based on the 2D and 3D image data of the target integrated chip carrier. Based on the data set of the flatness and concave-convexity of the via plane, it can be accurately determined whether the target via has defects and the type of defects. This improves the recognition accuracy and efficiency of the optical inspection system for integrated chip carrier vias, thereby reducing the manual re-judgment costs in traditional 2D optical inspection systems.

[0054] In a possible embodiment, the defect quantification degree of the target plugged via includes any one of the contamination area, protrusion height, and depression depth of the hole contamination. The defect quantification degree of the target plugged via is obtained based on the 2D and 3D image data of the target integrated chip carrier, including: if the defect type of the target plugged via is hole contamination, the contamination area of ​​the target plugged via is obtained based on the 2D image data of the target plugged via, and the contamination area of ​​the target plugged via is used as the defect quantification degree of the target plugged via; if the defect type of the target plugged via is hole bubble, the protrusion data set of the target plugged via is used to obtain the target plugged via quantification degree of the target plugged via. A spatial sphere fitting is performed on the target plugged hole to obtain the coordinates of the highest vertex corresponding to the bubble of the target plugged hole, and the protrusion height of the target plugged hole is calculated based on the coordinates of the highest vertex, and the protrusion height of the target plugged hole is used as the defect quantification degree of the target plugged hole; if the defect type of the target plugged hole is hole void and hole depression, a spatial sphere fitting is performed on the protrusion data set of the target plugged hole to obtain the coordinates of the lowest vertex corresponding to the bubble of the target plugged hole, and the depression depth of the target plugged hole is calculated based on the coordinates of the lowest vertex, and the depression depth of the target plugged hole is used as the defect quantification degree of the target plugged hole.

[0055] Specifically, different defect types of the target integrated chip substrate plugged vias correspond to different defect quantification data. When the target integrated chip substrate plugged via defect type is hole contamination, the corresponding defect quantification data may be the area of ​​contamination or the percentage of contamination. When the target integrated chip substrate plugged via defect type is hole bubbles, the corresponding defect quantification data may be the height of the highest vertex of the bubbles. When the target integrated chip substrate plugged via defect type is hole depression or hole void, the corresponding defect quantification data may be the depth of the lowest vertex of the hole depression or hole void.

[0056] In an embodiment of the present application, the defect quantification degree corresponding to the target integrated chip carrier plugging hole defect type can be obtained based on the 2D and 3D image data of the target integrated chip carrier, thereby scientifically and accurately reflecting the defect degree of the target integrated chip carrier plugging hole through specific data, thereby improving the recognition accuracy and recognition efficiency of the optical detection system of the integrated chip carrier plugging hole.

[0057] In a possible embodiment, a quality evaluation result of the plugging hole of the integrated chip carrier is obtained according to the plugging hole defect type and defect quantification degree of the target integrated chip carrier, including: determining the defect degree of all defective plugging holes of the plugging hole carrier according to the defect type and defect quantification degree of the target integrated chip carrier, the defect degree including serious, general and minor defects; obtaining the overall defect ratio of the target integrated chip carrier according to the proportion of defective plugging holes of each defect degree in all plugging holes of the plugging hole carrier; calculating the repeatability and reproducibility of the normal plugging hole depth according to the normal plugging hole depth of the target integrated chip carrier; and performing quality evaluation of the target integrated chip carrier according to the overall defect ratio of the target integrated chip carrier and the repeatability and reproducibility of the plugging hole depth, the lower the overall defect ratio and the higher the repeatability and reproducibility, the higher the quality of the target integrated chip carrier.

[0058] Specifically, first obtain the defect types of all plug holes of the target integrated chip carrier. Then, in each defect set, the defects are graded according to their quantification degree, and can be divided into severe, general, mild and other levels. The overall defect ratio of each defect type represents the global percentage data of the total number of plug holes of the current integrated chip carrier for each level of defect. Divide the data into N equal parts according to the distribution relationship, and obtain the distribution of the plug hole depth in each divided area, and express the area as a whole unit in percentage. The same integrated chip carrier can be divided into multiple different calculation areas according to the process processing sequence. The reproducibility of the target integrated chip carrier can be obtained by comparing the average depths of normal plug holes in multiple different calculation areas. The repeatability of the target integrated chip carrier can be obtained by comparing the same calculation areas of different boards. The higher the degree of similarity, the higher the reproducibility and repeatability. Reproducibility and repeatability represent the production process stability of the integrated chip carrier.

[0059] In a possible embodiment, the repeatability and reproducibility of the plug hole depth are calculated based on the normal plug hole depth of the target plug hole board, including: calculating the normal plug hole depth of the target integrated chip carrier based on 2D and 3D image data of the target integrated chip carrier, the normal plug hole depth being the plug hole depth of the normal plug hole excluding the defective plug hole, the repeatability of the normal plug hole depth representing the degree of consistency of the normal plug hole depth in different calculation areas of the target integrated chip carrier, and the reproducibility of the plug hole depth representing the degree of consistency of the normal plug hole depth in the same calculation area of ​​different target integrated chip carriers; dividing the normal plug hole depth into multiple calculation areas according to the process processing sequence of the target integrated chip carrier; and calculating the repeatability and reproducibility of the plug hole depth in multiple calculation areas based on the normal plug hole depth of the target integrated chip carrier.

[0060] Specifically, see Figure 5 , Figure 5A schematic diagram of the calculation area division of an integrated chip carrier provided in an embodiment of the present application; when processing the plug hole of the integrated chip carrier, it is generally processed from top to bottom and from left to right in a calculation area as a unit. Therefore, according to the process processing sequence, the calculation area of ​​the target integrated chip carrier can be divided into Figure 5 The nine regions shown. If the average depth of normal plugged vias in different calculated regions of the same substrate is relatively small, it indicates that the tested integrated chip substrate has high repeatability. If the average depth of normal plugged vias in different calculated regions of the same substrate is relatively small, it indicates that the tested integrated chip substrate has high reproducibility. This indicates that the current process parameters and process equipment settings are good, and the produced integrated chip substrates are highly stable. If the repeatability and reproducibility of the integrated chip substrate are low, it indicates that the current process parameters and electromechanical parameters of the process equipment in the current region are abnormal, and the process parameters in the current region need to be optimized.

[0061] In an embodiment of the present application, the overall defect ratio of the target integrated chip carrier is obtained based on the plugging hole defect type and the corresponding defect depth of the target integrated chip carrier, and the quality of the target integrated chip carrier is scientifically and objectively evaluated in combination with the repeatability and reproducibility of the normal plugging hole depth, thereby improving the recognition credibility, accuracy and objectivity of the optical detection system of the plugging hole of the integrated chip carrier.

[0062] By implementing the method in the embodiment of the present application, it can be seen that multiple scanning cameras are used to scan the target integrated chip carrier to obtain 2D and 3D image data of the target integrated chip carrier. The 2D and 3D image data of the target integrated chip carrier are analyzed and calculated to obtain the plug hole defect type and defect quantification degree of the target sunken chip carrier. The defect quantification degree of the target integrated new chip carrier and the repeatability and reproducibility of the normal plug hole depth are further obtained to evaluate the quality of the plug hole of the integrated chip carrier. This solves the problem of low recognition accuracy due to the limitations of 2D images in traditional 2D automatic optical inspection technology and the cost of manual re-judgment caused by the inability to obtain defect quantification data. It realizes a high-speed and high-coverage 2D+3D feature extraction, automated defect summarization and quantitative analysis method for integrated chip carrier plug holes with micron precision.

[0063] Based on the description of the configuration method embodiment, the present application also provides an integrated chip carrier plug hole feature extraction and quality evaluation device 600, which can be a computer program (including program code) running in a terminal. The integrated chip carrier plug hole feature extraction and quality evaluation device 600 can be executed. Figure 1 、 Figure 2 See the method shown in Figure 6 , Figure 6This is a schematic diagram of the structure of a device for extracting and evaluating the plug hole characteristics of an integrated chip carrier provided in an embodiment of the present application. The device includes:

[0064] Scanning unit 601: Scans the target integrated chip carrier through multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier;

[0065] Calculation unit 602: Obtaining a target plugged via defect type and defect quantification degree based on 2D and 3D image data of the target integrated chip carrier;

[0066] Evaluation unit 603: Obtaining a quality evaluation result of the plugging via of the integrated chip carrier according to the plugging via defect type and defect quantification degree of the target integrated chip carrier.

[0067] It should be noted that the above units (scanning unit 601, calculation unit 602 and evaluation unit 603) are used to execute the relevant steps of the above method. For example, the scanning unit 601 is used to execute the relevant content of step S201, and the calculation unit 602 is used to execute the relevant content of S202.

[0068] In a possible embodiment, in terms of obtaining the defect type of the target plugging hole based on the 2D and 3D image data of the target integrated chip carrier, the calculation unit 602 is further specifically used to: perform height plane fitting on the plugging hole center 3D image data of the target plugging hole in the target integrated chip carrier to obtain a height plane coefficient of the target plugging hole; obtain the flatness of the target plugging hole based on the height plane coefficient and the 3D image data of the target integrated chip carrier, wherein the smaller the flatness, the flatter the 3D plane of the corresponding target plugging hole; if the flatness of the target plugging hole is less than a first preset threshold, segment the 2D image data of the target plugging hole to obtain a segmented area of ​​the 2D image data of the target plugging hole; obtain first grayscale information of the segmentation and second grayscale information of the 2D image of the target integrated chip carrier, and calculate a difference value between the first grayscale information and the second grayscale information; if the difference value is greater than a second preset threshold, determine the defect type of the target plugging hole as hole contamination.

[0069] In a possible embodiment, if the flatness of the target plugged hole is greater than a first preset threshold, the calculation unit 602 is further specifically configured to: extract pixel points that are greater than a first preset number of pixel points from all pixel points of the target plugged hole based on the height plane coefficient and the position coordinates of the extracted pixel points of the target plugged hole in the 3D image data; calculate the difference between the actual height values ​​and the fitted values ​​of all position coordinates of the target plugged hole in the 3D image data to obtain a concave-convex data set of the target plugged hole; record all values ​​in the concave-convex data set that are greater than a third preset threshold as a convex data set, and record all values ​​that are less than a fourth preset threshold as a concave data set; if the number of values ​​in the convex data set is greater than the number of values ​​in the concave data set, determine that the defect type of the target plugged hole is a hole bubble.

[0070] In one possible embodiment, if the values ​​in the concave data set exceed the values ​​in the convex data set, the calculation unit 602 is further specifically configured to: perform spatial sphere fitting based on the values ​​in the concave data set to obtain a spatial sphere equation; solve the spatial sphere equation based on the 3D data image data of the target plugged hole to obtain a goodness of fit corresponding to the concave data set, and determine whether the concave data set of the target plugged hole satisfies a spherical morphology based on the goodness of fit; segment the 2D image data of the target plugged hole to obtain a planar image corresponding to the target plugged hole; perform ellipse feature extraction on the planar image corresponding to the target plugged hole to obtain a major axis and a minor axis included in the ellipse feature, and determine the defect type of the target plugged hole based on the ratio of the major axis to the minor axis; if it is determined that the concave data set of the target plugged hole satisfies a spherical morphology and the target plugged hole meets the ellipse feature, then determine that the defect type of the target plugged hole is a hole void; if it is determined that the concave data set of the target plugged hole meets the non-spherical morphology and the target plugged hole does not meet the ellipse feature, then determine that the defect type of the target plugged hole is a hole concave.

[0071] In a possible embodiment, the defect quantification degree of the target plugged via includes any one of the contamination area, protrusion height, and depression depth of the hole contamination. In terms of obtaining the defect quantification degree of the target plugged via based on the 2D and 3D image data of the target integrated chip carrier, the calculation unit 602 is further specifically configured to: if the defect type of the target plugged via is hole contamination, obtain the contamination area of ​​the target plugged via based on the 2D image data of the target plugged via, and use the contamination area of ​​the target plugged via as the defect quantification degree of the target plugged via; if the defect type of the target plugged via is hole bubble, calculate the target plugged via; A spatial sphere fitting is performed on the protrusion data set of the hole to obtain the highest vertex coordinate corresponding to the bubble of the target plugged hole, and the protrusion height of the target plugged hole is calculated based on the highest vertex coordinate, and the protrusion height of the target plugged hole is used as the defect quantification degree of the target plugged hole; if the defect type of the target plugged hole is hole void and hole depression, a spatial sphere fitting is performed on the protrusion data set of the target plugged hole to obtain the lowest vertex coordinate corresponding to the bubble of the target plugged hole, and the depression depth of the target plugged hole is calculated based on the lowest vertex coordinate, and the depression depth of the target plugged hole is used as the defect quantification degree of the target plugged hole.

[0072] In a possible embodiment, in terms of obtaining a quality evaluation result of the plugging hole of the integrated chip carrier according to the plugging hole defect type and defect quantification degree of the target integrated chip carrier, the evaluation unit 603 is further specifically used to: determine the defect degree of all defective plugging holes of the plugging hole carrier according to the defect type and defect quantification degree of the target integrated chip carrier, the defect degree including serious, general and minor defects; obtain the overall defect ratio of the target integrated chip carrier according to the proportion of defective plugging holes of each defect degree in all plugging holes of the plugging hole carrier; calculate the repeatability and reproducibility of the normal plugging hole depth according to the normal plugging hole depth of the target integrated chip carrier; and perform quality evaluation of the target integrated chip carrier according to the overall defect ratio of the target integrated chip carrier and the repeatability and reproducibility of the plugging hole depth, wherein the lower the overall defect ratio and the higher the repeatability and reproducibility, the higher the quality of the target integrated chip carrier.

[0073] In a possible embodiment, in terms of calculating the repeatability and reproducibility of the plugging hole depth based on the normal plugging hole depth of the target plugging hole board, the evaluation unit 603 is further specifically used to: calculate the normal plugging hole depth of the target integrated chip carrier based on the 2D and 3D image data of the target integrated chip carrier, the normal plugging hole depth being the plugging hole depth of the normal plugging hole excluding the defective plugging hole, the repeatability of the normal plugging hole depth representing the degree of consistency of the normal plugging hole depth in different calculation areas of the target integrated chip carrier, and the reproducibility of the plugging hole depth representing the degree of consistency of the normal plugging hole depth in the same calculation area of ​​different target integrated chip carriers; divide the normal plugging hole depth into multiple calculation areas according to the process processing sequence of the target integrated chip carrier; and calculate the repeatability and reproducibility of the plugging hole depth in multiple calculation areas according to the normal plugging hole depth of the target integrated chip carrier.

[0074] Based on the description of the above method embodiment and device embodiment, please refer to Figure 7 , Figure 7 This is a structural diagram of an electronic device provided in an embodiment of the present application. The electronic device 700 described in this embodiment is as follows: Figure 7As shown, the electronic device 700 includes a processor 701, a memory 702, a communication interface 703, and one or more programs. The processor 701 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above program. The memory 702 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these. The memory 702 can be independent and connected to the processor 701 via a bus. The memory 702 can also be integrated with the processor 701. The communication interface 703 is used to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The one or more programs are stored in the memory in the form of program code and are configured to be executed by the processor. In the embodiment of the present application, the program includes instructions for executing the following steps:

[0075] The target integrated chip carrier is scanned by multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier; the defect type and defect quantification degree of the target plugged hole are obtained based on the 2D and 3D image data of the target integrated chip carrier; and the quality evaluation result of the plugged hole of the integrated chip carrier is obtained based on the plugged hole defect type and defect quantification degree of the target integrated chip carrier.

[0076] In one possible embodiment, height plane fitting is performed on the 3D image data of the plug hole center of the target plug hole in the target integrated chip carrier to obtain the height plane coefficient of the target plug hole; the flatness of the target plug hole is obtained based on the height plane coefficient and the 3D image data of the target integrated chip carrier, and the smaller the flatness, the flatter the 3D plane of the corresponding target plug hole; if the flatness of the target plug hole is less than a first preset threshold, the 2D image data of the target plug hole is segmented to obtain a segmented area of ​​the 2D image data of the target plug hole; first grayscale information of the segmentation and second grayscale information of the 2D image of the target integrated chip carrier are obtained, and a difference value between the first grayscale information and the second grayscale information is calculated; if the difference value is greater than the second preset threshold, the defect type of the target plug hole is determined to be hole dirtiness.

[0077] In one possible embodiment, if the flatness of the target plugged hole is greater than a first preset threshold, the method further includes: extracting pixel points that are greater than a first preset number of pixel points from all pixel points of the target plugged hole based on the height plane coefficient and the position coordinates of the extracted pixel points of the target plugged hole in the 3D image data; calculating the difference between the actual height value and the fitted value of all position coordinates of the target plugged hole in the 3D image data to obtain a concave-convex data set of the target plugged hole; recording all values ​​in the concave-convex data set that are greater than a third preset threshold as a convex data set, and recording all values ​​that are less than a fourth preset threshold as a concave data set; if the number of values ​​in the convex data set is greater than the number of values ​​in the concave data set, determining that the defect type of the target plugged hole is a hole bubble.

[0078] In a possible embodiment, if the values ​​in the concave data set exceed the values ​​in the convex data set, the method further includes: performing spatial sphere fitting based on the values ​​in the concave data set to obtain a spatial sphere equation; solving the spatial sphere equation in combination with the 3D data image data of the target plugged hole to obtain a goodness of fit corresponding to the concave data set, and determining whether the concave data set of the target plugged hole satisfies a spherical morphology based on the goodness of fit; segmenting the 2D image data of the target plugged hole to obtain a plane image corresponding to the target plugged hole; performing elliptical feature extraction on the plane image corresponding to the target plugged hole to obtain the major axis and minor axis included in the elliptical feature, and judging the defect type of the target plugged hole based on the ratio of the major axis to the minor axis; if it is determined that the concave data set of the target plugged hole satisfies a spherical morphology and the target plugged hole meets the elliptical feature, then determining that the defect type of the target plugged hole is a hole void; if it is determined that the concave data set of the target plugged hole meets the non-spherical morphology and the target plugged hole does not meet the elliptical feature, then determining that the defect type of the target plugged hole is a hole concave.

[0079] In a possible embodiment, the defect quantification degree of the target plugged via includes any one of the contamination area, protrusion height, and depression depth of the hole contamination. The defect quantification degree of the target plugged via is obtained based on the 2D and 3D image data of the target integrated chip carrier, including: if the defect type of the target plugged via is hole contamination, the contamination area of ​​the target plugged via is obtained based on the 2D image data of the target plugged via, and the contamination area of ​​the target plugged via is used as the defect quantification degree of the target plugged via; if the defect type of the target plugged via is hole bubble, the protrusion data set of the target plugged via is used to obtain the target plugged via quantification degree of the target plugged via. A spatial sphere fitting is performed on the target plugged hole to obtain the coordinates of the highest vertex corresponding to the bubble of the target plugged hole, and the protrusion height of the target plugged hole is calculated based on the coordinates of the highest vertex, and the protrusion height of the target plugged hole is used as the defect quantification degree of the target plugged hole; if the defect type of the target plugged hole is hole void and hole depression, a spatial sphere fitting is performed on the protrusion data set of the target plugged hole to obtain the coordinates of the lowest vertex corresponding to the bubble of the target plugged hole, and the depression depth of the target plugged hole is calculated based on the coordinates of the lowest vertex, and the depression depth of the target plugged hole is used as the defect quantification degree of the target plugged hole.

[0080] In a possible embodiment, a quality evaluation result of the plugging hole of the integrated chip carrier is obtained according to the plugging hole defect type and defect quantification degree of the target integrated chip carrier, including: determining the defect degree of all defective plugging holes of the plugging hole carrier according to the defect type and defect quantification degree of the target integrated chip carrier, the defect degree including serious, general and minor defects; obtaining the overall defect ratio of the target integrated chip carrier according to the proportion of defective plugging holes of each defect degree in all plugging holes of the plugging hole carrier; calculating the repeatability and reproducibility of the normal plugging hole depth according to the normal plugging hole depth of the target integrated chip carrier; and performing quality evaluation of the target integrated chip carrier according to the overall defect ratio of the target integrated chip carrier and the repeatability and reproducibility of the plugging hole depth, the lower the overall defect ratio and the higher the repeatability and reproducibility, the higher the quality of the target integrated chip carrier.

[0081] In a possible embodiment, the repeatability and reproducibility of the plug hole depth are calculated based on the normal plug hole depth of the target plug hole board, including: calculating the normal plug hole depth of the target integrated chip carrier based on 2D and 3D image data of the target integrated chip carrier, the normal plug hole depth being the plug hole depth of the normal plug hole excluding the defective plug hole, the repeatability of the normal plug hole depth representing the degree of consistency of the normal plug hole depth in different calculation areas of the target integrated chip carrier, and the reproducibility of the plug hole depth representing the degree of consistency of the normal plug hole depth in the same calculation area of ​​different target integrated chip carriers; dividing the normal plug hole depth into multiple calculation areas according to the process processing sequence of the target integrated chip carrier; and calculating the repeatability and reproducibility of the plug hole depth in multiple calculation areas based on the normal plug hole depth of the target integrated chip carrier.

[0082] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0084] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0085] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0086] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0087] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program. The program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0088] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for extracting and evaluating the characteristics of plugged vias in an integrated chip carrier, applied to a processor of an optical inspection system for an integrated chip carrier, wherein the optical inspection system for the integrated chip carrier comprises a plurality of scanning cameras and the processor, characterized in that: The method comprises: Scanning the target integrated chip carrier board by the multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier board; Obtaining a defect type and a defect quantification degree of a target plugged via according to the 2D and 3D image data of the target integrated chip carrier; obtaining the defect type of the target plugged via according to the 2D and 3D image data of the target integrated chip carrier, including: performing height plane fitting on the plugged via center 3D image data of the target plugged via in the target integrated chip carrier to obtain a height plane coefficient of the target plugged via; obtaining flatness of the target plugged via according to the height plane coefficient and the 3D image data of the target integrated chip carrier, wherein a smaller flatness corresponds to a flatter 3D plane of the target plugged via; if the flatness of the target plugged via is less than a first preset threshold, segmenting the 2D image data of the target plugged via to obtain segmented regions of the 2D image data of the target plugged via; obtaining first grayscale information of the segmentation and second grayscale information of the 2D image of the target integrated chip carrier, and calculating a difference value between the first grayscale information and the second grayscale information; if the difference value is greater than a second preset threshold, determining the defect type of the target plugged via as hole contamination; A quality evaluation result of the plugging hole of the integrated chip carrier is obtained according to the plugging hole defect type of the target integrated chip carrier and the defect quantification degree of the defect type.

2. The method according to claim 1, characterized in that If the flatness of the target plug hole is greater than a first preset threshold, the method further includes: According to the height plane coefficient and the position coordinates of the extraction pixel points of the target plugging hole in the 3D image data, the extraction pixel points are pixel points greater than a first preset number among all the pixel points of the target plugging hole; Calculating the difference between the actual height value and the fitted value of all position coordinates of the target plug hole in the 3D image data to obtain a concave-convex data set of the target plug hole; Recording all values ​​in the concave-convex data set that are greater than a third preset threshold as a convex data set, and recording all values ​​that are less than a fourth preset threshold as a concave data set; If the value in the protrusion data set is greater than the value in the depression data set, it is determined that the defect type of the target plugged via is a via bubble.

3. The method according to claim 2, characterized in that If the value in the concave data set exceeds the value in the convex data set, the method further includes: Performing spatial sphere fitting according to the values ​​in the concave data set to obtain a spatial sphere equation; Solving the spatial sphere equation based on the 3D image data of the target plug hole to obtain a goodness of fit corresponding to the recessed data set, and determining whether the recessed data set of the target plug hole satisfies a spherical morphology based on the goodness of fit; Segmenting the 2D image data of the target plug hole to obtain a planar image corresponding to the target plug hole; Extracting elliptical features from a plane image corresponding to the target plugged hole to obtain a major axis and a minor axis included in the elliptical features, and determining a defect type of the target plugged hole based on a ratio of the major axis to the minor axis; If it is determined that the concave data set of the target plug hole satisfies a spherical morphology and the target plug hole conforms to an elliptical feature, then the defect type of the target plug hole is determined to be a hole void; If it is determined that the depression data set of the target plug hole satisfies a non-spherical morphology and the target plug hole does not conform to an elliptical feature, then the defect type of the target plug hole is determined to be a hole depression.

4. The method according to claim 2 or 3, characterized in that The target plugged via defect quantification degree includes any one of the contamination area, protrusion height, and concave depth of the hole contamination. The quantification degree of the target plugged via defect is obtained based on the 2D and 3D image data of the target integrated chip carrier, including: If the defect type of the target plugged via is hole contamination, obtaining the contamination area of ​​the target plugged via according to the 2D image data of the target plugged via, and using the contamination area of ​​the target plugged via as the quantified degree of the defect of the target plugged via; If the defect type of the target plugged via is a bubble, a spatial sphere fitting is performed on the protrusion data set of the target plugged via to obtain the coordinates of the highest vertex corresponding to the bubble of the target plugged via. The protrusion height of the target plugged via is calculated based on the coordinates of the highest vertex, and the protrusion height of the target plugged via is used as the quantified degree of the defect of the target plugged via. If the defect type of the target plugged hole is hole void and hole depression, a spatial sphere fitting is performed on the protrusion data set of the target plugged hole to obtain the lowest vertex coordinates corresponding to the bubble of the target plugged hole, and the depression depth of the target plugged hole is calculated based on the lowest vertex coordinates. The depression depth of the target plugged hole is used as the quantitative degree of the defect of the target plugged hole.

5. The method according to any one of claims 1 to 3, characterized in that The step of obtaining a quality evaluation result of the plugging via of the integrated chip carrier board according to the plugging via defect type of the target integrated chip carrier board and the defect quantification degree of the defect type includes: Determining defect levels of all defective plugged vias of the target integrated chip carrier board according to defect types and defect quantification levels of the target integrated chip carrier board, wherein the defect levels include severe, general, and minor defects; Obtaining an overall defect ratio of the target integrated chip carrier board according to a ratio of defective plugged vias of each defect level among all the defective plugged vias in the target integrated chip carrier board; Calculating the repeatability and reproducibility of the normal plugging hole depth according to the normal plugging hole depth of the target integrated chip carrier; The quality of the target integrated chip carrier is evaluated according to the overall defect ratio of the target integrated chip carrier and the repeatability and reproducibility of the plug hole depth. The lower the overall defect ratio and the higher the repeatability and reproducibility, the higher the quality of the target integrated chip carrier.

6. The method according to claim 5, characterized in that The method of calculating the repeatability and reproducibility of the plug hole depth based on the normal plug hole depth of the target integrated chip carrier includes: Calculating the depth of a normal plugged via of the target integrated chip carrier based on the 2D and 3D image data of the target integrated chip carrier, wherein the normal plugged via depth is the plugged via depth of a normal plugged via excluding the defective plugged via, the repeatability of the normal plugged via depth represents the degree of consistency of the normal plugged via depth in different calculated regions of the target integrated chip carrier, and the reproducibility of the plugged via depth represents the degree of consistency of the normal plugged via depth in the same calculated region of different target integrated chip carriers; Dividing the depth of the normal plug hole into a plurality of calculation areas according to the process sequence of the target integrated chip carrier; The repeatability and reproducibility of the plug hole depths of the plurality of calculation areas are calculated according to the depths of the normal plug holes of the target integrated chip carrier.

7. An integrated chip carrier plug hole feature extraction and quality evaluation device, applied to a processor of an optical inspection system of an integrated chip carrier, the optical inspection system of the integrated chip carrier comprising a plurality of scanning cameras and the processor, characterized in that: The device comprises: Scanning unit: scanning the target integrated chip carrier board through the multiple scanning cameras to obtain 2D and 3D image data of the target integrated chip carrier board; a calculation unit: obtaining a defect type and a defect quantification degree of a target plugged via based on the 2D and 3D image data of the target integrated chip carrier; obtaining the defect type of the target plugged via based on the 2D and 3D image data of the target integrated chip carrier, comprising: performing height plane fitting on the plugged via center 3D image data of the target plugged via in the target integrated chip carrier to obtain a height plane coefficient of the target plugged via; obtaining a flatness of the target plugged via based on the height plane coefficient and the 3D image data of the target integrated chip carrier, wherein a smaller flatness indicates a flatter 3D plane of the target plugged via; if the flatness of the target plugged via is less than a first preset threshold, segmenting the 2D image data of the target plugged via to obtain segmented regions of the 2D image data of the target plugged via; obtaining first grayscale information of the segmentation and second grayscale information of the 2D image of the target integrated chip carrier, and calculating a difference between the first grayscale information and the second grayscale information; if the difference is greater than a second preset threshold, determining the defect type of the target plugged via as hole contamination; An evaluation unit is configured to obtain a quality evaluation result of the plugging hole of the integrated chip carrier according to the plugging hole defect type of the target integrated chip carrier and the defect quantification degree of the defect type.

8. An electronic device, characterized in that: The method comprises a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for executing the steps in the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute the method according to any one of claims 1 to 6.

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