Test circuit, test system and test method

Abstract

A test circuit, a test system and a test method, the test circuit comprising: a test frequency generating unit adapted to generate a test clock signal with a corresponding test frequency under the control of a corresponding control signal; a frequency dividing processing unit adapted to perform frequency dividing processing on data output frequencies of a dynamic D flip-flop and a static D flip-flop under the control of the test clock signal, to obtain a corresponding test data output frequency and a reference data output frequency; a test machine adapted to compare the test data output frequency and the reference data output frequency; when it is determined that the test data output frequency and the reference data output frequency are consistent, a corresponding control signal is generated and sent to the test frequency generating unit, until the test data output frequency and the reference data output frequency are inconsistent, a corresponding test result is obtained. The above scheme can realize online automatic testing of a dynamic D flip-flop and improve test efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a test circuit, a test system and a test method. BACKGROUND

[0002] In addition to its own input signal, the D flip-flop also has a clock signal line, through the change of the clock signal, the next state of the flip-flop only depends on the state of the input signal at the time when the clock signal falling edge (or rising edge) arrives, so as to enhance the interference ability, therefore, the D flip-flop is also called edge-triggered flip-flop.

[0003] The D flip-flop can be divided into two categories: static D flip-flop and dynamic D flip-flop. Among them, the dynamic D flip-flop, compared with the static D flip-flop, due to the reduction of the positive feedback circuit for maintaining the working state, the circuit structure will be greatly simplified, which not only reduces the chip area, but also reduces the power consumption.

[0004] However, unlike the static D flip-flop with signal latching function, the dynamic D flip-flop only stores signals through capacitors, due to the inherent leakage of internal transistors, at a lower working frequency, it is easy to lose signals. Therefore, how to realize the online automatic test of the minimum working frequency of the dynamic D flip-flop becomes a problem to be solved. SUMMARY

[0005] The problem solved by the present application is to provide a test circuit to realize the online automatic test of the dynamic D flip-flop.

[0006] To solve the above problems, the present application provides a test circuit, comprising a test frequency generating unit, a frequency dividing processing unit and a test machine;

[0007] The test frequency generating unit is coupled with the test machine at the control end and coupled with the dynamic D flip-flop and the static D flip-flop at the output end, and is adapted to generate a test clock signal with a corresponding test frequency under the control of a corresponding control signal and transmit it to the dynamic D flip-flop and the static D flip-flop;

[0008] The frequency dividing processing unit is coupled with the dynamic D flip-flop and the static D flip-flop at the input end, respectively, and is adapted to frequency-divide the data output frequency of the dynamic D flip-flop and the static D flip-flop under the control of the test clock signal, respectively, to obtain the corresponding test data output frequency and the reference data output frequency;

[0009] The test machine is coupled with the frequency division processing unit at the input end and is adapted to compare the test data output frequency with the reference data output frequency; when it is determined that the test data output frequency is consistent with the reference data output frequency, a corresponding control signal is generated and sent to the test frequency generating unit, so that the test frequency generating unit adjusts the test frequency of the test clock signal according to a preset frequency reduction step, until the test data output frequency is inconsistent with the reference data output frequency, and a corresponding test result is obtained.

[0010] Optionally, the test frequency generating unit comprises a frequency adjustment voltage source, a ring oscillator, a clock signal buffer and a first frequency divider.

[0011] The frequency adjustment voltage source has a control end as or coupled with the control end of the test frequency generating unit, and an output end coupled with the ring oscillator, and is adapted to adjust the control voltage output by itself according to a preset voltage reduction step when receiving the voltage control signal sent by the test machine.

[0012] The ring oscillator has a voltage input end coupled with the output end of the frequency adjustment voltage source, an input end coupled with an output end, and an output end coupled with the clock buffer, and is adapted to generate a clock signal with a corresponding clock frequency based on the received control voltage.

[0013] The clock buffer has an input end coupled with the ring oscillator and an output end coupled with the first frequency divider, and is adapted to buffer the clock signal and output the buffered clock signal to the first frequency divider.

[0014] The first frequency divider has an input end coupled with the clock buffer and an output end as or coupled with the output end of the test frequency generating unit, and is adapted to divide the buffered clock signal to generate the test clock signal.

[0015] Optionally, the ring oscillator comprises a plurality of first inverters connected in series.

[0016] Optionally, the number of the plurality of first inverters connected in series is odd.

[0017] Optionally, the clock buffer comprises a plurality of second inverters connected in series.

[0018] Optionally, the number of the plurality of second inverters connected in series is even.

[0019] Optionally, the first frequency divider comprises a first D flip-flop.

[0020] The data input end of the first D flip-flop is coupled with the data inverting output end of the first D flip-flop, the clock input end of the first D flip-flop is the input end of the first frequency divider or is coupled with the input end of the first frequency divider, and the data inverting output end of the first D flip-flop is the output end of the first frequency divider or is coupled with the output end of the first frequency divider.

[0021] Optionally, the first frequency divider comprises a second D flip-flop and a third inverter.

[0022] The data input end of the second D flip-flop is coupled with the output end of the third inverter, the clock input end of the second D flip-flop is the input end of the first frequency divider or is coupled with the input end of the first frequency divider, the data output end of the second D flip-flop is coupled with the input end of the third inverter, and the output end of the third inverter is the output end of the first frequency divider or is coupled with the output end of the first frequency divider.

[0023] Optionally, the frequency processing unit comprises a plurality of frequency processing modules connected in series.

[0024] The data input end of each frequency processing module is coupled with the data inverting output end, the clock input end of each frequency processing module is coupled with the data inverting output end of the previous frequency processing module, and the data inverting output end of each frequency processing module is further coupled with the clock input end of the next frequency processing module.

[0025] Optionally, the frequency processing module comprises a third D flip-flop.

[0026] The data input end of the third D flip-flop is the data input end of the frequency processing module or is coupled with the data input end of the frequency processing module, the clock input end of the third D flip-flop is the clock input end of the frequency processing module or is coupled with the clock input end of the frequency processing module, and the data inverting output end of the third D flip-flop is the data inverting output end of the frequency processing module or is coupled with the data inverting output end of the frequency processing module.

[0027] Optionally, the frequency processing module comprises a fourth D flip-flop and a fourth inverter.

[0028] The data input end of the fourth D flip-flop is coupled to or serves as the data input end of the frequency division processing module, the clock input end of the fourth D flip-flop is coupled to or serves as the clock input end of the frequency division processing module, the data output end of the fourth D flip-flop is coupled to the input end of the fourth inverter, and the output end of the fourth inverter serves as or is coupled to the data inverse output end of the frequency division processing module.

[0029] Optionally, the number of stages of the frequency division processing module is 5 to 15.

[0030] Optionally, the plurality of dynamic D flip-flops to be tested further comprise:

[0031] The multiplexer has a control end coupled to the test machine, an input end coupled to the output ends of the plurality of dynamic D flip-flops to be tested, and an output end coupled to the input end of the frequency division processing unit, and is adapted to couple the output end of the corresponding dynamic D flip-flop to be tested or the static D flip-flop to the input end of the frequency division processing unit when receiving a read selection signal sent by the test machine.

[0032] Correspondingly, the embodiment of the present application further provides a test system comprising the test circuit according to any one of the above.

[0033] Correspondingly, the embodiment of the present application further provides a test method comprising:

[0034] The test frequency generation unit generates a test clock signal with a corresponding test frequency under the control of a corresponding control signal and transmits the test clock signal to the dynamic D flip-flop to be tested and the static D flip-flop;

[0035] The frequency division processing unit acquires the data output frequency of the dynamic D flip-flop to be tested and the static D flip-flop under the control of the test clock signal and performs frequency division processing to obtain a corresponding test data output frequency and a reference data output frequency;

[0036] The test machine compares the test data output frequency and the reference data output frequency; when it is determined that the test data output frequency and the reference data output frequency are consistent, a corresponding control signal is generated and sent to the test frequency generation unit, so that the test frequency generation unit adjusts the clock frequency of the test clock signal according to a preset frequency reduction step, and the test result is obtained until the test data output frequency and the reference data output frequency are inconsistent.

[0037] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0038] A test circuit includes: a test frequency generating unit, adapted to generate a test clock signal having a corresponding test frequency under the control of a corresponding control signal and transmit the signal to a dynamic D flip-flop under test and a static D flip-flop; a frequency division processing unit, adapted to divide the data output frequency of the dynamic D flip-flop under the control of the test clock signal and the data output frequency of the static D flip-flop under the control of the test clock signal to obtain corresponding test data output frequencies and reference data output frequencies; a test machine, adapted to compare the test data output frequency with the reference data output frequency; and when it is determined that the test data output frequency and the reference data output frequency are consistent, generating a corresponding control signal and transmitting it to the test frequency generating unit, so that the test frequency generating unit adjusts the test frequency of the test clock signal according to a preset frequency reduction step until the test data output frequency and the reference data output frequency are inconsistent, thereby obtaining a corresponding test result. The test circuit in the embodiment of the present invention, due to the configuration of the test frequency generating unit, the frequency division processing unit, and the test machine, can realize online automated testing of the dynamic D flip-flop under test, thereby improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the framework structure of a test circuit in an embodiment of the present invention is shown;

[0040] Figure 2 A schematic diagram of the circuit structure of a test frequency generating unit in an embodiment of the present invention is shown;

[0041] Figure 3 A schematic diagram of the circuit structure of a ring oscillator in an embodiment of the present invention is shown;

[0042] Figure 4 A schematic diagram of the circuit structure of a clock buffer in an embodiment of the present invention is shown;

[0043] Figure 5 A schematic diagram of the circuit structure of a first frequency divider in an embodiment of the present invention is shown;

[0044] Figure 6 shows a schematic circuit structure diagram of another first frequency divider in an embodiment of the present invention;

[0045] Figure 7 A schematic structural diagram of a frequency division processing unit in an embodiment of the present invention is shown;

[0046] Figure 8 A schematic structural diagram of another frequency division processing module in an embodiment of the present invention is shown;

[0047] Figure 9A flow chart of a test method in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] As known from the background, a dynamic D flip-flop only stores signals through a capacitor, and due to inherent leakage of internal transistors, the signals are easily lost at a low working frequency. Therefore, how to realize online automatic testing of the dynamic D flip-flop becomes a problem to be solved.

[0049] To solve the above problems, an embodiment of the present application provides a test circuit, which comprises: a test frequency generating unit adapted to generate a test clock signal with a corresponding test frequency under the control of a corresponding control signal and transmit the test clock signal to a dynamic D flip-flop to be tested and a static D flip-flop; a frequency dividing processing unit adapted to perform frequency dividing processing on data output frequencies of the dynamic D flip-flop to be tested and the static D flip-flop under the control of the test clock signal, respectively, to obtain corresponding test data output frequencies and reference data output frequencies; a test machine adapted to compare the test data output frequencies and the reference data output frequencies; when it is determined that the test data output frequencies and the reference data output frequencies are consistent, corresponding control signals are generated and sent to the test frequency generating unit, so that the test frequency generating unit adjusts the test frequency of the test clock signal according to a preset frequency reduction step, and when the test data output frequencies and the reference data output frequencies are inconsistent, corresponding test results are obtained. Due to the settings of the test frequency generating unit, the frequency dividing processing unit and the test machine, online automatic testing of the dynamic D flip-flop to be tested can be realized, and the testing efficiency is improved.

[0050] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 A framework structure schematic diagram of a test circuit in an embodiment of the present application is shown. Referring to Figure 1 The test circuit in an embodiment of the present application can specifically comprise a test frequency generating unit 10, a frequency dividing processing unit 20 and a test machine 30. Among them:

[0052] The test frequency generating unit 10 has a control end and an output end. The control end of the test frequency generating unit 10 is coupled with the test machine 30, and the output end of the test frequency generating unit 10 is coupled with the dynamic D flip-flop to be tested and the static D flip-flop. The test frequency generating unit 10 can generate a test clock signal with a corresponding test frequency under the control of a corresponding control signal and transmit the test clock signal to the dynamic D flip-flop to be tested and the static D flip-flop.

[0053] The frequency division processing unit 20 has an input end and an output end. The input end of the frequency division processing unit 20 is coupled with the dynamic D flip-flop to be tested and the static D flip-flop respectively, and the output end of the frequency division processing unit 20 is coupled with the test machine 30. The frequency division processing unit 20 can perform frequency division processing on the data output frequency of the dynamic D flip-flop to be tested and the static D flip-flop under the control of the test clock signal respectively, to obtain corresponding test data output frequency and reference data output frequency. The test data output frequency is obtained by performing frequency division processing on the data output frequency of the dynamic D flip-flop to be tested under the control of the test clock signal, and the reference data output frequency is obtained by performing frequency division processing on the data output frequency of the static D flip-flop under the control of the test clock signal.

[0054] The test machine 30 has an input end and a control signal output end. The input end of the test machine 30 is coupled with the frequency division processing unit 20, and the control signal output end of the test machine 30 is coupled with the test frequency generation unit 10. The test machine 30 can compare the test data output frequency and the reference data output frequency; when it is determined that the test data output frequency and the reference data output frequency are consistent, the corresponding control signal is generated and sent to the test frequency generation unit 10, and until the test data output frequency and the reference data output frequency are inconsistent, the corresponding test result is obtained.

[0055] Figure 2 The circuit structure schematic diagram of the test frequency generation unit in the embodiment of the application is shown. Please refer to Figure 2 The test frequency generation unit includes a frequency adjustment voltage source 101, a ring oscillator 102, a clock signal buffer 103 and a first frequency divider 104 which are coupled in sequence. Wherein:

[0056] The frequency adjustment voltage source 101 has a control end and an output end. The control end of the frequency adjustment voltage source 101 is used as the control end of the test frequency generation unit or is coupled with the control end of the test frequency generation unit, and the output end of the frequency adjustment voltage source 101 is coupled with the ring oscillator 102. The frequency adjustment voltage source 101 can adjust the control voltage output by itself according to the preset voltage reduction step when receiving the voltage control signal sent by the test machine.

[0057] The ring oscillator 102 has a voltage input end, an input end and an output end. The voltage input end of the ring oscillator 102 is coupled with the output end of the frequency adjusting voltage source 101, the input end of the ring oscillator 102 is coupled with the output end of the ring oscillator 102, and the output end of the ring oscillator 102 is further coupled with the clock buffer 103. The ring oscillator 102 can generate a clock signal with a corresponding clock frequency based on the received control voltage.

[0058] Specifically, the control voltage of the ring oscillator 102 is positively correlated with the clock frequency of the clock signal. In other words, the greater the control voltage of the ring oscillator 102, the higher the clock frequency of the corresponding clock signal; on the contrary, the smaller the control voltage of the ring oscillator 102, the lower the clock frequency of the corresponding clock signal. By adjusting the control voltage, the clock frequency of the clock signal output by the ring oscillator 102 can be adjusted.

[0059] Figure 3 The circuit structure schematic diagram of the ring oscillator in the embodiment of the present application is shown. Please refer to Figure 3 , the ring oscillator includes a plurality of first inverters 102a connected in series. Among them, the control voltage received by the ring oscillator is also the power voltage loaded on each first inverter 102a. The greater the power voltage loaded on the first inverter 102a, the shorter the delay time of the first inverter 102a, so that the clock frequency of the clock signal output by the ring oscillator is higher; on the contrary, the clock frequency of the clock signal output by the ring oscillator is lower.

[0060] The number of first inverters 102a included in the ring oscillator can be set according to actual needs. In the embodiment, the number of first inverters 102a in the ring oscillator is odd. In other words, the input data of the input end of the ring oscillator and the output data of the output end are inverted. In other embodiments, the number of first inverters 102a included in the ring oscillator can also be even, which can be selected by those skilled in the art according to actual needs, which is not limited herein.

[0061] In other embodiments, the ring oscillator can also be implemented by other structures with the same function, which is not limited herein.

[0062] Please continue to refer to Figure 2The clock buffer 103 has an input end and an output end. The input end of the clock buffer 103 is coupled with the ring oscillator 102, and the output end of the clock buffer 103 is coupled with the first frequency divider 104. The clock buffer 103 can buffer the clock signal and output the buffered clock signal to the first frequency divider 104.

[0063] Figure 4 A circuit structure schematic diagram of a clock buffer in an embodiment of the present application is shown. Please refer to Figure 4 The clock buffer includes a plurality of second inverters 103a connected in series. In other embodiments, the clock buffer can also be implemented by other structures with the same function, which is not limited herein.

[0064] The number of the second inverters 103a included in the clock buffer can be set according to actual needs. In the embodiment, the number of the second inverters 103a is even. Specifically, the number of the second inverters 103a is two. Accordingly, the clock signal input by the clock buffer and the buffered clock signal output by the clock buffer are in phase, that is, the buffered clock signal output by the clock buffer has a delay time of several periods from the clock signal input by the clock buffer.

[0065] Please continue to refer to Figure 2 The first frequency divider 104 has an input end and an output end. The input end of the first frequency divider 104 is coupled with the clock buffer 103, and the output end of the first frequency divider 104 is the output end of the test frequency generation unit or is coupled with the output end of the test frequency generation unit. The first frequency divider 104 can perform frequency division processing on the buffered clock signal to generate the test clock signal, so that the test clock signal is within the range of the working clock signal of the dynamic D flip-flop and the static D flip-flop to be tested.

[0066] In a specific implementation, the frequency division coefficient of the first frequency divider is related to the clock frequency of the buffered clock signal and the clock signal frequency of the working clock signal of the dynamic D flip-flop and the static D flip-flop to be tested.

[0067] Figure 5 A circuit structure schematic diagram of a first frequency divider in an embodiment of the present application is shown. Please refer to Figure 5The first frequency divider comprises a first D flip-flop 104a. The first D flip-flop 104a has a data input end D, a clock input end CLK, a data output end Q and a data inverse output end QB. The data input end D of the first D flip-flop 104a is coupled with the data inverse output end QB of the first D flip-flop 104a, the clock input end CLK of the first D flip-flop 104a is an input end of the first frequency divider or is coupled with the input end of the first frequency divider, and the data inverse output end QB of the first D flip-flop 104a is an output end of the first frequency divider or is coupled with the output end of the first frequency divider.

[0068] In other embodiments, the first frequency divider can also be implemented by other structures with the same function. Please refer to Figure 6 In another embodiment of the present application, the first frequency divider can comprise a second D flip-flop 601 and a third inverter 602. The second D flip-flop 601 has a data input end D, a clock input end CLK and a data output end Q. The data input end D of the second D flip-flop 601 is coupled with the output end of the third inverter 602, the clock input end CLK of the second D flip-flop 601 is an input end of the first frequency divider or is coupled with the input end of the first frequency divider, the data output end Q of the second D flip-flop 601 is coupled with the input end of the third inverter 602, and the output end of the third inverter 602 is an output end of the first frequency divider or is coupled with the output end of the first frequency divider.

[0069] Figure 7 A structure schematic diagram of a frequency division processing unit in an embodiment of the present application is shown. Please refer to Figure 7 The frequency division processing unit comprises a plurality of frequency division processing modules 701 connected in series. Each frequency division processing module 701 has a data input end D, a clock input end CLK, a data output end Q and a data inverse output end QB. The data input end D of each frequency division processing module 701 is coupled with the data inverse output end QB, the clock input end CLK of each frequency division processing module 701 is coupled with the data inverse output end QB of the previous frequency division processing module 701, and the data inverse output end QB of each frequency division processing module 701 is coupled with the clock input end CLK of the next frequency division processing module 701.

[0070] In a specific implementation, the number of the frequency division processing modules 701 can be set according to actual needs. For example, the number of the frequency division processing modules can be set to 5-15, etc. Those skilled in the art can select according to actual needs, which is not limited herein.

[0071] In this embodiment, the frequency division processing module 701 comprises a third D flip-flop. The third D flip-flop has a data input end, a clock input end, a data output end and a data inverse output end. The data input end of the third D flip-flop is coupled to or serves as the data input end D of the frequency division processing module 701, the clock input end of the third D flip-flop is coupled to or serves as the clock input end CLK of the frequency division processing module, and the data inverse output end of the third D flip-flop is coupled to or serves as the data inverse output end QB of the frequency division processing module.

[0072] In other embodiments, the frequency division processing module 701 can also be implemented by other structures with the same function. Please refer to Figure 8 In another embodiment of the present application, the frequency division processing module comprises a fourth D flip-flop 801 and a fourth inverter 802. The fourth D flip-flop 801 has a data input end, a clock input end and a data output end. The data input end of the fourth D flip-flop 801 is coupled to or serves as the data input end D of the frequency division processing module, the clock input end of the fourth D flip-flop 801 is coupled to or serves as the clock input end CLK of the frequency division processing module, the data output end of the fourth D flip-flop 801 is coupled to the input end of the fourth inverter 802, and the output end of the fourth inverter 802 is coupled to or serves as the data inverse output end QB of the frequency division processing module.

[0073] Please continue to refer to Figure 1 In this embodiment, in order to improve the test efficiency, the number of the dynamic D flip-flops to be tested can be multiple; and the test circuit further comprises a multiplexer 15. The multiplexer 15 has a control end, an input end and an output end. The control end of the multiplexer 15 is coupled to the test machine 30, the input end of the multiplexer 15 is coupled to the output ends of the multiple dynamic D flip-flops to be tested, and the output end of the multiplexer 15 is coupled to the input end of the frequency division processing unit 20. When receiving the reading selection signal sent by the test machine 30, the multiplexer 15 can couple the output end of the corresponding dynamic D flip-flop or static D flip-flop to be tested to the input end of the frequency division processing unit 20.

[0074] The working principle of the test circuit in the embodiment of the present application will be described below.

[0075] Please refer to Figures 1 to 8When testing the dynamic D flip-flop to be tested, the test machine 30 first outputs a corresponding control signal to the test frequency generating unit 10, so that the test frequency generating unit 10 generates a clock signal with a corresponding clock frequency.

[0076] Specifically, upon receiving the control signal, the frequency adjustment voltage source 101 generates a corresponding control voltage and outputs it to the ring oscillator 102. Upon receiving the control voltage output by the frequency adjustment voltage source 101, the ring oscillator 102 generates a clock signal having a corresponding test frequency based on the received control voltage and outputs it to the clock buffer 103. Upon receiving the clock signal, the clock buffer 103 comprises a plurality of second inverters 103a connected in series therein, which buffer the clock signal to shape and delay the clock signal. Upon receiving the buffered clock signal, the first frequency divider 104 divides the buffered clock signal so that the resulting test clock signal has a clock frequency within the operating clock frequency range of the dynamic D flip-flop and static D flip-flop to be tested.

[0077] The generated test clock signal is transmitted to the dynamic D flip-flop and the static D flip-flop to be tested respectively, so as to trigger the dynamic D flip-flop and the static D flip-flop to be tested to work and generate corresponding output data.

[0078] The frequency division processing unit 20 performs frequency division processing on the data output frequencies of the dynamic D flip-flop and the static D flip-flop to be tested under the control of the test clock signal, respectively, and obtains the corresponding test data output frequency and reference data output frequency, respectively, so that the test data output frequency and the reference data output frequency are within the measuring range of the test machine 30.

[0079] The test machine 30 compares the test data output frequency and the reference data output frequency upon receiving the test data output frequency and the reference data output frequency. When it is determined that the test data output frequency and the reference data output frequency are consistent, it indicates that the dynamic D flip-flop under test is in a normal working state. At this time, the test machine 30 generates a corresponding control signal and sends it to the frequency adjustment voltage source 101 of the test frequency generation unit 10, so that the frequency adjustment voltage source 101 adjusts the generated control voltage according to a preset step-down step, so that the clock frequency of the clock signal output by the ring oscillator 102 and the clock frequency of the buffered clock signal output by the clock buffer 103 are lowered, and then the clock frequency of the test clock signal output by the first frequency divider 104 is gradually lowered. This cycle continues until the test data output frequency and the reference data output frequency are inconsistent, indicating that the dynamic D flip-flop under test is abnormal. At this time, the test clock frequency of the previous test clock signal can be output as the lowest working frequency of the dynamic D flip-flop under test, that is, the corresponding test result is obtained.

[0080] It should be noted that in order to improve work efficiency, a plurality of dynamic D flip-flops under test and static D flip-flops are coupled with the frequency division processing unit 20 through the multiplexer 15. Specifically, the plurality of dynamic D flip-flops under test and static D flip-flops are respectively coupled with a plurality of input address pins of the multiplexer 15. When it is necessary to obtain the test data output frequency and the reference data output frequency of the dynamic D flip-flop under test or the static D flip-flop corresponding to the corresponding address of the multiplexer 15, the test machine 30 can send a corresponding read selection signal to the multiplexer 15, and the read selection signal carries address information of the dynamic D flip-flop under test or the static D flip-flop. When the multiplexer 15 receives the read selection signal, the output end of the corresponding dynamic D flip-flop under test or static D flip-flop is coupled with the input end of the frequency division processing unit 20 according to the address information of the dynamic D flip-flop under test or the static D flip-flop carried in the read selection signal, so as to obtain the information of the test data output frequency of the corresponding dynamic D flip-flop under test or the reference data output frequency of the static D flip-flop through the frequency division processing unit 20.

[0081] Correspondingly, the embodiment of the application also provides a test system comprising the test circuit as described. Wherein, the test circuit please refer to the introduction of the foregoing part, no longer tedious.

[0082] Correspondingly, the embodiment of the application also provides a test method.

[0083] Figure 9 A flow chart of a test method in the embodiment of the application is shown. Please refer toFigure 9 The test method can specifically include the following steps:

[0084] Step S901: A test frequency generation unit generates a test clock signal with a corresponding test frequency under the control of a corresponding control signal and transmits the test clock signal to a dynamic D flip-flop and a static D flip-flop to be tested;

[0085] Step S902: A frequency division processing unit acquires a data output frequency of the dynamic D flip-flop and the static D flip-flop to be tested under the control of the test clock signal and performs frequency division processing to obtain a corresponding test data output frequency and a reference data output frequency;

[0086] Step S903: A test machine compares the test data output frequency and the reference data output frequency; when it is determined that the test data output frequency and the reference data output frequency are consistent, a corresponding control signal is generated and sent to the test frequency generation unit, so that the test frequency generation unit adjusts the test clock frequency of the test clock signal according to a preset frequency reduction step, until the test data output frequency and the reference data output frequency are inconsistent, and a corresponding test result is obtained.

[0087] The test method can be executed by the test circuit described in the foregoing embodiments, or can be executed by other functional structures. For the specific description of the test method of the present embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0088] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A test circuit, characterized by The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included.

2. The test circuit of claim 1, wherein, The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included.

3. The test circuit of claim 2, wherein, The test frequency generating unit, the frequency division processing unit and the test machine are included.

4. The test circuit of claim 3, wherein, The test frequency generating unit, the frequency division processing unit and the test machine are included.

5. The test circuit of claim 2, wherein, The test frequency generating unit, the frequency division processing unit and the test machine are included.

6. The test circuit of claim 5, wherein, The test frequency generating unit, the frequency division processing unit and the test machine are included.

7. The test circuit of claim 2, wherein, The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. 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The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test machine are included. The test frequency generating unit, the frequency division processing unit and the test The data input end of the first D flip-flop is coupled with the data non-inverted output end of the first D flip-flop, the clock input end of the first D flip-flop is the input end of the first frequency divider or is coupled with the input end of the first frequency divider, and the data non-inverted output end of the first D flip-flop is the output end of the first frequency divider or is coupled with the output end of the first frequency divider.

8. The test circuit of claim 2, wherein, The first frequency divider comprises a second D flip-flop and a third inverter. The data input end of the second D flip-flop is coupled with the output end of the third inverter, the clock input end of the second D flip-flop is the input end of the first frequency divider or is coupled with the input end of the first frequency divider, the data output end of the second D flip-flop is coupled with the input end of the third inverter, and the output end of the third inverter is the output end of the first frequency divider or is coupled with the output end of the first frequency divider.

9. The test circuit of claim 1, wherein, The frequency division processing unit comprises a plurality of frequency division processing modules connected in series. The data input end of each frequency division processing module is coupled with the data non-inverted output end of the frequency division processing module, the clock input end of each frequency division processing module is coupled with the data non-inverted output end of the previous frequency division processing module, and the data non-inverted output end of each frequency division processing module is further coupled with the clock input end of the subsequent frequency division processing module.

10. The test circuit of claim 9, wherein, The frequency division processing module comprises a third D flip-flop. The data input end of the third D flip-flop is the data input end of the frequency division processing module or is coupled with the data input end of the frequency division processing module, the clock input end of the third D flip-flop is the clock input end of the frequency division processing module or is coupled with the clock input end of the frequency division processing module, and the data non-inverted output end of the third D flip-flop is the data non-inverted output end of the frequency division processing module or is coupled with the data non-inverted output end of the frequency division processing module.

11. The test circuit of claim 9, wherein, The frequency division processing module comprises a fourth D flip-flop and a fourth inverter. The data input end of the fourth D flip-flop is the data input end of the frequency division processing module or is coupled with the data input end of the frequency division processing module, the clock input end of the fourth D flip-flop is the clock input end of the frequency division processing module or is coupled with the clock input end of the frequency division processing module, the data output end of the fourth D flip-flop is coupled with the input end of the fourth inverter, and the output end of the fourth inverter is the data non-inverted output end of the frequency division processing module or is coupled with the data non-inverted output end of the frequency division processing module.

12. The test circuit according to any one of claims 9 to 11, characterized in that: The number of frequency division processing modules is 5 to 15.

13. The test circuit of claim 1, wherein, The dynamic D flip-flops to be tested are a plurality of dynamic D flip-flops. The test circuit further comprises: A multiplexer, the control end of which is coupled with the test machine, the input end of which is coupled with the output end of the plurality of dynamic D flip-flops to be tested, and the output end of which is coupled with the input end of the frequency division processing unit, and which is adapted to couple the output end of the corresponding dynamic D flip-flop to be tested or the static D flip-flop with the input end of the frequency division processing unit when receiving the read selection signal sent by the test machine.

14. A test system, characterized by The test circuit comprises any one of claims 1-13.

15. A test method characterized by, The test circuit comprises: The test frequency generation unit generates a test clock signal with a corresponding test frequency under the control of a corresponding control signal and transmits the test clock signal to the dynamic D flip-flop and the static D flip-flop to be tested; The frequency division processing unit acquires data output frequencies of the dynamic D flip-flop and the static D flip-flop under the control of the test clock signal and performs frequency division processing to obtain corresponding test data output frequencies and reference data output frequencies; The tester compares the test data output frequencies and the reference data output frequencies; when it is determined that the test data output frequencies and the reference data output frequencies are consistent, corresponding control signals are generated and sent to the test frequency generation unit, so that the test frequency generation unit adjusts the test clock frequency of the test clock signal according to a preset frequency reduction step, until the test data output frequencies and the reference data output frequencies are inconsistent, and corresponding test results are obtained.

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