Load detection circuit and battery system

Abstract

The present invention discloses a load detection circuit and a battery system. The load detection circuit includes: a logic module, a first control module, a comparison module, a second switching module, and a first resistor; a first input terminal of the logic module is connected to a first feedback terminal of the system circuit, a first output terminal of the logic module is connected to a control terminal of the first switching module, and the logic module is configured to output a first control signal to control the first switching module to turn off when performing load detection; the first control module is configured to output a second control signal to control the second switching module to turn on when performing load detection; the comparison module is configured to feedback a load abnormality signal to the system circuit when a detected voltage at a second terminal of the system circuit is greater than a reference voltage. The technical solution provided by the embodiments of the present invention can quickly detect the load condition, thereby determining whether there is an abnormal condition in the load. The circuit structure is simple and the cost is low.

Description

Technical Field

[0001] The present invention relates to the technical field of battery protection, and particularly to a load detection circuit and a battery system. Background Art

[0002] With the rapid development of technology, mobile devices such as mobile phones, electronic cigarettes, mobile power supplies, TWS (True Wireless Stereo) earphones, smart bracelet watches, etc., which use lithium-ion batteries as power supply devices, have been popularized and are increasingly welcomed by the majority of users.

[0003] After the connection of the battery and the load is completed to form a battery system, if the load is damaged, such as the damage of electronic components in the system circuit or the damage of the system circuit caused by the peak voltage during production, especially in the case of increased leakage current or short circuit, it may not be detected by the load circuit in the battery system, or the detection time is too long and the cost is relatively high. Especially in the battery system circuit of TWS earphones, it is impossible to quickly identify whether the load is damaged. Summary of the Invention

[0004] The present invention provides a load detection circuit and a battery system to quickly detect the condition of the load, so as to determine whether the load is damaged.

[0005] On one hand, the present invention provides a load detection circuit for load detection of a battery system. The battery system includes a battery, a system circuit, and a first switch module. The positive electrode of the battery is connected to the first end of the system circuit, the second end of the system circuit is connected to the first end of the first switch module, and the second end of the first switch module is connected to the second pole of the battery. The load detection circuit includes: a logic module, a first control module, a comparison module, a second switch module, and a first resistor;

[0006] The first input end of the logic module is connected to the first feedback end of the system circuit, and the first output end of the logic module is connected to the control end of the first switch module. The logic module is used to output a first control signal to control the first switch module to turn off during load detection;

[0007] The input end of the first control module is connected to the second output end of the logic module, and the output end of the first control module is connected to the control end of the second switch module. The first control module is used to output a second control signal to control the second switch module to turn on during load detection. Wherein, the first end of the second switch module is connected to the second end of the first resistor, the first end of the first resistor is connected to the second end of the system circuit, and the second end of the second switch module is connected to the second pole of the battery;

[0008] The first input terminal of the comparison module is connected to a reference voltage. The second input terminal of the comparison module is connected to the second terminal of the system circuit. The output terminal of the comparison module is respectively connected to the second input terminal of the logic module and the second feedback terminal of the system circuit. The comparison module is configured to feed back a load abnormal signal to the system circuit when the detected voltage at the second terminal of the system circuit is greater than the reference voltage.

[0009] Optionally, the first control module includes a first oscillation unit, a first timing unit, and a first judgment unit;

[0010] The output terminal of the first oscillation unit is connected to the control terminal of the first timing unit. The input terminal of the first timing unit is connected to the second output terminal of the logic module. The first input terminal of the first judgment unit is connected to the second output terminal of the logic module. The second input terminal of the first judgment unit is connected to the output terminal of the first timing unit. The output terminal of the first judgment unit is connected to the control terminal of the second switch module. The first judgment unit is configured to output the second control signal during the first preset time period of the first timing unit.

[0011] Optionally, the first control module further includes a second timing unit and a second judgment unit;

[0012] The control terminal of the second timing unit is connected to the output terminal of the first oscillation unit. The input terminal of the second timing unit is connected to the second output terminal of the logic module. The output terminal of the second timing unit is connected to the second input terminal of the second judgment unit. The first input terminal of the second judgment unit is connected to the input terminal of the second timing unit. The output terminal of the second judgment unit is connected to the enable terminal of the comparison module. The second judgment unit is configured to output a third control signal during the second preset time period of the second timing unit to control the start of the comparison module;

[0013] Wherein, the second preset time is greater than the first preset time.

[0014] Optionally, a first delay unit is further included. The input terminal of the first delay unit is connected to the output terminal of the comparison module. The output terminal of the first delay unit is respectively connected to the second input terminal of the logic module and the second feedback terminal of the system circuit.

[0015] Optionally, a signal detection module is further included. The input terminal of the signal detection module is connected to the first feedback terminal of the system circuit. The output terminal of the signal detection module is connected to the first input terminal of the logic module.

[0016] Optionally, the signal detection module includes a first transistor, a second transistor, a third transistor, a second resistor, a second delay unit, and a first AND gate;

[0017] The gate of the first transistor is connected to the first feedback terminal of the system circuit, the first pole of the first transistor is connected to the second terminal of the system circuit, the second pole of the first transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is connected to a power supply voltage; the first pole of the second transistor is connected to the second terminal of the second resistor, the second pole of the second transistor is connected to the first pole of the third transistor, the second pole of the third transistor is grounded, and the gates of the second transistor and the third transistor are both connected to the first terminal of the second resistor;

[0018] The input of the second delay unit is connected to the first pole of the third transistor, the output terminal of the second delay unit is connected to the first input terminal of the first AND gate, the second input terminal of the first AND gate is connected to the input terminal of the second delay unit, and the output terminal of the first AND gate is connected to the first input terminal of the logic module;

[0019] Or,

[0020] The signal detection module includes a third delay unit, a counting unit, a third timing unit, and a third judgment unit;

[0021] The input terminal of the third delay unit is connected to the first feedback terminal of the system circuit, the output terminal of the third delay unit is respectively connected to the first input terminal of the counting unit and the first input terminal of the third timing unit, the second input terminal of the counting unit is connected to the input terminal of the third delay unit, the output terminal of the counting unit is connected to the first input terminal of the third judgment unit, the second input terminal of the third timing unit is connected to the input terminal of the third delay unit, the output terminal of the third timing unit is connected to the second input terminal of the third judgment unit, and the output terminal of the third judgment unit is connected to the first input terminal of the logic module.

[0022] Optionally, the first feedback terminal of the system circuit is multiplexed as the second feedback terminal;

[0023] The load detection circuit further includes a second control module, the input terminal of the second control module is connected to the second input terminal of the logic module, the output terminal of the second control module is connected to the first feedback terminal of the system circuit, and the second control module is used to delay and divide the signal output by the comparison module;

[0024] The second control module includes a second oscillation unit, a fourth delay unit, and a frequency division unit. A first input end of the fourth delay unit is connected to an output end of the second oscillation unit. A second input end of the fourth delay unit is connected to an output end of the comparison module. An output end of the fourth delay unit is connected to a first input end of the frequency division unit. A second input end of the frequency division unit is connected to the output end of the second oscillation unit. An output end of the frequency division unit is connected to a first feedback end of the system circuit.

[0025] Optionally, the logic module includes a NAND gate and a second AND gate. A first input end of the NAND gate is the first input end of the logic module. A second input end of the NAND gate is the second input end of the logic module. An output end of the NAND gate is the second output end of the logic module and is connected to a first input end of the second AND gate. A second input end of the second AND gate is connected to the battery protection circuit. An output end of the second AND gate is the first output end of the logic module.

[0026] Optionally, the first switch module includes a fourth transistor. A first pole of the fourth transistor is connected to a second end of the system circuit. A second pole of the fourth transistor is connected to a second pole of the battery. A gate of the fourth transistor is connected to the first output end of the logic module; or,

[0027] The first switch module includes a fourth transistor and a sixth transistor. A first pole of the fourth transistor is connected to a second pole of the sixth transistor. A first pole of the sixth transistor is connected to a second end of the system circuit. A second pole of the fourth transistor is connected to a second pole of the battery. A gate of the fourth transistor is connected to the first output end of the logic module. A gate of the sixth transistor is connected to an output end of the battery protection circuit.

[0028] The second switch module includes a fifth transistor. A first pole of the fifth transistor is connected to a second end of the first resistor. A second pole of the fifth transistor is connected to a second pole of the battery. A gate of the fifth transistor is connected to an output end of the first control module.

[0029] On the other hand, the present invention provides a battery system, including the load detection circuit provided in any embodiment of the present invention.

[0030] In the technical solution of the embodiment of the present invention, the logic module receives a trigger signal sent by an external system circuit to enter the load detection mode. The logic module outputs a first control signal to control the first switch module to turn off. At the same time, the first control module generates a second control signal according to the sub-signal output by the logic module to control the second switch module to turn on. By comparing the magnitude relationship between the detection voltage of the system circuit and the reference voltage, it is determined whether the load is damaged. Compared with the prior art, the technical solution provided by the embodiment of the present invention can quickly detect the load condition, thereby determining whether the load has an abnormal condition. The circuit structure is simple and the cost is low.

[0031] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic structural diagram of a load detection circuit provided by an embodiment of the present invention;

[0034] Figure 2 It is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention;

[0035] Figure 3 It is a schematic structural diagram of a first control module provided by an embodiment of the present invention;

[0036] Figure 4 It is a schematic structural diagram of another first control module provided by an embodiment of the present invention;

[0037] Figure 5 It is a timing control waveform diagram of a first control module provided by an embodiment of the present invention;

[0038] Figure 6 It is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention;

[0039] Figure 7 It is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention;

[0040] Figure 8 It is a schematic structural diagram of another first control module provided by an embodiment of the present invention;

[0041] Figure 9 Another structural schematic diagram of the first control module provided by the embodiment of the present invention;

[0042] Figure 10 Another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention;

[0043] Figure 11 A structural schematic diagram of the second control module provided by the embodiment of the present invention;

[0044] Figure 12 Another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention;

[0045] Figure 13 A structural schematic diagram of the signal detection module provided by the embodiment of the present invention;

[0046] Figure 14 A structural schematic diagram of the signal detection module provided by the embodiment of the present invention;

[0047] Figure 15 Another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention;

[0048] Figure 16 Another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention;

[0049] Figure 17 Another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention. Detailed implementation manners

[0050] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] Figure 1 FIG. is a schematic structural diagram of a load detection circuit provided by an embodiment of the present invention. Refer to Figure 1 , the load detection circuit provided in this embodiment can be used for load detection of a battery system. Wherein, the battery system includes a battery, a system circuit 110 and a first switch module 120. The first switch module 120 is the main switch module of the battery system and is used to conduct or cut off the connection between the system circuit 110 and the battery. The load detection circuit 20 includes: a logic module 210, a first control module 220, a comparison module 240, a second switch module 230 and a first resistor R1.

[0053] The first input terminal A1 of the logic module 210 is connected to the first feedback terminal of the system circuit 110. The first output terminal A3 of the logic module 210 is connected to the control terminal of the first switch module 120. The logic module 210 is used to output a first control signal CS1 to control the first switch module 120 to turn off during load detection;

[0054] The input terminal of the first control module 220 is connected to the second output terminal A4 of the logic module 210. The output terminal of the first control module 220 is connected to the control terminal of the second switch module 230. The first control module 220 is used to output a second control signal CS2 to control the second switch module 230 to conduct during load detection; wherein, the first terminal of the second switch module 230 is connected to the second terminal of the first resistor R1. The first terminal of the first resistor R1 is connected to the second terminal of the system circuit 110. The second terminal of the second switch module 230 is connected to the second pole of the battery;

[0055] The first input terminal of the comparison module 240 is connected to the reference voltage VREF. The second input terminal of the comparison module 240 is connected to the second terminal of the system circuit 110. The output terminal of the comparison module 240 is respectively connected to the second input terminal A2 of the logic module 210 and the second feedback terminal of the system circuit 110. The comparison module 240 is configured to feed back a load abnormal signal to the system circuit 110 when the detected voltage VM at the second terminal of the system circuit 110 is greater than the reference voltage VREF.

[0056] Wherein, the system circuit 110 is connected between the first pole of the battery and the first terminal of the first switch module 120, and the second terminal of the first switch module 120 is connected to the second pole of the battery. Here, the first pole of the battery is the positive pole and the second pole is the negative pole; alternatively, the first pole of the battery is the negative pole and the second pole is the positive pole, which can be set according to the actual situation. In this embodiment, the case where the first pole is the positive pole and the second pole is the negative pole is taken as an example for illustration.

[0057] Specifically, the load detection circuit 20 can be integrated in the chip. The first feedback terminal and the second feedback terminal of the system circuit 110 are respectively connected to the load detection circuit 20 through the IO ports of the chip. The load detection circuit 20 starts to work by receiving the signal output by the system circuit 110, controls the first switch module 120 to turn off, so that the connection between the system circuit 110 and the battery is disconnected, and controls the second switch module 230 inside itself to turn on, so that the branch formed by the battery, the second switch module 230 and the system circuit 110 is connected, and the system enters the load detection mode. By detecting the magnitude of the voltage generated by the current in this branch, a logic level signal is output and fed back to the system circuit 110 for processing, so as to determine whether the load is abnormal.

[0058] Exemplarily, when the system needs to enter the load detection mode, the system circuit 110 sends a high-level trigger signal to the first input terminal A1 of the logic module 210. The logic module 210 generates a first control signal CS1 with a low level output from its first output terminal A3 according to the received high-level trigger signal, and outputs a sub-signal with a low level from its second output terminal A4. The first control module 220 outputs a second control signal CS2 with a high level according to the sub-signal with a low level. Therefore, the first switch module 120 turns off in response to the low-level first control signal CS1, and the second switch module 230 turns on in response to the high-level second control signal CS2. A loop is formed among the system circuit 110, the first resistor R1, the second switch module 230 and the battery, and the detected voltage VM at the second terminal of the system circuit 110 is equal to the product of the loop current and the resistance value of the first resistor R1.

[0059] In the load detection mode, if the detected voltage VM is less than or equal to the reference voltage VREF, the comparison module 240 outputs a high-level signal. The logic module 210 receives this high-level signal and maintains the original logic output, and the first switch module 120 remains in the off state. At this time, the load detection circuit 20 does not feedback a signal to the system circuit 110 through the corresponding IO port, or feedbacks the high-level signal output by the comparison module 240 to the system circuit 110. If the detected voltage VM is greater than the reference voltage VREF, the comparison module 240 outputs a low-level signal. The load detection circuit 20 feedbacks a load abnormality signal to the system circuit 110 through the corresponding IO port, and the system circuit 110 determines that the load is damaged. At this time, the output state of the logic module 210 is controlled by the low-level signal received by its second input terminal A2. The first switch module 120 is turned on in response to the high-level first control signal CS1 output by the logic module 210. At the same time, the second switch module 230 is turned off in response to the low-level second control signal CS2 output by the first control module 220, preventing the second switch module 230 from affecting the off state of the first switch module 120 in other abnormal states.

[0060] The load detection circuit provided by the embodiment of the present invention enters the load detection mode by receiving a trigger signal sent by an external system circuit through a logic module. The logic module outputs a first control signal to control the first switch module to turn off. At the same time, the first control module generates a second control signal according to the sub-signal output by the logic module to control the second switch module to turn on. By comparing the magnitude relationship between the detected voltage of the system circuit and the reference voltage, it is determined whether the load is damaged. Compared with the prior art, the technical solution provided by the embodiment of the present invention can quickly detect the load condition, thereby determining whether the load is abnormal. The circuit structure is simple and the cost is low.

[0061] In this embodiment, the comparison module 240 can be a comparator or a comparator with a delay function, that is, an abnormal level needs to be output after a certain period of time. The battery can be a lithium battery or other types of batteries.

[0062] Figure 2 For the structural schematic diagram of another load detection circuit provided by the embodiment of the present invention, refer to Figure 2 Based on the above technical solution, optionally, the logic module 210 includes a NAND gate I1 and a second AND gate I2. The first input terminal of the NAND gate I1 is the first input terminal A1 of the logic module 210, the second input terminal of the NAND gate I1 is the second input terminal A2 of the logic module 210, the output terminal of the NAND gate I1 is the second output terminal A4 of the logic module 210 and is connected to the first input terminal of the second AND gate I2. The second input terminal of the second AND gate I2 is connected to the battery protection circuit 30, and the output terminal of the second AND gate I2 is the first output terminal A3 of the logic module 210.

[0063] Among them, the battery protection circuit 30 is a basic protection circuit inside the battery system (not belonging to the load detection circuit 20), and can be used to implement overcharge voltage protection, overcharge current protection, discharge voltage protection, discharge current protection, over-temperature protection, etc. of the battery. When the battery is not in the protection state, the output of the battery protection circuit 30 is a high-level signal.

[0064] Continue to refer to Figure 2 , the load detection circuit 20 provided in this embodiment further includes a second control module 250. The input end of the second control module 250 is connected to the second input end A2 of the logic module 210, and the output end of the second control module 250 is connected to the first feedback end of the system circuit 110. Here, since the first feedback end of the system circuit 110 no longer controls the load detection circuit 20 after the load detection circuit 20 is started, the first feedback end of the system circuit 110 can be reused as the second feedback end, and the second control module 250 feeds back the level signal output by the comparison module 240 to the first feedback end of the system circuit 110. The technical solution provided in this embodiment can reduce the number of IO ports used by the chip integrating the load detection circuit 20, which is beneficial to optimizing resource allocation. Among them, the specific structure of the second control module 250 will be described in detail in subsequent embodiments.

[0065] The following embodiments will all be described by taking the first feedback end of the system circuit 110 reusing the second feedback end as an example, that is, the input and output of the load detection circuit 20 share one IO port.

[0066] Figure 3 It is a schematic structural diagram of a first control module provided by an embodiment of the present invention, which can enable the first control module 220 to pulse-width turn on the second switch module 230 to reduce the power consumption of the load detection circuit 20. Combining Figure 2 and Figure 3 , the first control module 220 includes a first oscillation unit 2201, a first timing unit 2202, and a first judgment unit 2203. The output end of the first oscillation unit 2201 is connected to the control end of the first timing unit 2202. The input end of the first timing unit 2202 is connected to the second output end A4 of the logic module 210. The first input end of the first judgment unit 2203 is connected to the second output end A4 of the logic module 210. The second input end of the first judgment unit 2203 is connected to the output end of the first timing unit 2202. The output end of the first judgment unit 2203 is connected to the control end of the second switch module 230. The first judgment unit 2203 is used to output a second control signal CS2 during the first preset time when the first timing unit 2202 is timing.

[0067] Specifically, the input terminal VIN1 of the first control module 220 is used to receive the sub-signal output from the second output terminal A4 of the logic module 210. The first oscillation unit 2201 can be an oscillator, such as a crystal oscillator, for generating a clock signal; the first timing unit 2202 is used to start timing when detecting that the sub-signal at the input terminal VIN1 of the first control module 220 is a valid signal, and the timing ends after a first preset time. The first determination unit 2203 outputs a second control signal CS2 during the timing of the first timing unit 2202 to control the second switch module 230 to conduct, and at other times except the first preset time, the second control module 220 controls the second switch module 230 to turn off.

[0068] Figure 4 Another structural schematic diagram of the first control module provided by the embodiment of the present invention, specifically Figure 3 The structural schematic diagram of the first control module shown is specifically the structural schematic diagram of a device Figure 5 A timing control waveform diagram of a first control module provided by the embodiment of the present invention, refer to Figures 3 to 5 As shown in, the first timing unit 2202 can be composed of multiple first flip-flops TR1, and the first determination unit 2203 can be a third AND gate I3. When the sub-signal output from the second output terminal A4 of the logic module 210 jumps from a high level to a low level, the first determination unit 2203 outputs a high-level second control signal CS2 from its output terminal OUT1 according to the low-level sub-signal and the low-level signal output by the first timing unit 2202 to control the second switch module 230 to conduct. After the first preset time, when the last flip-flop of the first timing unit 2202 outputs a high level, the timing ends, and the duration of the high-level second control signal CS2 is the first preset time. After the system enters the load detection mode, it can prevent the second switch module 230 from being always in the conducting state before it is determined that the load is not damaged, which may cause incorrect judgment or functional abnormality of other functions of the system. Among them, the first preset time can be set according to actual needs. Generally, it is set between several hundred milliseconds and several seconds.

[0069] Figure 6 Another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention, refer to Figure 6 Based on the above technical solution, optionally, the output terminal of the first control module 220 can also be connected to the enable terminal of the comparison module 240. The high-level second control signal CS2 output by the first control module 220 controls the second switch module 230 to conduct and also controls the comparison module 240 to turn on. That is to say, in the load detection mode, the second switch module 230 and the comparison module 240 are only conducting within the set first preset time, and are in the off state at other times, which is beneficial to reducing the power consumption of the load detection circuit 20 and the power consumption of the system.

[0070] Preferably, the second switching module 230 and the comparison module 240 can be turned on separately to prevent the comparison module 240 from making a misjudgment due to the instantaneous conduction of the second switching module 230, thereby reducing the accuracy of load detection. Figure 7 FIG. is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention. Refer to Figure 7 , one output terminal of the first control module 220 is connected to the control terminal of the second switching module 230 for outputting a second control signal CS2; another output terminal is connected to the enable terminal of the comparison module 240 for outputting a third control signal CS3. Among them, the effective start time of the third control signal CS3 can be later than the effective start time of the second control signal CS2, so that the comparison module 240 starts to work after the second switching module 230 is turned on.

[0071] Figure 8 FIG. is a schematic structural diagram of another first control module provided by an embodiment of the present invention. Refer to Figure 3 and Figure 8 , on the basis of the structure shown in Figure 3 , the first control module 220 further includes a second timing unit 2204 and a second judgment unit 2205. The control terminal of the second timing unit 2204 is connected to the output terminal of the first oscillation unit 2201. The input terminal of the second timing unit 2204 is connected to the second output terminal A4 of the logic module 210. The output terminal of the second timing unit 2204 is connected to the second input terminal of the second judgment unit 2205. The first input terminal of the second judgment unit 2205 is connected to the input terminal of the second timing unit 2204. The output terminal of the second judgment unit 2205 is connected to the enable terminal of the comparison module 240. The second judgment unit 2205 is configured to output a third control signal CS3 from its output terminal OUT2 during the second preset time counted by the second timing unit 2204 to control the comparison module 240 to start.

[0072] Figure 9 FIG. is a schematic structural diagram of another first control module provided by an embodiment of the present invention. Specifically, Figure 8 the schematic structural diagram of the first control module shown is specifically the schematic structural diagram of a device. The second judgment unit 2205 includes a fourth AND gate I4. Figure 9 For the specific working principle of the first control module 220 shown, reference can be made to the relevant description of the structure shown in Figure 4 . Details are not described herein again. It should be noted that the second preset time is greater than the first preset time, and the timing duration of the second timing unit 2204 is greater than the timing duration of the first timing unit 2202 to ensure that the comparison module 240 starts after the second switching module 230 is turned on.

[0073] Optionally, the first control module 220 may further include a fifth delay unit 2206 to delay the sub-signal received at the input end of the second timing unit 2204, ensuring that the first judgment unit 2203 and the second judgment unit 2205 do not output signals simultaneously.

[0074] Figure 10 FIG. is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention. Refer to Figure 10 , based on the above technical solutions, optionally, the load detection circuit 20 further includes a first delay unit 260. The input end of the first delay unit 260 is connected to the output end of the comparison module 240, and the output end of the first delay unit 260 is respectively connected to the second input end A2 of the logic module 210 and the second feedback end of the system circuit 110. Among them, when the load detection circuit 20 shares an IO port, the first delay unit 260 is connected to the second feedback end of the system circuit 110 through the second control module 250. The first delay unit 260 is used to delay the level signal output by the comparison module 240 to ensure that the system circuit 110 and the logic module 210 have sufficient delay time to receive the level signal output by the comparison module 240, which is beneficial to improving the anti-interference ability of the load detection circuit 20. Among them, the first delay unit 260 may be composed of an oscillator and a trigger.

[0075] Figure 11 FIG. is a schematic structural diagram of a second control module provided by an embodiment of the present invention. Refer to Figure 11 and Figure 10 , optionally, the second control module 250 includes a second oscillation unit 2501, a fourth delay unit 2502, and a frequency division unit 2503. The first input end of the fourth delay unit 2502 is connected to the output end of the second oscillation unit 2501, the second input end of the fourth delay unit 2502 is connected to the output end of the comparison module 240, the output end of the fourth delay unit 2502 is connected to the first input end of the frequency division unit 2503, the second input end of the frequency division unit 2503 is connected to the output end of the second oscillation unit 2501, and the output end OUT3 of the frequency division unit 2503 is connected to the first feedback end of the system circuit 110.

[0076] Among them, the frequency division unit 2503 is used to reduce the working frequency of the level signal output by the comparison module 240, facilitating the system circuit 110 to detect the level signal, which is beneficial to improving the accuracy of load detection.

[0077] In this embodiment, the fourth delay unit 2502 may also be a pulse-type opening structure, which is used to transmit corresponding signals to the frequency division unit 2503 during the delay time. For example, the structure of the fourth delay unit 2502 may be the same as that of Figure 3The structure of the first control module 220 shown is the same, and its specific working principle can be referred to the Figure 3 specific description of the first control module 220 shown, which will not be elaborated here.

[0078] Figure 12 FIG. is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention. Referring to Figure 12 , on the basis of the above technical solutions, optionally, the load detection circuit 20 provided in this embodiment further includes a signal detection module 270. The input end of the signal detection module 270 is connected to the first feedback end of the system circuit 110, and the output end of the signal detection module 270 is connected to the first input end A1 of the logic module 240. The signal detection module 270 is configured to detect the trigger signal output by the system circuit 110. At this time, the trigger signal output by the system circuit 110 may be a pulse signal, and the load detection circuit 20 is started according to this pulse signal. Compared with the method of starting the load detection circuit 20 according to a high-level trigger signal, the technical solution provided in this embodiment can improve the anti-interference performance of the overall circuit.

[0079] Figure 13 FIG. is a schematic structural diagram of a signal detection module provided by an embodiment of the present invention. Referring to Figure 12 and Figure 13 , the signal detection module 270 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a second resistor R2, a second delay unit 2701, and a first AND gate I5. The gate of the first transistor Q1 is connected to the first feedback end of the system circuit 110. The first pole of the first transistor Q1 is connected to the detection voltage VM (i.e., connected to the second end of the system circuit 110), and the second pole of the first transistor Q1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the power supply voltage VCC. The first pole of the second transistor Q2 is connected to the second end of the second resistor R2, the second pole of the second transistor Q2 is connected to the first pole of the third transistor Q3, the second pole of the third transistor Q3 is grounded, and the gates of the second transistor Q2 and the third transistor Q3 are both connected to the first end of the second resistor R2. The input of the second delay unit 2701 is connected to the first pole of the third transistor Q3, the output end of the second delay unit 2701 is connected to the first input end of the first AND gate I5, the second input end of the first AND gate I5 is connected to the input end of the second delay unit 2701, and the output end of the first AND gate I5 is connected to the first input end A1 of the logic module 270, that is, the OUT4 end is the output end of the signal detection module 270.

[0080] Specifically, when the trigger signal output by the system circuit 110 turns on the first transistor Q1, the detection voltage VM is transmitted to the gates of the second transistor Q2 and the third transistor Q3. The channel types of the second transistor Q2 and the third transistor Q3 are opposite. For example, the second transistor Q2 is a P-type transistor, and the third transistor Q3 is an N-type transistor. The second transistor Q2 or the third transistor Q3 turns on according to the voltage at its gate. Here, the second resistor R2 is a pull-up resistor to ensure the stability of the detection voltage VM at the gates of the second transistor Q2 and the third transistor Q3. When the detection voltage VM is small enough to turn on the second transistor Q2 and turn off the third transistor Q3, the power supply voltage VCC is transmitted to the input terminal of the second delay unit 2701 and the second input terminal of the first AND gate I5 through the second transistor Q2. After the delay of the second delay unit 2701, the first AND gate I5 outputs a high-level signal, and the system enters the load detection mode. Among them, the power supply voltage VCC can be converted from the battery voltage or can be a separate voltage.

[0081] When the detection voltage VM is large enough to turn on the third transistor M3, the ground voltage is transmitted to the input terminal of the second delay unit 2701 and the second input terminal of the first AND gate I5 through the second transistor Q2. After the delay of the second delay unit 2701, the first AND gate I5 outputs a low-level signal, that is, the signal detection module 270 outputs a low-level signal to the first input terminal A1 of the logic module 210.

[0082] Figure 14 FIG. is a schematic structural diagram of a signal detection module provided by an embodiment of the present invention. Refer to Figure 12 and Figure 14 , the signal detection module 270 includes a third delay unit 2702, a counting unit 2703, a third timing unit 2704, and a third determination unit 2705; the input terminal of the third delay unit 2702 is connected to the first feedback terminal of the system circuit 110, and the output terminal of the third delay unit 2702 is respectively connected to the first input terminal of the counting unit 2703 and the first input terminal of the third timing unit 2704. The second input terminal of the counting unit 2703 is connected to the input terminal of the third delay unit 2704. The output terminal of the counting unit 2703 is connected to the first input terminal of the third determination unit 2705. The second input terminal of the third timing unit 2704 is connected to the input terminal of the third delay unit 2702. The output terminal of the third timing unit 2704 is connected to the second input terminal of the third determination unit 2705. The output terminal of the third determination unit 2705 is connected to the first input terminal A1 of the logic module 210.

[0083] Specifically, the counting unit 2703 counts the number of pulses of the trigger signal output by the system circuit 110 and the trigger signal delayed by the third delay unit 2702, and outputs a first type of signal when the number of pulses reaches a preset number; at the same time, the third timing unit 2704 times the trigger signal output by the system circuit 110 and the trigger signal delayed by the third delay unit 2702, and outputs a second type of signal within the delay time of the third delay unit 2702. The third determination unit 2705 makes a logical determination based on the received first type of signal and second type of signal that meet the conditions, and outputs a high-level signal to the first input terminal A1 of the logic module 210.

[0084] In this embodiment, both the second delay unit 2701 and the third delay unit 2702 may include an oscillator and a trigger. The specific structure of this embodiment is not limited as long as it can play a delay role.

[0085] The technical solution provided in this embodiment enables the system circuit 110 to output a pulse signal to trigger the load detection circuit 20 to enter the load detection mode by adding the signal detection module 270, which is beneficial to improving the anti-interference performance of the circuit.

[0086] Figure 15 For another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention, refer to Figure 15 , the first switch module 120 includes a fourth transistor Q4. The first pole of the fourth transistor Q4 is connected to the second terminal of the system circuit 110, the second pole of the fourth transistor Q4 is connected to the negative pole of the battery, and the gate of the fourth transistor Q4 is connected to the first output terminal A3 of the logic module 210; the second switch module 230 includes a fifth transistor Q5. The first pole of the fifth transistor Q5 is connected to the second terminal of the first resistor R1, the second pole of the fifth transistor Q5 is connected to the negative pole of the battery, and the gate of the fifth transistor Q5 is connected to the output terminal of the first control module 220. Here, both the fourth transistor Q4 and the fifth transistor Q5 may be N-type transistors. Of course, in other embodiments, both the fourth transistor Q4 and the fifth transistor Q5 may also be P-type transistors.

[0087] Figure 16 For another structural schematic diagram of the load detection circuit provided by the embodiment of the present invention, refer to Figure 16 , the fourth transistor Q4 is connected between the positive pole of the battery and the first terminal of the system circuit 110, and the fifth transistor Q5 and the first resistor R1 are connected in series between the positive pole of the battery and the first terminal of the system circuit 110, forming a positive pole protection structure of the battery, similar to Figure 15 the negative pole protection structure shown. The load detection circuit 20 provided by any embodiment of the present invention is also applicable to Figure 16The circuit structure shown also has the beneficial effects described in any embodiment of the present invention, and its specific working principle will not be elaborated here.

[0088] Figure 17 FIG. is a schematic structural diagram of another load detection circuit provided by an embodiment of the present invention. Among them, Figure 17 The structure shown is a discrete protection structure, and the charge and discharge between the battery and the system circuit 110 are respectively realized through two transistors (the fifth transistor Q5 and the sixth transistor Q6). Refer to Figure 17 , optionally, the first switch module 120 includes a fourth transistor Q4 and a sixth transistor Q6. The first pole of the fourth transistor Q4 is connected to the second pole of the sixth transistor Q6. The first pole of the sixth transistor Q6 is connected to the second end of the system circuit 110. The second pole of the fourth transistor Q4 is connected to the negative pole of the battery. The gate of the fourth transistor Q4 is connected to the first output terminal A3 of the logic module 210. The gate of the sixth transistor Q6 is connected to the output terminal of the battery protection circuit. The load detection circuit 20 provided by any embodiment of the present invention is also applicable to Figure 17 The circuit structure shown also has the beneficial effects described in any embodiment of the present invention, and its specific working principle will not be elaborated here.

[0089] Optionally, the present invention also provides a battery system, which includes a battery, a system circuit, a first switch module, a battery protection circuit, and the load detection circuit provided by any embodiment of the present invention, where the battery can be a lithium battery. In other embodiments, the battery can also be other types of batteries. Therefore, the battery system provided by this embodiment also has the beneficial effects described in any embodiment of the present invention, and its specific working principle will not be elaborated here.

[0090] It should be understood that the various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation here.

[0091] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A load detection circuit, characterized in that, it is used for load detection of a battery system, the battery system includes a battery, a system circuit and a first switch module, a first pole of the battery is connected to a first end of the system circuit, a second end of the system circuit is connected to a first end of the first switch module, and a second end of the first switch module is connected to a second pole of the battery; the load detection circuit includes: a logic module, a first control module, a comparison module, a second switch module and a first resistor; a first input end of the logic module is connected to a first feedback end of the system circuit, a first output end of the logic module is connected to a control end of the first switch module, and the logic module is configured to output a first control signal to control the first switch module to turn off during load detection; an input end of the first control module is connected to a second output end of the logic module, an output end of the first control module is connected to a control end of the second switch module, and the first control module is configured to output a second control signal to control the second switch module to turn on during load detection; wherein, a first end of the second switch module is connected to a second end of the first resistor, a first end of the first resistor is connected to a second end of the system circuit, and a second end of the second switch module is connected to a second pole of the battery; a first input end of the comparison module is connected to a reference voltage, a second input end of the comparison module is connected to a second end of the system circuit, and an output end of the comparison module is respectively connected to a second input end of the logic module and a second feedback end of the system circuit, and the comparison module is configured to feed back a load abnormal signal to the system circuit when a detected voltage at the second end of the system circuit is greater than the reference voltage.

2. The load detection circuit according to claim 1, characterized in that, the first control module includes a first oscillation unit, a first timing unit and a first judgment unit; an output end of the first oscillation unit is connected to a control end of the first timing unit, an input end of the first timing unit is connected to a second output end of the logic module, a first input end of the first judgment unit is connected to a second output end of the logic module, a second input end of the first judgment unit is connected to an output end of the first timing unit, and an output end of the first judgment unit is connected to a control end of the second switch module, and the first judgment unit is configured to output the second control signal during a first preset time period when the first timing unit is timing.

3. The load detection circuit according to claim 2, characterized in that, the first control module further includes a second timing unit and a second judgment unit; The control terminal of the second timing unit is connected to the output terminal of the first oscillation unit. The input terminal of the second timing unit is connected to the second output terminal of the logic module. The output terminal of the second timing unit is connected to the second input terminal of the second determination unit. The first input terminal of the second determination unit is connected to the input terminal of the second timing unit. The output terminal of the second determination unit is connected to the enable terminal of the comparison module. The second determination unit is configured to output a third control signal during a second preset time period when the second timing unit is timing, so as to control the comparison module to start; Wherein, the second preset time is greater than the first preset time.

4. The load detection circuit according to claim 1, characterized in that, further comprising a first delay unit, the input terminal of the first delay unit is connected to the output terminal of the comparison module, and the output terminal of the first delay unit is respectively connected to the second input terminal of the logic module and the second feedback terminal of the system circuit.

5. The load detection circuit according to claim 1, characterized in that, further comprising a signal detection module, the input terminal of the signal detection module is connected to the first feedback terminal of the system circuit, and the output terminal of the signal detection module is connected to the first input terminal of the logic module.

6. The load detection circuit according to claim 5, characterized in that, the signal detection module includes a first transistor, a second transistor, a third transistor, a second resistor, a second delay unit and a first AND gate; The gate of the first transistor is connected to the first feedback terminal of the system circuit. The first pole of the first transistor is connected to the second terminal of the system circuit. The second pole of the first transistor is connected to the first terminal of the second resistor. The second terminal of the second resistor is connected to a power supply voltage. The first pole of the second transistor is connected to the second terminal of the second resistor. The second pole of the second transistor is connected to the first pole of the third transistor. The second pole of the third transistor is grounded. The gates of the second transistor and the third transistor are both connected to the first terminal of the second resistor; The input of the second delay unit is connected to the first pole of the third transistor. The output terminal of the second delay unit is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the input terminal of the second delay unit. The output terminal of the first AND gate is connected to the first input terminal of the logic module; Or, the signal detection module includes a third delay unit, a counting unit, a third timing unit and a third determination unit; The input end of the third delay unit is connected to the first feedback end of the system circuit. The output end of the third delay unit is respectively connected to the first input end of the counting unit and the first input end of the third timing unit. The second input end of the counting unit is connected to the input end of the third delay unit. The output end of the counting unit is connected to the first input end of the third judging unit. The second input end of the third timing unit is connected to the input end of the third delay unit. The output end of the third timing unit is connected to the second input end of the third judging unit. The output end of the third judging unit is connected to the first input end of the logic module.

7. The load detection circuit according to any one of claims 1-6, wherein, the first feedback end of the system circuit is multiplexed as the second feedback end; the load detection circuit further includes a second control module. The input end of the second control module is connected to the second input end of the logic module. The output end of the second control module is connected to the first feedback end of the system circuit. The second control module is configured to delay and divide the frequency of the signal output by the comparison module; the second control module includes a second oscillation unit, a fourth delay unit and a frequency division unit. The first input end of the fourth delay unit is connected to the output end of the second oscillation unit. The second input end of the fourth delay unit is connected to the output end of the comparison module. The output end of the fourth delay unit is connected to the first input end of the frequency division unit. The second input end of the frequency division unit is connected to the output end of the second oscillation unit. The output end of the frequency division unit is connected to the first feedback end of the system circuit.

8. The load detection circuit according to claim 1, wherein, the logic module includes a NAND gate and a second AND gate. The first input end of the NAND gate is the first input end of the logic module. The second input end of the NAND gate is the second input end of the logic module. The output end of the NAND gate is the second output end of the logic module and is connected to the first input end of the second AND gate. The second input end of the second AND gate is connected to the battery protection circuit. The output end of the second AND gate is the first output end of the logic module.

9. The load detection circuit according to claim 1, wherein, the first switch module includes a fourth transistor. The first pole of the fourth transistor is connected to the second end of the system circuit. The second pole of the fourth transistor is connected to the second pole of the battery. The gate of the fourth transistor is connected to the first output end of the logic module; or, the first switch module includes a fourth transistor and a sixth transistor. The first pole of the fourth transistor is connected to the second pole of the sixth transistor. The first pole of the sixth transistor is connected to the second end of the system circuit. The second pole of the fourth transistor is connected to the second pole of the battery. The gate of the fourth transistor is connected to the first output end of the logic module. The gate of the sixth transistor is connected to the output end of the battery protection circuit; The second switching module includes a fifth transistor. A first pole of the fifth transistor is connected to a second end of the first resistor. A second pole of the fifth transistor is connected to a second pole of the battery. A gate of the fifth transistor is connected to an output end of the first control module.

10. A battery system, characterized in that it includes the load detection circuit according to any one of claims 1-9.

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