Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof, and a display device. The display substrate comprises: a base substrate, comprising a pixel array area and a peripheral area; a first scan drive circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are arranged in the peripheral area and located on the first side of the base substrate. The first scan drive circuit comprises a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power supply voltages to the plurality of cascaded shift registers included in the first scan drive circuit; the first signal line group comprises at least one timing signal line; the second signal line group comprises a first trigger signal line, which is configured to provide a first trigger signal to the first-stage first shift register, and the first trigger signal line is located between the plurality of power lines and the pixel array area. The display substrate facilitates the introduction of signal lines, which is conducive to the display of a large-size display panel.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 21, 2019, application number 201980001412.8, and invention name “Display substrate, manufacturing method thereof, and display device”. Technical Field

[0002] Embodiments of the present disclosure relate to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0003] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The driving of the gate lines can be achieved by a bound integrated drive circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide a switching state voltage signal (scanning signal) for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to open in sequence, and at the same time, the data line provides a data signal to the pixel unit of the corresponding row in the pixel array, so as to form the grayscale voltage required for each grayscale of the display image in each pixel unit, thereby displaying a frame of image. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a pixel array area and a peripheral area; a first scan drive circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are arranged in the peripheral area and located on the first side of the base substrate. The first scan drive circuit comprises a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power supply voltages to the plurality of cascaded first shift registers included in the first scan drive circuit; the first signal line group comprises at least one timing signal line, which is configured to provide at least one timing signal to the plurality of cascaded first shift registers included in the first scan drive circuit; the second signal line group comprises a first trigger signal line, which is configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers included in the first scan drive circuit to provide a first trigger signal to the first-stage first shift register, and the first trigger signal line is located between the plurality of power lines and the pixel array area.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second signal line group is located on a side of the first scanning driving circuit close to the pixel array area, and the first signal line group is located on the other side of the first scanning driving circuit opposite to the side where the second signal line group is located.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel array area includes a first display area and a second display area that are parallel to each other and do not overlap, and the first scan drive circuit is connected to the first display area to drive the first display area to display; the display substrate also includes a second scan drive circuit arranged in the peripheral area and located on the first side of the base substrate, which is arranged in sequence with the first scan drive circuit along the scanning direction of the pixel array and connected to the second display area to drive the second display area to display. The second scan drive circuit includes a plurality of cascaded second shift registers, and the second signal line group also includes a second trigger signal line, which is connected to the first-stage second shift register of the plurality of cascaded second shift registers included in the second scan drive circuit to provide a second trigger signal to the first-stage second shift register included in the second scan drive circuit.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the extension lengths of the first trigger signal line and the second trigger signal line are the same as the arrangement lengths of the first scan driving circuit and the second scan driving circuit.

[0008] For example, in a display substrate provided in at least one embodiment of the present disclosure, the first trigger signal line and the second trigger signal line are arranged side by side.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of power lines include a first power line and a second power line; the first power line and the second power line are configured to provide the same first power voltage.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the first power line on the base substrate partially overlaps with the orthographic projection of the first scanning drive circuit on the base substrate, and the orthographic projection of the second power line on the base substrate is located between the orthographic projection of the first power line on the base substrate and the orthographic projection of the second signal line group on the base substrate.

[0011] For example, the display substrate provided by at least one embodiment of the present disclosure further includes at least one first resistor; the first resistor is located on the side of the first scanning drive circuit away from the first-stage first shift register, and the first trigger signal line is connected to the first-stage first shift register of the first scanning drive circuit through the at least one first resistor.

[0012] For example, the display substrate provided by at least one embodiment of the present disclosure further includes at least one second resistor, wherein the second resistor is located between the last-stage first shift register of the first scanning driving circuit and the first-stage second shift register of the second scanning driving circuit, and the second trigger signal line is connected to the first-stage second shift register of the second scanning driving circuit through the at least one second resistor.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first resistor and the second resistor have different sizes.

[0014] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a folding line located between the first display area and the second display area; the second resistor is located in an extension direction of the folding line, and the extension direction of the folding line is perpendicular to the extension direction of the first signal line group and the second signal line group.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the at least one second resistor on the base substrate is located between the orthographic projection of the last-stage first shift register of the first scanning driving circuit on the base substrate and the orthographic projection of the first-stage second shift register of the second scanning driving circuit on the base substrate.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one first resistor is located between the base substrate and the second signal line group in a direction perpendicular to the base substrate, and the orthographic projection of the at least one first resistor on the base substrate is located on a side of the orthographic projection of the second signal line group on the base substrate away from the pixel array area.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the material of the first resistor is a semiconductor material.

[0018] For example, the display substrate provided by at least one embodiment of the present disclosure also includes at least one first connecting line and at least one second connecting line; the first connecting line connects one end of the at least one first resistor to the first-stage first shift register of the first scanning drive circuit, and the second connecting line connects the other end of the at least one first resistor to the first trigger signal line.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first connecting line and the second connecting line are located on a side of the at least one first resistor away from the base substrate.

[0020] For example, the display substrate provided by at least one embodiment of the present disclosure further includes: a first conductive connection part, a second conductive connection part, a first insulating layer and a second insulating layer; the first conductive connection part and the second conductive connection part are located on the side of the first connection line and the second connection line away from the base substrate, and are arranged on the same layer as the multiple power lines, the first signal line group and the second signal line group, the first insulating layer is located between the at least one first resistor and the first connection line and the second connection line in a direction perpendicular to the base substrate, and the second insulating layer is located between the first connection line and the second connection line and the first conductive connection part and the second conductive connection part in a direction perpendicular to the base substrate. One end of the first conductive connection portion is connected to one end of the first connection line through a via penetrating the second insulating layer, the other end of the first conductive connection portion is connected to one end of the at least one first resistor through a via penetrating the first insulating layer and the second insulating layer, and the other end of the first connection line is connected to the first-stage first shift register of the first scan drive circuit; one end of the second conductive connection portion is connected to one end of the second connection line through a via penetrating the second insulating layer, the other end of the second conductive connection portion is connected to the other end of the at least one first resistor through a via penetrating the first insulating layer and the second insulating layer, and the other end of the second connection line is connected to the first trigger signal line through a via penetrating the second insulating layer.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the first shift registers of the first scan driving circuit includes a first constituent transistor connected to the first power line and a second constituent transistor and a third constituent transistor connected to the second power line; the orthographic projection of the first constituent transistor on the substrate substrate is located between the orthographic projection of the first signal line group on the substrate substrate and the orthographic projection of the first power line on the substrate substrate and is close to the orthographic projection of the first power line on the substrate substrate, and the orthographic projection of the second constituent transistor and the third constituent transistor on the substrate substrate is located between the orthographic projection of the first power line on the substrate substrate and the orthographic projection of the second power line on the substrate substrate and is close to the orthographic projection of the second power line on the substrate substrate.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of power lines include a third power line and a fourth power line; the third power line and the fourth power line are configured to provide the same second power supply voltage; the orthographic projection of the fourth power line on the base substrate partially overlaps with the orthographic projection of the first scanning drive circuit on the base substrate, and the orthographic projection of the third power line on the base substrate is located between the orthographic projection of the fourth power line on the base substrate and the orthographic projection of the first signal line group on the base substrate.

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the first shift registers of the first scan driving circuit further includes a fourth constituent transistor connected to the third power line and a fifth constituent transistor connected to the fourth power line; the orthographic projection of the fourth constituent transistor on the substrate substrate is located on a side of the orthographic projection of the third power line on the substrate substrate away from the orthographic projection of the first signal line group on the substrate substrate, and is close to the orthographic projection of the third power line on the substrate substrate, and the orthographic projection of the fifth constituent transistor on the substrate substrate is located between the orthographic projection of the fourth power line on the substrate substrate and the orthographic projection of the second signal line group on the substrate substrate, and is close to the orthographic projection of the fourth power line on the substrate substrate.

[0024] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a pixel array area and a peripheral area, a first scan drive circuit, a plurality of power lines, a first signal line group and a second signal line group, which are arranged in the peripheral area and located on a first side of the base substrate; the first scan drive circuit comprises a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power supply voltages to the plurality of cascaded first shift registers included in the first scan drive circuit; the first signal line group comprises at least one timing signal line, which is configured to provide at least one timing signal to the plurality of cascaded first shift registers included in the first scan drive circuit; the second signal line group comprises a first trigger signal line, which is configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers included in the first scan drive circuit to provide a first trigger signal to the first-stage first shift register, the first scan drive circuit comprises a first transistor, a second transistor and a third transistor, the first transistor, the second transistor and the third transistor are respectively connected to the first signal line group, and the extension direction of the channels of the first transistor, the second transistor and the third transistor is parallel to the extension direction of the first signal line group and the second signal line group.

[0025] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first scan driving circuit also includes a sixth transistor and a seventh transistor, and the sixth transistor and the seventh transistor are respectively connected to the first signal line group, and the extension direction of the channel of the sixth transistor and the seventh transistor is parallel to the extension direction of the first signal line group and the second signal line group.

[0026] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate provided by any embodiment of the present disclosure.

[0027] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, comprising: providing a base substrate; forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer and a third conductive layer in sequence in a direction perpendicular to the base substrate; the power line, the first signal line group and the second signal line group are located in the third conductive layer; the first scan drive circuit is formed in the semiconductor layer, the first conductive layer and the second conductive layer; the first scan drive circuit is respectively connected to the power line, the first signal line group and the second signal line group through vias penetrating the first insulating layer, the second insulating layer and the third insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0029] Figure 1 A circuit diagram of a light emitting control shift register;

[0030] Figure 2 for Figure 1 The signal timing diagram of the light emitting control shift register shown in FIG.

[0031] Figure 3 A schematic diagram of a first resistor and a second resistor provided in at least one embodiment of the present disclosure;

[0032] Figure 4 A schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0033] Figure 5A A schematic diagram of the layout of a display substrate provided for at least one embodiment of the present disclosure;

[0034] Figure 5B A schematic layout diagram of a display substrate including a first-stage shift register of a second scan drive circuit is shown;

[0035] Fig. 6A , Fig. 7A , Figure 8 and Fig. 9A They are shown respectively Figure 5A A plan view showing wiring of each layer of the substrate is shown in FIG.

[0036] Figure 6B , Figure 7B , Figure 8 and Fig. 9B They are shown respectively Figure 5B The plan view of each layer wiring of the first stage shift register included in the display substrate is shown in FIG.

[0037] Fig.10 for Figure 5B A cross-sectional view of the display substrate along the AA' direction shown;

[0038] Fig.11 A schematic diagram of a display device provided for at least one embodiment of the present disclosure; and

[0039] Fig.12 A flow chart of a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] The present disclosure is described below by several specific embodiments. In order to keep the following description of the embodiments of the present invention clear and concise, the detailed description of known functions and known components may be omitted. When any component of the embodiments of the present invention appears in more than one accompanying drawings, the component is represented by the same reference numeral in each of the accompanying drawings.

[0043] Figure 1 The invention is a circuit diagram of a light emitting control shift register. Figure 2 for Figure 1 The signal timing diagram of the light emitting control shift register is shown below. Figure 1 and Figure 2 The working process of the light emitting control shift register is briefly introduced.

[0044] like Figure 1 As shown, the light emitting control shift register 100 includes 10 transistors (a first transistor T1, a second transistor T2, ..., a tenth transistor T10) and 3 capacitors (a first capacitor C1, a second capacitor C2, and a third capacitor C3). For example, when a plurality of light emitting control shift registers 100 are cascaded, the first electrode of the first transistor T1 in the first stage shift register 100 is configured to be connected to the first trigger signal line ESTV1 to receive the first trigger signal ESTV1, and the first electrode of the first transistor T1 in the other stages of the light emitting control shift register 100 is connected to the previous stage of the light emitting control shift register 100 to receive the first output signal EM output by the previous stage of the light emitting control shift register 100.

[0045] in addition, Figure 1 and Figure 2 CK in the figure represents a first clock signal terminal, ECK represents a first clock signal line and a first clock signal, and the first clock signal terminal CK is connected to the first clock signal line ECK to receive the first clock signal, CB represents a second clock signal terminal, ECB represents a second clock signal line and a second clock signal, and the second clock signal terminal CB is connected to the second clock signal line ECB to receive the second clock signal. For example, the first clock signal ECK and the second clock signal ECB can use pulse signals with a duty cycle greater than 50%; VGH1 represents a first power line and a first power supply voltage provided by the first power line, for example, the first power supply voltage is a DC high level, VGL1 represents a third power line and a second power supply voltage provided by the third power line, for example, the second power supply voltage is a DC low level, and the first power supply voltage is greater than the second power supply voltage; N1, N2, N3 and N4 represent a first node, a second node, a third node and a fourth node, respectively.

[0046] like Figure 1As shown, the gate of the first transistor T1 is connected to the first clock signal terminal CK (i.e., the first clock signal line ECK) to receive the first clock signal, the first electrode of the first transistor T1 is connected to the input terminal IN, and the second electrode of the first transistor T1 is connected to the first node N1. For example, when the light emitting control shift register is a first-stage shift register, the input terminal IN is connected to the first trigger signal line ESTV1 to receive the first trigger signal, and when the light emitting control shift register is a shift register of each stage other than the first-stage shift register, the input terminal IN is connected to the output terminal OUT of its upper-stage light emitting control shift register.

[0047] A gate of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first clock signal line ECK to receive the first clock signal, and a second electrode of the second transistor T2 is connected to the second node N2 .

[0048] A gate of the third transistor T3 is connected to the first clock signal line ECK to receive the first clock signal, a first electrode of the third transistor is connected to the third power line VGL1 to receive the second power voltage, and a second electrode of the third transistor T3 is connected to the second node N2.

[0049] A gate of the fourth transistor T4 is connected to the second clock signal terminal CB (ie, the second clock signal line ECB) to receive the second clock signal, a first electrode of the fourth transistor T4 is connected to the first node N1, and a second electrode of the fourth transistor T4 is connected to a first electrode of the fifth transistor T5.

[0050] A gate electrode of the fifth transistor T5 is connected to the second node N2 , and a second electrode of the fifth transistor T5 is connected to the first power line VGH to receive the first power voltage.

[0051] A gate of the sixth transistor T6 is connected to the second node N2 , a first electrode of the sixth transistor T6 is connected to the second clock signal line ECB to receive the second clock signal, and a second electrode of the sixth transistor T6 is connected to the third node N3 .

[0052] A first end of the first capacitor C1 is connected to the second node N2 , and a second end of the first capacitor C2 is connected to the third node N3 .

[0053] A gate electrode of the seventh transistor T7 is connected to the second clock signal line ECB to receive the second clock signal, a first electrode of the seventh transistor T7 is connected to the third node N3, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0054] A gate of the eighth transistor T8 is connected to the first node N1 , a first electrode of the eighth transistor T8 is connected to the first power line VGH1 to receive the first power voltage, and a second electrode of the eighth transistor T8 is connected to the fourth node N4 .

[0055] A gate of the ninth transistor T9 is connected to the fourth node N4 , a first electrode of the ninth transistor T9 is connected to the first power line VGH1 to receive the first power voltage, and a second electrode of the ninth transistor T9 is connected to the output terminal OUT.

[0056] A first terminal of the third capacitor C3 is connected to the fourth node N4 , and a second terminal of the third capacitor C3 is connected to the first power line VGH1 to receive the first power voltage.

[0057] A gate of the tenth transistor T10 is connected to the first node N1 , a first electrode of the tenth transistor T10 is connected to the third power line VGL1 to receive the second power voltage, and a second electrode of the tenth transistor T10 is connected to the output terminal OUT.

[0058] A first end of the second capacitor C2 is connected to the second clock signal line ECB to receive the second clock signal, and a second end of the second capacitor C2 is connected to the first node N1.

[0059] Figure 1 The transistors in the light emission control shift register 100 shown in FIG. 1 are all described by taking P-type transistors as examples, that is, each transistor is turned on when the gate is connected to a low level, and is turned off when the gate is connected to a high level. At this time, the first electrode can be a source electrode, and the second electrode can be a drain electrode.

[0060] Embodiments of the present disclosure include but are not limited to Figure 1 Configuration method, for example, each transistor in the light emitting control shift register 100 can also use N-type transistors or a mixture of P-type transistors and N-type transistors, and it is only necessary to simultaneously connect the port polarities of the selected type of transistors according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0061] Figure 2 for Figure 1 The signal timing diagram of the light emitting control shift register is shown below. Figure 1 and Figure 2 The working process of the light emitting control shift register is described in detail. For example, the working principle of the first-stage light emitting control shift register 100 is described, and the working principles of the remaining stages of the light emitting control shift register 100 are similar to it, and will not be described in detail. Figure 2 As shown, the working process of the light emitting control shift register includes six stages, namely the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6. Figure 2 The timing waveforms of each signal in each stage are shown.

[0062] In the first stage P1, if Figure 2As shown, the first clock signal ECK is at a low level, so the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 transmits the high-level first trigger signal ESTV1 to the first node N1, so that the level of the first node N1 becomes high, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. In addition, the turned-on third transistor T3 transmits the low-level second power supply voltage VGL1 to the second node N2, so that the level of the second node N2 becomes low, so the fifth transistor T5 and the sixth transistor T6 are turned on. Since the second clock signal ECB is at a high level, the seventh transistor T7 is turned off. In addition, due to the storage effect of the third capacitor C3, the level of the fourth node N4 can be kept at a high level, so that the ninth transistor T9 is turned off. In the first stage P1, since the ninth transistor T9 and the tenth transistor T10 are both turned off, the first output signal output by the output terminal OUT_1 of the light emitting control shift register 100 maintains the previous low level.

[0063] In the second stage P2, if Figure 4 As shown, the second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. Since the first clock signal ECK is at a high level, the first transistor T1 and the third transistor T3 are turned off. Due to the storage function of the first capacitor C1, the second node N2 can continue to maintain the low level of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level first power supply voltage VGH1 is transmitted to the first node N1 through the turned-on fifth transistor T5 and the fourth transistor T4, so that the level of the first node N1 continues to maintain the high level of the previous stage, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. In addition, the low-level second clock signal ECB is transmitted to the fourth node N4 through the turned-on sixth transistor T6 and the seventh transistor T7, so that the level of the fourth node N4 becomes a low level, so the ninth transistor T9 is turned on, and the turned-on ninth transistor T9 outputs the high-level first power supply voltage VGH1, so the first output signal outputted by the output terminal OUT_1 of the light-emitting control shift register 100 in the second stage P2 is a high level.

[0064] In the third stage P3, if Figure 4As shown, the first clock signal ECK is at a low level, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal ECB is at a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. Due to the storage function of the third capacitor C3, the level of the fourth node N4 can maintain the low level of the previous stage, so that the ninth transistor T9 remains in the on state, and the turned-on ninth transistor T9 outputs the high-level first power supply voltage VGH1, so the output signal output by the output terminal OUT_1 of the light emitting control shift register 100 in the third stage P3 is still at a high level. At the same time, in this stage, the output terminal OUT_2 of the second-stage light emitting control shift register 100 outputs a high level (for a specific description, refer to the working process of the first-stage light emitting control shift register in the second stage P2 above).

[0065] In the fourth stage P4, if Figure 4 As shown, the first clock signal ECK is at a high level, so the first transistor T1 and the third transistor T3 are turned off. The second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. Due to the storage function of the second capacitor C2, the level of the first node N1 remains at a high level in the previous stage, so that the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. Due to the storage function of the first capacitor C1, the second node N2 continues to maintain the low level in the previous stage, so that the fifth transistor T5 and the sixth transistor T6 are turned on. In addition, the low-level second clock signal ECB is transmitted to the fourth node N4 through the turned-on sixth transistor T6 and the seventh transistor T7, so that the level of the fourth node N4 becomes a low level, so the ninth transistor T9 is turned on, and the turned-on ninth transistor T9 outputs the high-level first power supply voltage VGH1, so the first output signal output by the output terminal OUT_1 of the light-emitting control shift register 100 in the second stage P2 is still high. Meanwhile, in this stage, the output terminal OUT_2 of the second-stage light emitting control shift register 100 outputs a high level (for a detailed description, please refer to the working process of the first-stage light emitting control shift register in the third stage P3 above).

[0066] In the fifth stage P5, if Figure 4 As shown, the first clock signal ECK is at a low level, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal ECB is at a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. The turned-on first transistor T1 transmits the low-level first trigger signal ESTV to the first node N1, so that the level of the first node N1 becomes a low level.

[0067] For example, in the fifth stage P5, the low level voltage of the first clock signal ECK is -6V, the low level voltage of the first trigger signal ESTV1 is -6V, and the threshold voltage Vth of the first transistor T1 is -1.5V. Since the first transistor T1 is a P-type transistor, in order to turn on the first transistor T1, it is necessary to make the voltage Vgs of the gate and source of the first transistor T1 less than the threshold voltage Vth of the first transistor T1. Therefore, when the first node N1 is charged to -4.5V, the first transistor T1 is turned off, and the charging of the first node N1 is stopped at this time, that is, the low level voltage of the first node N1 is -4.5V at this stage, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on. The turned-on second transistor T2 transmits the low-level first clock signal ECK to the second node N2, so that the level of the second node N2 can be further lowered, so the second node N2 continues to maintain the low level of the previous stage, so that the fifth transistor T5 and the sixth transistor T6 are turned on. In addition, the turned-on eighth transistor T8 transmits the high-level first power supply voltage VGH1 to the fourth node N4, so that the level of the fourth node N4 becomes high, so the ninth transistor T9 is turned off. The turned-on tenth transistor T10 responds to the low level (e.g., -4.5V) of the first node N1 and outputs the low-level second power supply voltage VGL (e.g., -6V). Similarly, the threshold voltage Vth of the tenth transistor T10 is -1.5V. In order to turn on the tenth transistor T10, it is necessary to make the voltage Vgs of the gate and source of the tenth transistor T10 less than the threshold voltage Vth of the tenth transistor T10. Therefore, when the voltage output by the output terminal OUT is -3V, the tenth transistor T10 is turned off, that is, the low-level voltage of the output terminal OUT is -3V at this stage, so the output signal output by the output terminal OUT_1 of the light emitting control shift register 100 in the fifth stage P5 becomes the first low level (e.g., -3V). Meanwhile, in this stage, the output terminal OUT_2 of the second-stage light emitting control shift register 100 outputs a high level (for a detailed description, please refer to the working process of the first-stage light emitting control shift register in the fourth stage P4 above).

[0068] In the sixth stage P6, if Figure 4As shown, the first clock signal ECK is at a high level and the second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. Since the second clock signal ECB changes from a high level in the fifth stage P5 to a low level, for example, the change amount is Δt (for example, greater than 6V), according to the bootstrap effect of the second capacitor C2, the level of the first node N1 changes from a low level (for example, -4.5V) in the fifth stage P5 to a lower low level (for example, -4.5V-Δt), so that the second transistor T2 and the tenth transistor T10 are turned on under the control of the low level (for example, -4.5V-Δt) of the first node N1. According to the conduction characteristics of the tenth transistor T10 described above, the low-level second power supply voltage VGL (for example, -6V) can be fully output to the output terminal OUT. For example, in the sixth stage P6, the voltage output by the output terminal OUT is the second low level (for example, -6V). Meanwhile, in this stage, the output terminal OUT_2 of the second-stage first shift register 100 outputs a low level (eg, -3V, for a detailed description, refer to the working process of the first-stage first shift register in the fourth stage P4 above).

[0069] For example, Figure 1 As shown in FIG. 1 , on the left side of the display substrate, due to the dense wiring, the space left for the first trigger signal line ESTV1 is small, which makes it inconvenient to introduce multiple trigger signal lines. Figure 1 As shown, since there is only one first power line VGH1 and the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are wound to connect to the first power line VGH1, the space occupied by the display substrate in the vertical direction is increased, which is not conducive to the layout design of the display substrate.

[0070] At least one embodiment of the present disclosure provides a display substrate, comprising: a substrate substrate, comprising a pixel array area and a peripheral area; a first scan drive circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are arranged in the peripheral area and located on the first side of the substrate substrate. The first scan drive circuit comprises a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power supply voltages to the plurality of cascaded first shift registers included in the first scan drive circuit; the first signal line group comprises at least one timing signal line, configured to provide at least one timing signal to the plurality of cascaded first shift registers included in the first scan drive circuit; the second signal line group comprises a first trigger signal line, configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers included in the first scan drive circuit, so as to provide a first trigger signal to the first-stage first shift register, and the first trigger signal line is located between the plurality of power supply voltage lines and the pixel array area.

[0071] At least one embodiment of the present disclosure further provides a display device and a manufacturing method corresponding to the above-mentioned display substrate.

[0072] The display substrate provided by the above embodiment of the present disclosure arranges the first trigger signal line between the plurality of power lines and the pixel array area, which facilitates the introduction of the signal line and is conducive to realizing the display of a large-size display panel.

[0073] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0074] At least one embodiment of the present disclosure provides a display substrate. For example, the display substrate can be applied to a single-row single-drive scan drive circuit, that is, the output signal output by the primary shift register drives only one row of pixel units. Since the single-row single-drive scan drive circuit needs to drive half the load as compared to the single-row dual-drive scan drive circuit, it has a stronger driving capability and is more suitable for displaying large-size display panels.

[0075] It should be noted that the display substrate can also be applied to a single-row dual-drive scanning drive circuit, that is, the output signal output by a first-stage shift register can drive two rows of pixel units, and the embodiments of the present disclosure are not limited to this.

[0076] Figure 4 A schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 4 As shown, the display substrate 1 includes: a base substrate 10 , a first scan driving circuit 130 , a plurality of power lines 140 , a first signal line group 150 and a second signal line group 160 .

[0077] For example, the substrate 100 may be made of glass, plastic, quartz, or other suitable materials, which is not limited in the embodiments of the present disclosure. For example, the substrate 10 includes a pixel array area 110 and a peripheral area 120, and a first scan drive circuit 130, a plurality of power lines 140, a first signal line group 150, and a second signal line group 160 are arranged in the peripheral area 120 and located on a first side of the substrate 10, for example, on the left side of the substrate 10.

[0078] For example, the pixel array area 110 includes a plurality of pixel units P arranged in an array. For example, each of the plurality of pixel units P includes a pixel circuit, and may further include a light emitting element (not shown in the figure).

[0079] For example, the first scan driving circuit 130 includes a plurality of cascaded first shift registers 100, for example, including a plurality of Figure 1The shift register 100 shown. For the sake of clarity and brevity, the first shift register 100 is referred to as the shift register 100 below. The following embodiments are the same and will not be described in detail. For example, the output ends of the multiple shift registers 100 are respectively connected to the light-emitting control ends of the pixel circuits of each row in the pixel array area to provide output signals (e.g., light-emitting control signals) to the pixel circuits of each row, thereby driving the light-emitting elements to emit light. For example, the pixel circuit can be a pixel circuit in the art, such as a circuit structure including 2T1C, 4T2C, 8T2C, etc., which will not be described in detail here.

[0080] For example, the first scan driving circuit 130 includes at least one transistor, and the extension direction of the channel of the at least one transistor is parallel to the extension direction of the first signal line group 150 and the second signal line group 160, thereby reducing the area of ​​the first scan driving circuit 130 in the direction perpendicular to the channel length direction, improving process matching, and forming a better channel effect.

[0081] For example, the first scan driving circuit 130 includes a first transistor T1, a second transistor T2, and a third transistor T3, and the first transistor T1, the second transistor T2, and the third transistor T3 are respectively connected to the first signal line group 150, for example, connected to the first clock signal ECK in the first signal line group 150. For example, the extension direction of the channels of the first transistor T1, the second transistor T2, and the third transistor T3 is parallel to the extension direction of the first signal line group 150 and the second signal line group 160. For example, the extension direction of the channel is the extension direction from the first pole to the second pole of the transistor, for example, the extension direction from the first pole to the second pole of the first transistor T1.

[0082] For example, the first scan driving circuit 130 also includes a sixth transistor T6 and a seventh transistor T7, which are respectively connected to the first signal line group 150, and the extension direction of the channels of the sixth transistor T6 and the seventh transistor T7 are parallel to the extension direction of the first signal line group 150 and the second signal line group 160.

[0083] For example, the plurality of power lines 140 are configured to provide a plurality of power supply voltages to the plurality of cascaded shift registers 100 included in the first scan driving circuit 130. For example, a first power supply voltage (eg, having a DC high level) and a second power supply voltage (eg, having a DC low level) are provided.

[0084] The first signal line group 150 includes at least one timing signal line, for example, a first clock signal line ECK and a second clock signal line ECB, and is configured to provide at least one timing signal, for example, the first clock signal ECK and the second clock signal ECB described above, to a plurality of cascaded shift registers 100 included in the first scan driving circuit 130.

[0085] For example, in at least one example, the second signal line group 160 includes a first trigger signal line ESTV1, which is configured to be connected to a first stage shift register of a plurality of cascaded shift registers 100 included in the first scan driving circuit 150 to provide a first trigger signal to the first stage shift register. For example, the first trigger signal line ESTV1 is located between the plurality of power lines 140 and the pixel array area 110. For example, Figure 4 As shown, the first trigger signal line ESTV1 can be located on the right side of the first scanning drive circuit 130, that is, the orthographic projection of the first trigger signal line ESTV1 on the substrate substrate 10 is located between the orthographic projection of the first scanning drive circuit 130 on the substrate substrate 10 and the orthographic projection of the pixel array area 110 on the substrate substrate 10; of course, it can also be located between the transistors of the first scanning drive circuit 130, that is, the orthographic projection of the first trigger signal line ESTV1 on the substrate substrate 10 at least partially overlaps with the orthographic projection of the first scanning drive circuit 130 on the substrate substrate 10, as long as it can be set in an area with sparse wiring to facilitate the introduction of the trigger signal line, the embodiments of the present disclosure are not limited to this.

[0086] It should be noted that the display substrate may further include a plurality of scan drive circuits and a plurality of trigger signal lines respectively connected to the first-stage shift registers of the plurality of scan drive circuits, which is not limited in the embodiments of the present disclosure.

[0087] For example, in some examples, when the display substrate further includes a second scan drive circuit, a third scan drive circuit and a plurality of other scan drive circuits, the display substrate also includes a second trigger signal line ESTV2 connected to the first-stage shift register of the second scan drive circuit, a third trigger signal line connected to the first-stage shift register of the third scan drive circuit and a plurality of other trigger signal lines. For example, the second scan drive circuit, the third scan drive circuit and a plurality of other scan drive circuits have the same structure as the first scan drive circuit, and are arranged in sequence with the first scan drive circuit to jointly drive the pixel array area of ​​the display substrate. For example, the pixel array area includes a plurality of display areas that do not overlap each other (for example, are arranged side by side), and the first scan drive circuit, the second scan drive circuit and the third scan drive circuit and a plurality of other scan drive circuits respectively drive the display areas corresponding thereto.

[0088] For example, when multiple scan drive circuits are included, the second signal line group 160 also includes the multiple trigger signal lines. For example, the multiple trigger signal lines can be located between the multiple power lines 140 and the pixel array area 110, for example, located on the right side of each scan drive circuit, or at least overlap with each scan drive circuit, as long as they can be set in an area where the wiring is not densely packed to facilitate the introduction of the trigger signal lines, and the embodiments of the present disclosure are not limited to this.

[0089] The display substrate provided in the above-mentioned embodiment of the present disclosure avoids the problems of being unable to introduce more signal lines and winding connections due to dense wiring by adjusting the position of the first trigger signal line, which is more conducive to realizing a narrow frame design of the display panel, thereby facilitating the display of a large-size display panel.

[0090] Figure 5A A schematic layout diagram of a display substrate provided for at least one embodiment of the present disclosure. Figure 5B A schematic layout diagram of a display substrate including a first-stage shift register of a second scan driving circuit is shown. Fig.10 for Figure 5B The cross-sectional view of the display substrate along the AA' direction is shown. Of course, Fig.10 Can also be used to explain Figure 5A The stacked structure shown in .

[0091] It should be noted that Figure 5B The stacked structure of the first-stage shift register shown in can be applied to the first-stage shift register of each scanning driving circuit, and it is only necessary to change the connection with the corresponding trigger signal, that is, the first-stage shift register of the first scanning driving circuit is connected to the first trigger signal line ESTV1, the first-stage shift register of the second scanning driving circuit is connected to the second trigger signal line ESTV2..., and so on.

[0092] Fig. 6A , Fig. 7A , Figure 8 and Fig. 9A They are shown respectively Figure 5A The plan view showing the wiring of each layer of the substrate is shown in FIG. Fig. 6A A plan view of a semiconductor layer of a display substrate is provided for at least one embodiment of the present disclosure. Fig. 7A A plan view of a first conductive layer of a display substrate is provided for at least one embodiment of the present disclosure. Figure 8 A plan view of a second conductive layer of a display substrate provided in at least one embodiment of the present disclosure, Fig. 9A A plan view of a third conductive layer of a display substrate provided for at least one embodiment of the present disclosure.

[0093] For example, an interlayer insulating layer (eg, including a first insulating layer, a second insulating layer, a third insulating layer, etc.) may be located 6A to 9A For example, the first insulating layer 350 (eg Fig.10 shown) is located at Fig. 6A The semiconductor layer 310 and Fig. 7A The first conductive layer 320 is shown between the second insulating layer 360 (such as Fig.10 shown) is located at Fig. 7A The first conductive layer 320 and Figure 8 The third insulating layer 370 (such as Fig.10 shown) is located at Figure 8 The second conductive layer 330 and Fig. 9A Between the third conductive layers 340 shown.

[0094] For example, Fig.10 As shown, the display substrate further includes a fourth insulating layer 380 . The fourth insulating layer 380 is located on the third conductive layer 340 and is used to protect the third conductive layer 340 .

[0095] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370 and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other suitable materials, which is not limited to the embodiments of the present disclosure.

[0096] It should be noted that Figure 5A The display substrate shown in the figure takes the layout design of a shift register in the first scan drive circuit and the signal lines connected thereto as an example for explanation. The layout implementation methods of the remaining shift registers at various levels can refer to Figure 5A The layout shown in FIG. 1 is not described in detail here. Of course, other layouts can also be used, and the embodiments of the present disclosure are not limited to this. Of course, the shift registers of each level of the remaining scanning drive circuits can also refer to FIG. Figure 5A The layout shown in FIG. 1 may also adopt other layout forms, and the embodiments of the present disclosure are not limited thereto.

[0097] Combine the following Figures 5A-9A A display substrate provided in at least one embodiment of the present disclosure is introduced in detail.

[0098] For example, Figure 5A The first transistor T1 to the tenth transistor T10 of the shift register 100 shown in FIG. 1 may be formed at Fig. 6A The semiconductor layer 310 is shown in FIG. The semiconductor layer 310 may be formed by patterning a semiconductor material. Fig. 6A As shown, as needed, the semiconductor layer 310 can be in the shape of a short rod or have a curved or bent shape, and can be used to make the active layers of the above-mentioned first transistor T1 to the tenth transistor T10. Each active layer may include a source region, a drain region, and a channel region located between the source region and the drain region. For example, the channel region may be doped with impurities so that it has semiconductor properties; the source region and the drain region are on both sides of the channel region, and may be doped with impurities and therefore have conductivity. For example, the source region corresponds to the source of the transistor (or called the first electrode), and the drain region corresponds to the drain of the transistor (or called the second electrode). For example, as Fig.10 As shown, taking the first transistor T1 as an example, the active layer of the first transistor T1 includes a source region S1, a drain region D1 (such as Fig.10 The first transistor T1 further includes a gate G1, wherein the gate G1 is located in the first conductive layer 320, which will be described below and will not be repeated here. It should be noted that the drain region D1 of the first transistor is not located in the first conductive layer 320. Figure 5B In the cross-section along the AA` direction, in order to ensure clear description, Fig.10 In FIG. 1 , the drain region D1 of the first transistor T1 is added with a dotted line.

[0099] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0100] It should be noted that in other examples, the first electrode and the second electrode of each transistor may also be located in other conductive layers, and connected to the corresponding active layer through vias in the insulating layer between the transistor and the semiconductor layer. The embodiments of the present disclosure are not limited to this.

[0101] Fig. 7A The first conductive layer 320 of the display substrate is shown, and the first conductive layer 320 is disposed on the first insulating layer, thereby being insulated from the semiconductor layer 310. For example, the first conductive layer 320 may include first electrodes CE11, CE12, CE13 of the first capacitor C1 to the third capacitor C3 and the gates of the first transistor T1 to the tenth transistor T10, and the first insulating layer also serves as a gate insulating layer. Fig. 7A As shown, the gates of the first transistor T1 to the tenth transistor T10 are the portions where the semiconductor layer structures of the respective transistors overlap with the wiring on the first conductive layer 320 .

[0102] Figure 8 The second conductive layer 330 of the display substrate is shown, and the second conductive layer 330 includes second electrodes CE21, CE22, and CE23 of the first capacitor C1 to the third capacitor C3. For example, the second electrode CE21 at least partially overlaps with the first electrode CE11 to form the first capacitor C1, the second electrode CE22 at least partially overlaps with the first electrode CE12 to form the second capacitor C2, and the second electrode CE23 at least partially overlaps with the first electrode CE13 to form the third capacitor C3.

[0103] Fig. 9AThe third conductive layer 340 of the display substrate is shown, and the third conductive layer 340 includes a first signal line group 150, a plurality of power lines 140, and a second signal line group 160. It should be noted that the third conductive layer also includes conductive connecting parts connecting various transistors, capacitors, and signal lines. Figure 5A and 9A As shown, the first signal line group 150, multiple power lines 140 and the second signal line group 160 are connected to the transistors that need to be connected to them in the remaining layers through at least one via, and the transistors are also connected through at least one via, or bridged by a conductive connection part, which will not be repeated here.

[0104] For example, the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy or any other suitable material, which is not limited in the embodiments of the present disclosure. For example, the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be repeated here.

[0105] Figure 5A For the above Fig. 6A The semiconductor layer 310 shown Fig. 7A The first conductive layer 320 shown, Figure 8 The second conductive layer 330 and Fig. 9A Schematic diagram of the stacking position relationship of the third conductive layer 340 shown.

[0106] like Figure 5A and 9A As shown, in at least one example, the display substrate includes a first signal line group 150 (for example, including a first clock signal line ECK and a second clock signal line ECB) and a plurality of power lines 140 (for example, including a third power line VGL1, a first power line VGH1 and a fourth power line VGL2) sequentially arranged along the row direction and a second signal line group 160 (for example, including a first trigger signal line ESTV1). It should be noted that when the second scan drive circuit is included, for example, the second signal line group 160 also includes a second start signal line ESTV2.

[0107] In some embodiments, Figure 4 or Figure 5A As shown, the second signal line group 160 is located on one side of the first scan driving circuit 130 close to the pixel array area 110, and the first signal line group 150 is located on the other side of the first scan driving circuit 130 opposite to the side where the second signal line group 160 is located. Figure 4 or Figure 5A As shown, the second signal line group 160 is located on the right side of the shift register 100 , and the first signal line group 150 is located on the left side of the shift register 100 .

[0108] In this embodiment, by arranging the second signal line group 160 including the first trigger signal line ESTV1 and the second trigger signal line ESTV2 on the right side of the shift register, that is, separately from the first signal group 150 and the plurality of power lines 140, it is possible to avoid dense routing due to too many signal lines on the left side, thereby avoiding the problem of too little space left for the trigger signal line due to dense routing and affecting the introduction of other signal lines.

[0109] In other examples, such as Figure 5A As shown, the plurality of power lines 140 include a first power line VGH1, a second power line VGH2, a third power line VGL1 and a fourth power line VGL2. For example, the first power line VGH1 and the second power line VGH2 provide the same first power voltage, for example, a DC high voltage.

[0110] For example, the orthographic projection of the first power line VGH1 on the substrate 10 partially overlaps with the orthographic projection of the first scan driving circuit on the substrate 10, and the orthographic projection of the second power line VGH2 on the substrate 10 is located between the orthographic projection of the first power line VGH1 on the substrate 10 and the orthographic projection of the second signal line group 160 on the substrate.

[0111] It should be noted that the orthographic projection of the first scan driving circuit on the base substrate 10 is not a continuous area, therefore, the orthographic projection of the first power line VGH1 on the base substrate 10 only needs to overlap with the orthographic projection of some transistors or capacitors of the first scan driving circuit on the base substrate 10. The embodiments of the present disclosure are not limited to this. Figure 5A As shown, the orthographic projection of the first power line VGH1 on the substrate 10 overlaps with the routing on the first conductive layer 320, for example, partially overlaps with the routing connecting the gate of the third transistor T3 and the gate of the first transistor T1, the routing connecting the gate of the fourth transistor T4, the routing connecting the gate of the fifth transistor T5, and the routing connecting the gate of the second transistor T2.

[0112] For example, Figure 5A As shown, each shift register of the first scan drive circuit includes a first constituent transistor connected to the first power line VGH1 and a second constituent transistor and a third constituent transistor connected to the second power line VGH2. For example, the fifth transistor T5 is an example of the first constituent transistor, the eighth transistor T8 is an example of the second constituent transistor, and the ninth transistor T9 is an example of the third constituent transistor. The following is an example in which the first constituent transistor is the fifth transistor T5, the second constituent transistor is the eighth transistor T8, and the third constituent transistor is the ninth transistor T9, which is not limited to the embodiments of the present disclosure. The following embodiments are the same as this and will not be repeated.

[0113] For example, the orthographic projection of the fifth transistor T5 on the substrate 10 is located between the orthographic projection of the first signal line group 150 on the substrate 10 and the orthographic projection of the first power line VGH1 on the substrate 10 and is close to the orthographic projection of the first power line VGH1 on the substrate 10, and the orthographic projections of the eighth transistor T8 and the ninth transistor T9 on the substrate 10 are located between the orthographic projection of the first power line VGH1 on the substrate 10 and the orthographic projection of the second power line VGH2 on the substrate 10 and are close to the orthographic projection of the second power line VGH2 on the substrate 10. That is, the first power line VGH1 is set at a position close to the fifth transistor T5, and the eighth transistor T8 and the ninth transistor T9 are set at a position close to the second power line VGH2, so that the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 can be avoided from being wound in order to be connected to one power line (for example, the first power line VGH1), thereby avoiding the space occupied by the winding in the vertical direction of the display substrate.

[0114] For example, the third power line VGL1 and the fourth power line VGL2 are configured to provide the same second power supply voltage, for example, a DC low voltage. For example, the first power supply voltage is higher than the second power supply voltage. For example, the orthographic projection of the fourth power line VGL2 on the substrate 10 partially overlaps with the orthographic projection of the first scan drive circuit on the substrate 10, and the orthographic projection of the third power line VGL1 on the substrate 10 is located between the orthographic projection of the third power line VGL1 on the substrate 10 and the orthographic projection of the first signal line group 150 on the substrate 10.

[0115] As described above, the orthographic projection of the first scan driving circuit on the base substrate 10 is not a continuous area, therefore, the orthographic projection of the fourth power line VGL2 on the base substrate 10 only needs to overlap with the orthographic projection of some transistors or capacitors of the first scan driving circuit on the base substrate 10. The embodiments of the present disclosure are not limited to this. Figure 5A As shown, the orthographic projection of the fourth power line VGL2 on the base substrate 10 overlaps with the routing on the first conductive layer 320, for example, overlaps with the routing connecting the gate of the eighth transistor T8, the routing connecting the gate of the tenth transistor T10, and the first electrode CE12 of the second capacitor C2.

[0116] For example, each shift register of the first scan drive circuit further includes a fourth constituent transistor connected to the third power line VGL1, and includes a fifth constituent transistor connected to the fourth power line VGL2. For example, the third transistor T3 is an example of the fourth constituent transistor, and the tenth transistor T10 is an example of the fifth constituent transistor. The following is described by taking the third transistor T3 as the fourth constituent transistor and the tenth transistor T10 as the fifth constituent transistor as an example, and the embodiments of the present disclosure are not limited to this. The following embodiments are the same as this and will not be repeated.

[0117] For example, the orthographic projection of the third transistor T3 on the substrate substrate 10 is located on a side of the orthographic projection of the third power line VGL1 on the substrate substrate 10 away from the orthographic projection of the first signal line group 150 on the substrate substrate 10, and is close to the orthographic projection of the third power line VGL1 on the substrate substrate 10. For example, the orthographic projection of the tenth transistor T10 on the substrate substrate 10 is located between the orthographic projection of the fourth power line VGL2 on the substrate substrate 10 and the orthographic projection of the second signal line group 160 on the substrate substrate 10, and is close to the orthographic projection of the tenth transistor T10 on the substrate substrate 10. That is, the third power line VGL1 is arranged at a position close to the third transistor T3, and the tenth transistor T10 is arranged at a position close to the fourth power line VGL2, so that the third transistor T3 and the tenth transistor T10 can be avoided from being wound in order to be connected to one power line (for example, the third power line VGL1) or respectively to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display substrate, thereby avoiding the space occupied by the winding in the vertical direction of the display substrate.

[0118] In at least one embodiment of the present disclosure, by arranging the first power line VGH1, the second power line VGH2, the third power line VGL1 and the fourth power line VGL2 respectively next to the transistors connected thereto, it is possible to avoid winding the transistors in order to connect them to one power line, thereby avoiding the space occupied by the winding in the vertical direction of the display substrate, which is conducive to realizing a narrow bezel design.

[0119] In some other embodiments, the pixel array area 110 includes a first display area and a second display area (not shown) that are parallel to each other and do not overlap, and the first scan driving circuit 130 is connected to the first display area to drive the first display area to display.

[0120] The display substrate further includes a second scanning drive circuit disposed in the peripheral region and located on one side of the base substrate. For example, the second scanning drive circuit is arranged in sequence with the first scanning drive circuit along a scanning direction (for example, a column direction) of the pixel array, and is connected to the second display region to drive the second display region to display. For example, the second scanning drive circuit includes a plurality of cascaded second shift registers (for example, including Figure 5B For example, the structure of the second shift register is the same as the circuit structure of the first shift register, and both use Figure 1 The circuit structure of the shift register shown in the figure, of course, the structure of the second shift register and the circuit structure of the first shift register may also be different, and the embodiments of the present disclosure are not limited to this. For the sake of clarity and simplicity, the second shift register is also referred to as the shift register below. The following embodiments are the same as this and will not be repeated.

[0121] For example, the display substrate is a folding display substrate, and further includes a folding line located between the first display area and the second display area. For example, the second resistor R2 is located in the extension direction of the folding line, and the extension direction of the folding line is perpendicular to the extension direction of the first signal line group 150 and the second signal line group 160, so that the signal line can run through the entire display substrate. For example, the extension direction of the first signal line group 150 and the second signal line group 160 is Figure 4 The vertical direction is the extending direction of the folding line which is the horizontal direction.

[0122] For example, Figure 5B As shown, the second signal line group 160 also includes a second trigger signal line ESTV2, which is connected to the first stage shift register 132 of the plurality of cascaded shift registers included in the second scan drive circuit to provide a second trigger signal to the first stage shift register 132 included in the second scan drive circuit. For example, the first trigger signal line ESTV1 and the second trigger signal line ESTN2 are adjacent and arranged side by side. The first trigger signal line ESTV1 and the second trigger signal line ESTV2 extend in parallel, and the extension lengths of the two are the same as the arrangement lengths of the first scan drive circuit and the second scan drive circuit, for example, they can run through the entire display panel, so as to avoid the different wiring resistances caused by the different lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2, so as to affect the trigger signals transmitted respectively. Correspondingly, for example, when a plurality of scan drive circuits are included, the remaining trigger signal lines can also be adjacent to the first trigger signal line ESTV1 and the second trigger signal line ESTV2 and arranged side by side, and their extension lengths can be the same as the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.

[0123] It should be noted that Figure 5B Only the last stage shift register 131 of the first scanning driving circuit and the first stage shift register 132 of the second scanning driving circuit are schematically shown. The layout of the other stages of the shift registers can refer to Figure 5A The layout shown will not be described in detail.

[0124] Figure 6B , Figure 7B , Figure 8 and Fig. 9B They are shown respectively Figure 5B The plan view of each layer wiring of the first stage shift register included in the display substrate is shown in FIG. Figure 5B-Figure 9B A display substrate provided in at least one embodiment of the present disclosure is introduced in detail.

[0125] It should be noted that Figure 6B The semiconductor layer shown is Fig. 6AThe semiconductor layer shown is similar, except that it further includes at least one resistor (e.g., a second resistor R2); Figure 7B The first conductive layer 320 is shown Fig. 7A The first conductive layer 320 shown is similar, except that it also includes a first connecting line L1 and a second connecting line L2; Fig. 9B The third conductive layer 340 and Fig. 9A The third conductive layer 340 shown is similar, except that it also includes a first conductive connection portion 341 and a second conductive connection portion 342 , and the specific connection relationship will be described in detail below.

[0126] For example, when the last stage shift register 131 of the first scan driving circuit outputs an output signal, the second trigger signal line ESTV2 provides a second trigger signal to the first stage shift register 132 of the second scan driving circuit to drive the multiple cascaded shift registers included therein to output the output signal row by row. It should be noted that, while the first trigger signal line ESTV1 provides a first trigger signal to the first scan driving circuit, the second trigger signal line ESTV2 provides a second trigger signal to the second scan driving circuit, thereby simultaneously driving the first scan driving circuit and the second scan driving circuit to work, as long as the pixel units in the pixel array area of ​​the display substrate can be driven to display a normal image, the embodiments of the present disclosure are not limited to this.

[0127] For example, in some examples, such as Figure 3 As shown, the display substrate further includes at least one first resistor R1 (such as Figure 3 As shown). For example, the first resistor R1 is located on a side of the first scan driving circuit 130 away from the first stage first shift register. For example, the first trigger signal line ESTV1 is connected to the first stage shift register of the first scan driving circuit 130 (for example, the first transistor T1 of the first stage shift register) through the first resistor R1. Figure 5B As shown, when the display substrate includes the second scan drive circuit 230, the display substrate may further include at least one second resistor R2. For example, the second resistor R2 is located between the last stage first shift register of the first scan drive circuit 130 and the first stage second shift register of the second scan drive circuit 230. For example, the second trigger signal line ESTV2 is connected to the first stage second shift register of the second scan drive circuit 230 through the second resistor R2, for example, connected to the first transistor T1 of the first stage shift register 132 of the second scan drive circuit 230.

[0128] For example, the resistance value of the first resistor R1 is different from the resistance value of the second resistor R2. For example, in some examples, the first trigger signal line ESTV1 is connected to the controller 20 from the upper side of the display substrate to receive the first trigger signal, and the second trigger signal line ESTV2 passes through the middle of the display substrate and is connected to the controller to receive the second trigger signal, so that the wiring resistance (load) of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 is different, so, for example, when the load of the first trigger signal line ESTV1 is greater than the load of the second trigger signal line ESTV2, the first resistor R1 is less than the second resistor R2, so that the resistance value of the wiring resistance on the first trigger signal line ESTV1 plus the resistance value of the first resistor is approximately equal to the resistance value of the wiring resistance on the second trigger signal line ESTV1 plus the resistance value of the second resistor. For example, in some examples, the resistance of the first resistor R1 is 5000 ohms, the resistance of the second resistor R2 is 5500 ohms, the resistance of the wiring resistance on the first trigger signal line ESTV1 is 1000 ohms, and the resistance of the wiring resistance on the second trigger signal line ESTV1 is 500 ohms.

[0129] It should be noted that when the display substrate includes multiple scan drive circuits, the display substrate may also include multiple resistors to respectively connect the first-stage shift registers of the multiple scan drive circuits and the corresponding trigger signal lines. For example, when the display substrate includes multiple scan drive circuits such as a third scan drive circuit and a fourth scan drive circuit, the display substrate may also include a third resistor, a fourth resistor, etc. respectively connected to the first transistor T1 of the first-stage shift register thereof. The embodiments of the present disclosure are not limited to this. For example, the settings of the remaining multiple resistors may refer to the settings of the first resistor and the second resistor R2, and will not be described in detail.

[0130] For example, the first resistor and the second resistor may be the same or different, depending on the actual situation, and the embodiments of the present disclosure are not limited to this. For example, the materials of the first resistor and the second resistor may be semiconductor materials, which may be arranged in the same layer as the active layer of the transistor. For example, the first resistor and the second resistor are located Figure 6B The semiconductor layer shown.

[0131] because Figure 5B The connection method of the second resistor is shown in FIG. Figure 5B The second resistor R2 shown in FIG. 1 is used as an example for explanation. Fig.10 for Figure 5B The cross-sectional view of the display substrate along the AA' direction shown in FIG. Figure 5B and Fig.10 The connection method of each resistor is described in detail, taking the second resistor as an example.

[0132] like Figure 5B and Fig.10 As shown, the second resistor R2 is located between the substrate 10 and the second signal line group 160 in a direction perpendicular to the substrate 10 (i.e., located in the semiconductor layer 310), and the orthographic projection of the second resistor R2 on the substrate 10 is located on the side of the orthographic projection of the second signal line group 160 on the substrate 10 away from the pixel array area. Correspondingly, the first resistor is located between the substrate 10 and the second signal line group 160 in a direction perpendicular to the substrate 10 (i.e., located in the semiconductor layer 310), and the orthographic projection of the first resistor on the substrate 10 is located on the side of the orthographic projection of the second signal line group 160 on the substrate 10 away from the pixel array area. It should be noted that the first resistor and the second resistor R2 can also be set at other suitable positions, not limited to Figure 5B The position shown only needs to be located at a position convenient for connecting the trigger signal line and the first transistor T1, and the embodiments of the present disclosure are not limited to this.

[0133] like Figure 5B As shown, the display substrate further includes at least one first connection line L1 and at least one second connection line L2. The first connection line L1 connects one end of the second resistor R2 to the first stage shift register (e.g., the first transistor T1) of the second scan drive circuit, and the second connection line L2 connects the other end of the second resistor R2 to the second trigger signal line ESTV2.

[0134] It should be noted that the display substrate also includes a plurality of first connecting lines and second connecting lines corresponding one to one with resistors corresponding to other scanning drive circuits. The first resistor or other resistors are connected to the corresponding scanning drive circuits and trigger signal lines through the corresponding first connecting lines and second connecting lines. For example, the first connecting line connects one end of the first resistor to the first-stage shift register of the first scanning drive circuit, and the second connecting line connects the other end of the first resistor to the first trigger signal line, which will not be repeated here.

[0135] For example, the first connection line L1 and the second connection line L2 are located on a side of the second resistor R2 away from the base substrate 10, that is, the first connection line L1 and the second connection line L2 are located on Figure 7B The first conductive layer 320 shown can therefore avoid signal confusion caused by crossing the fourth power line VGL2 when it is disposed on the third conductive layer 340 .

[0136] For example, the display substrate further includes at least one first conductive connection portion L3 and a second conductive connection portion L4, so that each resistor is connected to the first connection line and the second connection line in a bridge manner. For example, the first conductive connection portion L3 and the second conductive connection portion L4 are located on a side of the first connection line L1 and the second connection line L2 away from the base substrate 10, and are arranged on the same layer as the plurality of power lines 140, the first signal line group 150 and the second signal line group 160, that is, the first conductive connection portion L3 and the second conductive connection portion L4 are located as shown in FIG. Fig. 9B A third conductive layer 340 is shown.

[0137] For example, as described above, the display substrate 1 further includes a first insulating layer 350, a second insulating layer 360, and a third insulating layer 370. For example, the first insulating layer 350 is located between the second resistor R2 (i.e., the semiconductor layer 310) and the first connecting line L1 and the second connecting line L2 (i.e., the first conductive layer 320) in a direction perpendicular to the base substrate 10, and the second insulating layer 360 is located between the first connecting line L1 and the second connecting line L2 (i.e., the first conductive layer 320) and the first conductive connecting portion L3 and the second conductive connecting portion L4 (i.e., the third conductive layer 340) in a direction perpendicular to the base substrate 10. It should be noted that between the second insulating layer 360 and the third conductive layer 340, there is also Figure 8 The second conductive layer 330 and the third insulating layer 370 located between the second conductive layer 330 and the third conductive layer 340 are shown in FIG. 3 . For a detailed introduction, please refer to the above description, which will not be repeated here.

[0138] For example, Figure 5B and Fig.10 As shown, one end of the first conductive connection portion L3 is connected to one end of the first connection line L1 through a via hole 133 penetrating the second insulating layer 360 (and the third insulating layer 370), and the other end of the first conductive connection portion L3 is connected to one end of the second resistor R2 through a via hole 134 penetrating the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). For example, the other end of the first connection line L1 is connected to the first stage shift register (for example, the source S1 of the first transistor T1) of the first scan driving circuit through a via hole 135 penetrating the second insulating layer 360 and the third insulating layer 360 and through a via hole 139 penetrating the first insulating layer 350, the second insulating layer 360 and the third insulating layer 360. For example, when the orthographic projection of the other end of the first connecting line L1 on the base substrate 10 at least partially overlaps with the orthographic projection of the source S1 of the first transistor T1 on the base substrate 10, the other end of the first connecting line L1 may also be connected to the source S1 of the first transistor T1 through a via (not shown in the figure) penetrating the first insulating layer 350, and the embodiments of the present disclosure are not limited to this.

[0139] One end of the second conductive connection portion L4 is connected to one end of the second connection line L2 through a via 136 penetrating the second insulating layer 350 (and the third insulating layer 360), and the other end of the second conductive connection portion L4 is connected to the other end of the second resistor R2 through a via 137 penetrating the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). The other end of the second connection line L2 is connected to the second trigger signal line ESTV2 through a via 138 penetrating the second insulating layer 360 and the third insulating layer 370.

[0140] It should be noted that the display substrate also includes a plurality of first conductive connection parts and second conductive connection parts corresponding to the resistors corresponding to other scanning driving circuits. The first resistor or other resistors are connected through the corresponding first conductive connection parts and second conductive connection parts and the corresponding first connection lines and second connection lines, which will not be repeated here.

[0141] For example, one end of the first conductive connection part is connected to one end of the first connection line through a via penetrating the second insulating layer, the other end of the first conductive connection part is connected to one end of the first resistor through a via penetrating the first insulating layer and the second insulating layer, and the other end of the first connection line is connected to the first-stage shift register of the first scan drive circuit; one end of the second conductive connection part is connected to one end of the second connection line through a via penetrating the second insulating layer, the other end of the second conductive connection part is connected to the other end of the first resistor through a via penetrating the first insulating layer and the second insulating layer, and the other end of the second connection line is connected to the first trigger signal line through a via penetrating the second insulating layer.

[0142] In the embodiments of the present disclosure, the first-stage shift register of each scanning driving circuit is connected to the corresponding trigger signal through each resistor, which can avoid the influence of static electricity generated at the moment when the device is powered on on various signals (for example, trigger signals, clock signals, etc.), thereby making the output signal output by the scanning driving circuit more accurate and improving the display quality of the display panel.

[0143] At least one embodiment of the present disclosure further provides a display device. Fig.11 Schematic diagram of a display device provided by at least one embodiment of the present disclosure. Fig.11 As shown, the display device 2 includes a display substrate 1 provided by any embodiment of the present disclosure, for example, Figure 4 , Figure 5A or Figure 5B The display substrate 1 shown in FIG.

[0144] It should be noted that the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 can also include other components, which are not limited in the embodiments of the present disclosure.

[0145] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device. To realize the substrate function of the display device, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0146] The technical effects of the display device 2 provided in the above embodiment may refer to the technical effects of the display substrate 1 provided in the embodiment of the present disclosure, which will not be described in detail here.

[0147] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. Fig.12 A flowchart of a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure. For example, the manufacturing method can be used to manufacture a display substrate provided in any embodiment of the present disclosure. For example, it can be used to manufacture Figure 5A or Figure 5B The display substrate shown in .

[0148] like Fig.12 As shown, the method for manufacturing the display substrate includes steps S110 to S120.

[0149] Step S110: providing a substrate.

[0150] Step S120: forming a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group in the peripheral area of ​​the base substrate and on the first side of the base substrate.

[0151] For step S110 , for example, the base substrate 10 may be made of glass, plastic, quartz, or other suitable materials, which is not limited in the embodiments of the present disclosure. For example, the base substrate 10 includes a pixel array area 110 and a peripheral area 120 .

[0152] For step S120 , for example, the first scan driving circuit 130 , the plurality of power lines 140 , the first signal line group 150 and the second signal line group 160 are disposed in the peripheral region 120 and located on a first side of the base substrate 10 , for example, on a left side of the base substrate 10 .

[0153] For example, the first scan driving circuit 130 includes a plurality of cascaded shift registers 100, for example, including a plurality of Figure 1For example, the first transistor T1 to the tenth transistor T10 of the shift register can be formed in Fig. 6A On the semiconductor layer 310 shown. For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0154] For example, the first electrodes CE11, CE12, CE13 of the first capacitor C1 to the third capacitor C3 and the gates of the first transistor T1 to the tenth transistor T10 may be formed at Fig. 7A The first conductive layer 320 is shown. Fig. 7A As shown, the gates of the first transistor T1 to the tenth transistor T10 are the portions where the semiconductor layer structures of the respective transistors overlap with the wiring on the first conductive layer 320 .

[0155] For example, the second electrodes CE21, CE22, and CE23 of the first capacitor C1 to the third capacitor C3 may be formed at Figure 8 The second conductive layer 330 is shown. For example, the second electrode CE21 at least partially overlaps with the first electrode CE11 to form a first capacitor C1, the second electrode CE22 at least partially overlaps with the first electrode CE12 to form a second capacitor C2, and the second electrode CE23 at least partially overlaps with the first electrode CE13 to form a third capacitor C3.

[0156] For example, the plurality of power lines 140, the first signal line group 150, and the second signal line group may be formed on Fig. 9A The third conductive layer 340 shown in FIG. It should be noted that the third conductive layer also includes conductive connecting portions connecting various transistors, capacitors and signal lines. Figure 5A and 9A As shown, the first signal line group 150, multiple power lines 140 and the second signal line group 160 are connected to the transistors that need to be connected to them in the remaining layers through at least one via, and the transistors are also connected through at least one via, or bridged by a conductive connection part, which will not be repeated here.

[0157] For example, the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy or any other suitable material, which is not limited in the embodiments of the present disclosure. For example, the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be repeated here.

[0158] For example, the plurality of power lines 140 are configured to provide power voltages to the plurality of cascaded shift registers 100 included in the first scan driving circuit 130. For example, a first power voltage (eg, having a DC high level) and a second power voltage (eg, having a DC low level) are provided.

[0159] For example, the first signal line group 150 includes at least one timing signal line, for example, a first clock signal line ECK and a second clock signal line ECB, configured to provide timing signals, for example, the first clock signal ECK and the second clock signal ECB described above, to a plurality of cascaded shift registers 100 included in the first scan driving circuit 130.

[0160] For example, in at least one example, the second signal line group 160 includes a first trigger signal line ESTV1, which is configured to be connected to a first stage shift register of a plurality of cascaded shift registers 100 included in the first scan driving circuit 150 to provide a first trigger signal to the first stage shift register. For example, the first trigger signal line ESTV1 is located between the plurality of power lines 140 and the pixel array area 110.

[0161] In some embodiments, Figure 4 or Figure 5A As shown, the second signal line group 160 is formed on one side of the first scan driving circuit 130 close to the pixel array area 110, and the first signal line group 150 is formed on the other side of the first scan driving circuit 130 opposite to the side where the second signal line group 160 is located. Figure 4 or Figure 5A As shown, the second signal line group 160 is located on the right side of the shift register 100 , and the first signal line group 150 is located on the left side of the shift register 100 .

[0162] In this embodiment, by setting the first trigger signal line ESTV1 on the right side of the shift register, that is, separately from the first signal group 150 and the multiple power lines 140, it is possible to avoid dense routing due to too many signal lines on the left side, thereby avoiding the problem of too little space left for the trigger signal line due to dense routing and affecting the introduction of other signal lines.

[0163] For example, step S120 further includes forming a first power line VGH1, a second power line VGH2, and a third power line VGL1 on the base substrate 10, and forming a fifth transistor T5 connected to the first power line VGH1, an eighth transistor T8 and a ninth transistor T9 connected to the second power line VGH2, a third transistor T3 connected to the third power line VGHL1, and a tenth transistor T10 connected to the fourth power line VGL2 on the base substrate 10. For example, the first power line VGH1 and the second power line VGH2 provide the same first power supply voltage, for example, a DC high voltage.

[0164] For example, the orthographic projection of the first power line VGH1 on the substrate 10 partially overlaps with the orthographic projection of the first scan driving circuit on the substrate 10, and the orthographic projection of the second power line VGH2 on the substrate 10 is located between the orthographic projection of the first power line VGH1 on the substrate 10 and the orthographic projection of the second signal line group 160 on the substrate.

[0165] For example, the first power line VGH1 is formed near the fifth transistor T5, and the second power line VGH2 is formed near the eighth transistor T8 and the ninth transistor T9, thereby avoiding the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 from being wound in order to be connected to one power line (for example, the first power line VGH1), thereby avoiding the space occupied by the winding in the vertical direction of the display substrate.

[0166] For example, the third power line VGL1 and the fourth power line VGL2 provide the same second power supply voltage, for example, a DC low voltage. For example, the first power supply voltage is higher than the second power supply voltage. For example, the orthographic projection of the fourth power line VGL2 on the substrate 10 partially overlaps with the orthographic projection of the first scan drive circuit on the substrate 10, and the orthographic projection of the third power line VGL1 on the substrate 10 is located between the orthographic projection of the third power line VGL1 on the substrate 10 and the orthographic projection of the first signal line group 150 on the substrate 10.

[0167] For example, the third power line VGL1 is formed at a position close to the third transistor T3, and the fourth power line VGL2 is formed at a position close to the tenth transistor T10, thereby avoiding the third transistor T3 and the tenth transistor T10 from being wound in order to be connected to one power line (for example, the third power line VGL1) or to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display substrate, respectively, thereby avoiding the space occupied by the winding in the vertical direction of the display substrate.

[0168] For example, in some examples, the method for manufacturing the display substrate further includes: forming a second scan drive circuit in the peripheral area and on the first side of the base substrate 10. For example, the second scan drive circuit includes a plurality of cascaded shift registers (for example, including Figure 5B For example, the first stage shift register 132 shown in FIG. Figure 5B As shown, the second signal line group 160 also includes a second trigger signal line ESTV2, which is connected to the first stage shift register 132 of the plurality of cascaded shift registers included in the second scan driving circuit to provide a second trigger signal to the first stage shift register 132 included in the second scan driving circuit.

[0169] For example, the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are the same as the arrangement lengths of the first scan drive circuit and the second scan drive circuit, thereby avoiding the different wiring resistances caused by the different extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2, which affects the trigger signals transmitted respectively. Accordingly, for example, when multiple scan drive circuits are included, the extension lengths of the remaining trigger signal lines can be the same as the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.

[0170] For example, in some examples, the method for manufacturing the display substrate further includes: forming at least one first resistor and at least one second resistor in a direction perpendicular to the base substrate 10 and between the base substrate 10 and the second signal line group 160 .

[0171] It should be noted that when the display substrate includes multiple scan driving circuits (for example, also including a third scan driving circuit, a fourth scan driving circuit, etc.), the method for manufacturing the display substrate also includes: forming resistors corresponding to the multiple scan driving circuits in a direction perpendicular to the base substrate 10 and between the base substrate 10 and the second signal line group, and the embodiments of the present disclosure are not limited to this.

[0172] like Figure 5B and Fig.10 As shown, the second resistor R2 is located between the substrate 10 and the second signal line group 160 in a direction perpendicular to the substrate 10 (i.e., located in the semiconductor layer 310), and the orthogonal projection of the second resistor R2 on the substrate 10 is located on the side of the orthogonal projection of the second signal line group 160 on the substrate 10 away from the pixel array area. Correspondingly, the first resistor is located between the substrate 10 and the second signal line group 160 in a direction perpendicular to the substrate 10, and the orthogonal projection of the first resistor on the substrate 10 is located on the side of the orthogonal projection of the second signal line group 160 on the substrate 10 away from the pixel array area. It should be noted that the first resistor and the second resistor R2 can also be set at other suitable positions, not limited to Figure 5B Position shown.

[0173] For example, in some examples, the method for manufacturing the display substrate further includes: forming at least one first connection line and at least one second connection line on a side of the first resistor R1 and the second resistor R2 away from the base substrate 10, that is, on the first conductive layer 320. Therefore, it is possible to avoid signal confusion caused by crossing the fourth power line VGL2 when it is arranged on the third conductive layer 340.

[0174] For example, the first connecting line connects one end of the first resistor to the first-stage shift register of the first scanning driving circuit, and the second connecting line connects the other end of the first resistor to the first trigger signal line; the first connecting line L1 connects one end of the second resistor R2 to the first-stage shift register of the second scanning driving circuit (for example, the first transistor T1), and the second connecting line L2 connects the other end of the second resistor R2 to the second trigger signal line ESTV2.

[0175] For example, in some examples, the method for manufacturing the display substrate also includes: forming a first conductive connection portion L3 and a second conductive connection portion L4 on the base substrate 10, which are arranged on the same layer as the multiple power lines 140, the first signal line group 150 and the second signal line group 160; forming a first insulating layer 350 in a direction perpendicular to the base substrate 10 and between the first resistor R1 (i.e., the semiconductor layer 310) and the first connection line L1 and the second connection line L2 (the first conductive layer 320); forming a second insulating layer 360 in a direction perpendicular to the base substrate 10 and between the first connection line L1 and the second connection line L2 (the first conductive layer 320) and the first conductive connection portion L3 and the second conductive connection portion L4 (i.e., the third conductive layer 340). It should be noted that the method for manufacturing the display substrate also includes forming a first conductive connection portion L3 and a second conductive connection portion L4 between the second insulating layer 360 and the third conductive layer 340 as shown in FIG. Figure 8 The second conductive layer 330 and the third insulating layer 370 located between the second conductive layer 330 and the third conductive layer 340 are shown in FIG. 3 . For a detailed introduction, please refer to the above description, which will not be repeated here.

[0176] For example, Figure 5B and Fig.10As shown, one end of the first conductive connection portion L3 is connected to one end of the first connection line L1 through a via hole 133 penetrating the second insulating layer 360 (and the third insulating layer 370), and the other end of the first conductive connection portion L3 is connected to one end of the second resistor R2 through a via hole 134 penetrating the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). For example, the other end of the first connection line L1 is connected to the first stage shift register (for example, the source S1 of the first transistor T1) of the first scan driving circuit through a via hole 135 penetrating the second insulating layer 360 and the third insulating layer 360 and through a via hole 139 penetrating the first insulating layer 350, the second insulating layer 360 and the third insulating layer 360. For example, when the orthographic projection of the other end of the first connecting line L1 on the base substrate 10 at least partially overlaps with the orthographic projection of the source S1 of the first transistor T1 on the base substrate 10, the other end of the first connecting line L1 may also be connected to the source S1 of the first transistor T1 through a via (not shown in the figure) penetrating the first insulating layer 350, and the embodiments of the present disclosure are not limited to this.

[0177] One end of the second conductive connection portion L4 is connected to one end of the second connection line L2 through a via 136 penetrating the second insulating layer 350 (and the third insulating layer 360), and the other end of the second conductive connection portion L4 is connected to the other end of the second resistor R2 through a via 137 penetrating the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). The other end of the second connection line L2 is connected to the second trigger signal line ESTV2 through a via 138 penetrating the second insulating layer 360 and the third insulating layer 370.

[0178] In the embodiments of the present disclosure, the first-stage shift register of each scanning driving circuit is connected to the corresponding trigger signal through each resistor, which can avoid the influence of static electricity generated at the moment when the device is powered on on various signals (for example, trigger signals, clock signals, etc.), thereby making the output signal output by the scanning driving circuit more accurate and improving the display quality of the display panel.

[0179] It should be noted that in multiple embodiments of the present disclosure, the process of the method for manufacturing the display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the process of the manufacturing method described above includes multiple operations that appear in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The manufacturing method described above can be performed once or multiple times according to predetermined conditions.

[0180] The technical effects of the method for manufacturing the display substrate provided in the above embodiment may refer to the technical effects of the display substrate provided in the embodiment of the present disclosure, which will not be described in detail here.

[0181] There are a few points to note:

[0182] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0183] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0184] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: The substrate includes a pixel array area and a peripheral area. A first scan driving circuit, a plurality of power lines, a first signal line group and a second signal line group are arranged in the peripheral area and located on the first side of the base substrate; Wherein, the first scan driving circuit comprises a plurality of cascaded first shift registers; The plurality of power supply lines are configured to provide a plurality of power supply voltages to a plurality of cascaded first shift registers included in the first scan driving circuit; The first signal line group includes at least one timing signal line configured to provide at least one timing signal to a plurality of cascaded first shift registers included in the first scan driving circuit; The second signal line group includes a first trigger signal line configured to be connected to a first stage first shift register of a plurality of cascaded first shift registers included in the first scan driving circuit to provide a first trigger signal to the first stage first shift register. The first trigger signal line is located between the plurality of power lines and the pixel array area; The multiple power lines include a third power line, and at least one of the first shift registers includes a fourth constituent transistor connected to the third power line, and the orthographic projection of the fourth constituent transistor on the substrate is located on a side of the orthographic projection of the third power line on the substrate away from the orthographic projection of the first signal line group on the substrate.

2. The display substrate according to claim 1, wherein: The second signal line group is located at a side of the first scan driving circuit close to the pixel array area. The first signal line group is located at another side of the first scan driving circuit opposite to the side where the second signal line group is located.

3. The display substrate according to claim 2, wherein: The plurality of power lines further include a fourth power line, The orthographic projection of the fourth power line on the base substrate partially overlaps with the orthographic projection of the first scan driving circuit on the base substrate.

4. The display substrate according to claim 3, wherein: The orthographic projection of the third power line on the base substrate is located between the orthographic projection of the fourth power line on the base substrate and the orthographic projection of the first signal line group on the base substrate.

5. The display substrate according to claim 4, wherein: The third power line and the fourth power line are configured to provide the same second power voltage.

6. The display substrate according to claim 1, wherein: The plurality of power lines also include a first power line, The orthographic projection of the first power line on the base substrate partially overlaps with the orthographic projection of the first scan driving circuit on the base substrate.

7. The display substrate according to claim 6, wherein: at least one of the first shift registers comprises a first constituent transistor connected to the first power supply line, The orthographic projection of the first constituent transistor on the base substrate is located between the orthographic projection of the first signal line group on the base substrate and the orthographic projection of the first power line on the base substrate.

8. The display substrate according to claim 7, wherein: A gate electrode of the first constituent transistor is connected to the second node, and a second electrode of the first constituent transistor is connected to the first power supply line to receive a first power supply voltage.

9. The display substrate according to claim 3, wherein: At least one of the first shift registers further includes a fifth constituent transistor connected to the fourth power supply line, The orthographic projection of the fifth constituent transistor on the base substrate is located between the orthographic projection of the fourth power line on the base substrate and the orthographic projection of the second signal line group on the base substrate.

10. The display substrate according to claim 1, wherein: The first signal line group includes a first clock signal line configured to provide a first clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit.

11. The display substrate according to claim 10, wherein: The gate of the fourth constituent transistor is connected to the first clock signal line to receive the first clock signal, the first electrode of the fourth constituent transistor is connected to the third power supply line to receive the second power supply voltage, and the second electrode of the fourth constituent transistor is connected to the second node.

12. The display substrate according to claim 9, wherein: The first signal line group includes a second clock signal line configured to provide a second clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit. A gate of the fifth constituent transistor is connected to the first node, a first electrode of the fifth constituent transistor is connected to a third power supply line to receive a second power supply voltage, and a second electrode of the fifth constituent transistor is connected to an output terminal of the first shift register.

13. A display substrate, comprising: The substrate includes a pixel array area and a peripheral area. A first scan driving circuit, a plurality of power lines, a first signal line group and a second signal line group are arranged in the peripheral area and located on the first side of the base substrate; Wherein, the first scan driving circuit comprises a plurality of cascaded first shift registers; The plurality of power supply lines are configured to provide a plurality of power supply voltages to a plurality of cascaded first shift registers included in the first scan driving circuit; The first signal line group includes at least one timing signal line configured to provide at least one timing signal to a plurality of cascaded first shift registers included in the first scan driving circuit; The second signal line group includes a first trigger signal line configured to be connected to a first stage first shift register of a plurality of cascaded first shift registers included in the first scan driving circuit to provide a first trigger signal to the first stage first shift register. The first trigger signal line is located between the plurality of power lines and the pixel array area; The first scan driving circuit includes a first transistor, a second transistor and a third transistor, and the first transistor, the second transistor and the third transistor are respectively connected to the first signal line group. An extension direction of channels of the first transistor, the second transistor, and the third transistor is parallel to an extension direction of the first signal line group and the second signal line group.

14. The display substrate according to claim 13, wherein: The first signal line group includes a first clock signal line configured to provide a first clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit. The gate of the first transistor is connected to the first clock signal line to receive the first clock signal, the first electrode of the first transistor is connected to the input end of the first shift register, and the second electrode of the first transistor is connected to the first node.

15. The display substrate according to claim 13, wherein: The first signal line group includes a first clock signal line configured to provide a first clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit. A gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to the first clock signal line to receive the first clock signal, and a second electrode of the second transistor is connected to the second node.

16. The display substrate according to claim 13, wherein: The first signal line group includes a first clock signal line configured to provide a first clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit. The multiple power lines include a third power line, a gate of the third transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the third transistor is connected to the third power line to receive a second power supply voltage, and a second electrode of the third transistor is connected to a second node.

17. The display substrate according to claim 13, wherein: The first scan driving circuit further includes a sixth transistor and a seventh transistor, wherein the sixth transistor and the seventh transistor are respectively connected to the first signal line group. An extension direction of the channels of the sixth transistor and the seventh transistor is parallel to an extension direction of the first signal line group and the second signal line group.

18. The display substrate according to claim 17, wherein: The first signal line group includes a second clock signal line configured to provide a second clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit. A gate of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the second clock signal line to receive the second clock signal, and a second electrode of the sixth transistor is connected to the third node.

19. The display substrate according to claim 17, wherein: The first signal line group includes a second clock signal line configured to provide a second clock signal to a plurality of cascaded first shift registers included in the first scan driving circuit. A gate of the seventh transistor is connected to the second clock signal line to receive the second clock signal, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to the fourth node.

20. A display device, comprising the display substrate according to any one of claims 1 to 19.

21. A method for manufacturing a display substrate according to any one of claims 1 to 19, comprising: Providing the substrate; Sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the substrate; Wherein, the power line and the first signal line group are located in the third conductive layer; The first scan driving circuit is formed on the semiconductor layer, the first conductive layer and the second conductive layer; The first scan driving circuit is connected to the power line and the first signal line group respectively through via holes penetrating the first insulating layer, the second insulating layer and the third insulating layer.

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