Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, relates to the technical field of display, and is used for narrowing the frame width of a display product better. The shift register comprises an output circuit, the output circuit comprises a first output transistor, the first output transistor comprises a double-gate transistor, a top gate of the first output transistor is coupled with a cascade signal output end, a bottom gate of the first output transistor is coupled with a regulation and control end, and the double-gate transistor comprises a double-gate transistor. A first electrode of the first output transistor is coupled with a first level signal input end, and a second electrode of the first output transistor is coupled with a gate driving signal output end; the cascade signal output end is used for controlling the first output transistor to be switched on or switched off, and the regulation and control end is used for controlling characteristic parameters of the first output transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, and people have higher and higher requirements for the display quality of display products. In order to better realize narrow-border display products, GOA (English: Gate On Array) technology is used in display products, that is, the gate drive circuit is directly made on the array substrate, and the sub-pixel rows in the display area are driven by the various levels of shift registers included in the gate drive circuit, thereby realizing the display function of the display product. However, the existing shift register has a complex structure, includes a large number of transistors, and still occupies a large layout space, which is not conducive to further narrowing the border of the display product. Summary of the invention

[0003] The object of the present invention is to provide a shift register, a gate driving circuit and a display device, which are used to better narrow the border width of a display product.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a shift register, comprising: an output circuit; the output circuit comprises a first output transistor, the first output transistor comprises a dual-gate transistor, a top gate of the first output transistor is coupled to a cascade signal output terminal, a bottom gate of the first output transistor is coupled to a regulation terminal, a first electrode of the first output transistor is coupled to a first level signal input terminal, and a second electrode of the first output transistor is coupled to a gate drive signal output terminal;

[0006] The cascade signal output terminal is used to control the first output transistor to be turned on or off, and the regulation terminal is used to control the characteristic parameters of the first output transistor.

[0007] Optionally, the output circuit further includes a second output transistor; the first output transistor includes an oxide transistor, and the second output transistor includes a low-temperature polysilicon transistor;

[0008] The gate of the second output transistor is coupled to the cascade signal output terminal, the first electrode of the second output transistor is coupled to the second level signal input terminal, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal.

[0009] Optionally, the shift register includes a first first-level signal input terminal and a third first-level signal input terminal; a voltage value of the first-level signal inputted to the third first-level signal input terminal is smaller than a voltage value of the first-level signal inputted to the first first-level signal input terminal;

[0010] The regulating end is coupled to the third first-level signal input end, and the first electrode of the first output transistor is coupled to the first first-level signal input end.

[0011] Optionally, the shift register includes a second first level signal input terminal;

[0012] The regulating end is coupled to the cascade signal output end, and the first electrode of the first output transistor is coupled to the second first level signal input end.

[0013] Optionally, the shift register comprises a first first-level signal input terminal and a second first-level signal input terminal; a voltage value of the first-level signal inputted to the first first-level signal input terminal is smaller than a voltage value of the first-level signal inputted to the second first-level signal input terminal;

[0014] The output circuit further includes a tenth transistor, the tenth transistor including an oxide transistor with a dual-gate structure; a top gate of the tenth transistor is coupled to the cascade signal output terminal, a bottom gate of the tenth transistor is coupled to the cascade signal output terminal, a first electrode of the tenth transistor is coupled to the first first-level signal input terminal or the second first-level signal input terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the first output transistor;

[0015] The shift register further includes:

[0016] The leakage control circuit is coupled to the gate drive signal output terminal, the first voltage signal input terminal and the second electrode of the tenth transistor, respectively, and is used to control the conduction or disconnection of the electrical connection between the first voltage signal input terminal and the second electrode of the tenth transistor under the control of the gate drive signal output by the gate drive signal output terminal.

[0017] Optionally, the shift register includes a first second-level signal input terminal and a second second-level signal input terminal, a voltage value of the second-level signal inputted by the second second-level signal input terminal is less than or equal to a voltage value of the second-level signal inputted by the first second-level signal input terminal; a first electrode of the second output transistor is coupled to the first second-level signal input terminal or the second second-level signal input terminal;

[0018] The shift register further includes:

[0019] A first cascade control circuit is coupled to the first node, the cascade signal output terminal and the second clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the cascade signal output terminal and the second clock signal input terminal under the control of the potential of the first node;

[0020] The second cascade control circuit is coupled to the second node, the cascade signal output terminal and the first second level signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the cascade signal output terminal and the first second level signal input terminal under the control of the potential of the second node.

[0021] Optionally, the shift register further includes:

[0022] A first node control circuit is coupled to the first node, the first first level signal input terminal and the third node respectively, and is used to control the conduction or disconnection of the electrical connection between the first node and the third node under the control of the first second level signal input terminal;

[0023] The third node control circuit is coupled to the third node, the start signal input terminal and the first clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the third node and the start signal input terminal under the control of the first clock signal input terminal.

[0024] Optionally, the shift register further includes:

[0025] A second node control circuit is coupled to the second node, the first clock signal input terminal and the fourth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second node and the fourth node under the control of the first clock signal input terminal;

[0026] The fourth node control circuit is respectively coupled to the fourth node, the start signal input terminal, the first level signal input terminal and the first second level signal input terminal, and is used for controlling the conduction or disconnection of the electrical connection between the fourth node and the first level signal input terminal, and controlling the conduction or disconnection of the electrical connection between the fourth node and the first second level signal input terminal under the control of the start signal input at the start signal input terminal.

[0027] Optionally, the shift register comprises a first first-level signal input terminal and a third first-level signal input terminal, and a level value of the first-level signal inputted to the first first-level signal input terminal is greater than a level value of the first-level signal inputted to the third first-level signal input terminal;

[0028] The fourth node control circuit includes a fifth transistor and a sixth transistor;

[0029] The fifth transistor comprises an oxide transistor of a dual-gate structure, a top gate of the fifth transistor is coupled to the start signal input terminal, a bottom gate of the fifth transistor is coupled to the third first-level signal input terminal, a first electrode of the fifth transistor is coupled to the first first-level signal input terminal, and a second electrode of the fifth transistor is coupled to the fourth node;

[0030] A gate of the sixth transistor is coupled to the start signal input terminal, a first electrode of the sixth transistor is coupled to the first second level signal input terminal, and a second electrode of the sixth transistor is coupled to the fourth node.

[0031] Optionally, the shift register comprises a first first-level signal input terminal and a second first-level signal input terminal, and a level value of the first-level signal inputted to the first first-level signal input terminal is smaller than a level value of the first-level signal inputted to the second first-level signal input terminal;

[0032] The fourth node control circuit includes a fifth transistor and a sixth transistor;

[0033] The fifth transistor comprises an oxide transistor of a dual-gate structure, a top gate of the fifth transistor is coupled to the start signal input terminal, a bottom gate of the fifth transistor is coupled to the first first-level signal input terminal, a first electrode of the fifth transistor is coupled to the second first-level signal input terminal, and a second electrode of the fifth transistor is coupled to the fourth node;

[0034] A gate of the sixth transistor is coupled to the start signal input terminal, a first electrode of the sixth transistor is coupled to the first second level signal input terminal, and a second electrode of the sixth transistor is coupled to the fourth node.

[0035] Optionally, the shift register further includes:

[0036] The anti-noise control circuit is coupled to the second clock signal input terminal, the second node, the first second-level signal input terminal and the third node respectively, and is used to control the conduction or disconnection of the electrical connection between the first second-level signal input terminal and the third node under the joint control of the second clock signal input to the second clock signal input terminal and the potential of the second node.

[0037] Optionally, the first cascade control circuit includes a second transistor and a first capacitor; a gate of the second transistor is coupled to the first node, a first electrode of the second transistor is coupled to the second clock signal input terminal, and a second electrode of the second transistor is coupled to the cascade signal output terminal; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the cascade signal output terminal;

[0038] The second cascade control circuit includes a first transistor and a second capacitor; the gate of the first transistor is coupled to the second node, the first electrode of the first transistor is coupled to the first second level signal input terminal, and the second electrode of the first transistor is coupled to the cascade signal output terminal; the first electrode of the second capacitor is coupled to the second node, and the second electrode of the second capacitor is coupled to the first second level signal input terminal;

[0039] The first node control circuit comprises a fourth transistor, a gate of the fourth transistor is coupled to the first first level signal input terminal, a first electrode of the fourth transistor is coupled to the third node, and a second electrode of the fourth transistor is coupled to the first node;

[0040] The third node control circuit comprises a third transistor, a gate of the third transistor is coupled to the first clock signal input terminal, a first electrode of the third transistor is coupled to the start signal input terminal, and a second electrode of the third transistor is coupled to the third node;

[0041] The second node control circuit comprises a seventh transistor, a gate of the seventh transistor is coupled to the first clock signal input terminal, a first electrode of the seventh transistor is coupled to the fourth node, and a second electrode of the seventh transistor is coupled to the second node;

[0042] In the case where the shift register includes a leakage control circuit, the leakage control circuit includes an eleventh transistor, a gate of the eleventh transistor is coupled to the gate drive signal output terminal, a first electrode of the eleventh transistor is coupled to the first voltage signal input terminal, and a second electrode of the eleventh transistor is coupled to a second electrode of the tenth transistor;

[0043] The anti-noise control circuit includes a twelfth transistor and a thirteenth transistor;

[0044] The gate of the twelfth transistor is coupled to the second node, the first electrode of the twelfth transistor is coupled to the first second-level signal input terminal, the second electrode of the twelfth transistor is coupled to the first electrode of the thirteenth transistor, the gate of the thirteenth transistor is coupled to the second clock signal input terminal, and the second electrode of the thirteenth transistor is coupled to the third node.

[0045] Based on the technical solution of the above-mentioned shift register, a second aspect of the present invention provides a gate driving circuit, comprising a plurality of the above-mentioned shift registers connected in cascade.

[0046] Optionally, the cascade signal output terminal of the n-th stage shift register is coupled to the start signal input terminal of the (n+m)-th stage shift register, where n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

[0047] Based on the technical solution of the above-mentioned gate driving circuit, a third aspect of the present invention provides a display device, including the above-mentioned gate driving circuit.

[0048] In the technical solution provided by the present invention, the cascade signal outputted by the cascade signal output terminal in the shift register is coupled to the top gate of the first output transistor in the output circuit, which can control the conduction state of the first output transistor, and then control the gate drive signal output terminal to output the gate drive signal. Therefore, in the technical solution provided by the present invention, there is no need to introduce an additional control circuit part to control the output circuit. By using the existing cascade signal in the shift register to control the first output transistor in the output circuit, the gate drive signal output terminal can be controlled to output a gate drive signal that meets the requirements; therefore, the technical solution provided by the present invention effectively simplifies the circuit complexity, and when the shift register is applied to a display product, the border area of ​​the display product can be further narrowed.

[0049] Moreover, in the shift register provided by the present invention, the control end is coupled to the bottom gate of the first output transistor, and the control signal output by the control end can control the characteristic parameters of the first output transistor, which can specifically include the magnitude of the on-current and the degree of offset of the threshold voltage, thereby ensuring that the first output transistor can achieve better working characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0051] Figure 1 A schematic diagram of a first module of a shift register provided in an embodiment of the present invention;

[0052] Figure 2 A schematic diagram of a second module of a shift register provided in an embodiment of the present invention;

[0053] Figure 3 A schematic diagram of a third module of a shift register provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of a fourth module of a shift register provided by an embodiment of the present invention;

[0055] Figure 5 A schematic diagram of a first circuit structure of a shift register provided by an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of a second circuit structure of a shift register provided in an embodiment of the present invention;

[0057] Figure 7 A third circuit structure diagram of a shift register provided by an embodiment of the present invention;

[0058] Figure 8 A fourth circuit structure diagram of the shift register provided by an embodiment of the present invention;

[0059] Fig. 9 A fifth circuit structure diagram of the shift register provided by an embodiment of the present invention;

[0060] Fig.10 A schematic diagram of the effect of the bottom gate voltage on the threshold voltage of a transistor provided by an embodiment of the present invention;

[0061] Fig.11 A working timing diagram of a shift register provided by an embodiment of the present invention;

[0062] Fig.12 A schematic diagram of a cascade connection of a multi-stage shift register provided by an embodiment of the present invention;

[0063] Fig.13 An output timing diagram of a multi-stage shift register is provided for an embodiment of the present invention;

[0064] Fig.14 Another schematic diagram of cascading a multi-stage shift register provided by an embodiment of the present invention; DETAILED DESCRIPTION

[0065] In order to further illustrate the shift register, gate driving circuit and display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0066] See also Figure 1 , Figures 5 to 9, an embodiment of the present invention provides a shift register, comprising: an output circuit 10; the output circuit 10 comprises a first output transistor T8, the first output transistor T8 comprises a dual-gate transistor, the top gate of the first output transistor T8 is coupled to the cascade signal output terminal CR, the bottom gate of the first output transistor T8 is coupled to the regulation terminal TK, the first electrode of the first output transistor T8 is coupled to the first level signal input terminal VGL, and the second electrode of the first output transistor T8 is coupled to the gate drive signal output terminal OUT;

[0067] The cascade signal output terminal CR is used to control the first output transistor T8 to be turned on or off, and the regulation terminal TK is used to control the characteristic parameters of the first output transistor T8.

[0068] Exemplarily, the control terminal TK is coupled to the cascade signal output terminal CR or the third first level signal input terminal VGL3, but is not limited thereto.

[0069] Exemplarily, the characteristic parameters include the magnitude of the on-current and the degree of shift of the threshold voltage, but are not limited thereto.

[0070] Exemplarily, the output circuit 10 is respectively coupled to the cascade signal output terminal CR, the gate drive signal output terminal OUT, the first level signal input terminal VGL and the second level signal input terminal VGH, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal OUT and the first level signal input terminal VGL, and control the conduction or disconnection of the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGH under the control of the cascade signal output by the cascade signal output terminal CR.

[0071] Exemplarily, the shift register can be applied to LTPO or LTPS OLED display products, for example: the shift register can be applied to LTPO. In this display product, the tube that controls the writing of data signals to the gate of the driving transistor in the pixel circuit is an oxide transistor, and a gate drive signal with a high voltage pulse with a pulse width of less than 1H or about 1.5H is required as the control signal of the oxide transistor. The shift register that outputs the signal can be called NGateGOA.

[0072] Exemplarily, the first level signal input terminal is used to output a first level signal of a negative voltage, and the second level signal input terminal is used to output a second level signal of a positive voltage.

[0073] Exemplarily, when the gate drive signal output from the gate drive signal output terminal OUT is at a low level, the output circuit 10 is used to control the electrical connection between the gate drive signal output terminal OUT and the first level signal input terminal, and control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal to be disconnected, under the control of the cascade signal output from the cascade signal output terminal CR; when the gate drive signal output from the gate drive signal output terminal OUT is at a high level, the output circuit 10 is used to control the electrical connection between the gate drive signal output terminal OUT and the first level signal input terminal, and control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal to be disconnected, under the control of the cascade signal output from the cascade signal output terminal CR.

[0074] According to the specific structure of the above-mentioned shift register, it can be known that the cascade signal outputted by the cascade signal output terminal CR in the shift register provided by the embodiment of the present invention is coupled to the top gate of the first output transistor T8 in the output circuit 10, and can control the conduction state of the first output transistor T8, thereby controlling the gate drive signal output terminal OUT to output the gate drive signal. Therefore, in the shift register provided by the embodiment of the present invention, there is no need to introduce an additional control circuit part to control the output circuit 10. By using the existing cascade signal in the shift register to control the first output transistor T8 in the output circuit 10, the gate drive signal output terminal OUT can be controlled to output a gate drive signal that meets the requirements; therefore, the shift register provided by the embodiment of the present invention effectively simplifies the circuit complexity, and when the shift register is applied to display products, the border area of ​​the display product can be further narrowed.

[0075] Moreover, in the shift register provided in the embodiment of the present invention, the control end is coupled to the bottom gate of the first output transistor T8, and the control signal output by the control end can control the characteristic parameters of the first output transistor, which can specifically include the magnitude of the on-current and the degree of offset of the threshold voltage, thereby ensuring that the first output transistor can achieve better working characteristics.

[0076] like Figures 5 to 9 As shown, in some embodiments, the output circuit 10 further includes a second output transistor T9; the first output transistor T8 includes an oxide transistor, and the second output transistor T9 includes a low temperature polysilicon transistor;

[0077] A gate of the second output transistor T9 is coupled to the cascade signal output terminal CR, a first electrode of the second output transistor T9 is coupled to the second level signal input terminal, and a second electrode of the second output transistor T9 is coupled to the gate drive signal output terminal OUT.

[0078] Exemplarily, the first output transistor T8 includes an NMOS transistor, and the second output transistor T9 includes a PMOS transistor.

[0079] The output circuit 10 of the above structure adopts a CMOS circuit structure, which can effectively reduce the number of transistors used in the shift register while outputting a gate drive signal with a positive pulse. When the shift register is applied to a display product, the border area of ​​the display product can be further narrowed.

[0080] like Figure 5 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a third first-level signal input terminal VGL3; the voltage value of the first-level signal inputted by the third first-level signal input terminal VGL3 is smaller than the voltage value of the first-level signal inputted by the first first-level signal input terminal VGL1;

[0081] The regulating terminal TK is coupled to the third first-level signal input terminal VGL3 , and the first electrode of the first output transistor T8 is coupled to the first first-level signal input terminal VGL1 .

[0082] Exemplarily, the first first-level signal input terminal VGL1 and the third first-level signal input terminal VGL3 are both used to output a first-level signal of a negative voltage, and the negative voltage value of the first-level signal input to the first first-level signal input terminal VGL1 is greater than the negative voltage value of the first-level signal input to the third first-level signal input terminal VGL3.

[0083] In more detail, Fig.10 As shown in the figure, the Id-Vg curve of the oxide transistor under different bottom gate voltages (-6V, -4V, -2V, 0V, 2V, 4V, 6V) is illustrated, where Id represents the driving current of the transistor when it is working, and Vg represents the top gate voltage of the transistor. The horizontal axis in the figure represents Vg in V, and the vertical axis represents Id in A. It can be seen from the figure that the more negative the bottom gate voltage is, the more positive the threshold voltage Vth of the transistor is. It can be seen that the purpose of increasing the bottom gate voltage is to make the Vth of the oxide transistor positive and not negatively biased.

[0084] In the shift register provided in the above embodiment, the bottom gate of the first output transistor T8 is coupled to the third first-level signal input terminal VGL3, which can better ensure that the threshold voltage of the first output transistor T8 does not have a negative bias; at the same time, the first electrode of the first output transistor T8 is coupled to the first first-level signal input terminal VGL1, so that the gate drive signal can have a low level that meets the requirements.

[0085] like Figure 6 As shown, in some embodiments, the shift register includes a second first level signal input terminal VGL2; the regulating terminal is coupled to the cascade signal output terminal CR, and the first electrode of the first output transistor T8 is coupled to the second first level signal input terminal VGL2.

[0086] Exemplarily, the first first-level signal input terminal VGL1, the second first-level signal input terminal VGL2 and the third first-level signal input terminal VGL3 are all used to output first-level signals of negative voltages, the negative voltage value of the first-level signal input to the first first-level signal input terminal VGL1 is greater than the negative voltage value of the first-level signal input to the third first-level signal input terminal VGL3, and the negative voltage value of the first-level signal input to the second first-level signal input terminal VGL2 is greater than the negative voltage value of the first-level signal input to the first first-level signal input terminal VGL1.

[0087] The top gate and the bottom gate of the first output transistor T8 are coupled to the cascade signal output terminal CR, so that the first output transistor T8 has a larger conduction current when it is turned on. In this way, when the first level signal is written into the gate drive signal output terminal OUT through the first output transistor T8, the low-voltage first level signal is not easily lost. At the same time, the size of the first output transistor T8 can be reduced, thereby further reducing the layout space occupied by the shift register, which is conducive to reducing the border size of the display product to which it is applied.

[0088] like Figure 8 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a second first-level signal input terminal VGL2; the voltage value of the first-level signal inputted by the first first-level signal input terminal VGL1 is smaller than the voltage value of the first-level signal inputted by the second first-level signal input terminal VGL2;

[0089] The output circuit 10 further includes a tenth transistor T10, and the tenth transistor T10 includes an oxide transistor with a dual-gate structure; a top gate of the tenth transistor T10 is coupled to the cascade signal output terminal CR, a bottom gate of the tenth transistor T10 is coupled to the cascade signal output terminal CR, a first electrode of the tenth transistor T10 is coupled to the first first-level signal input terminal VGL1 or the second first-level signal input terminal VGL2, and a second electrode of the tenth transistor T10 is coupled to the first electrode of the first output transistor T8;

[0090] The shift register further includes:

[0091] The leakage control circuit 50 is respectively coupled to the gate drive signal output terminal OUT, the first voltage signal input terminal GVDD and the second electrode of the tenth transistor T10, and is used to control the conduction or disconnection of the electrical connection between the first voltage signal input terminal and the second electrode of the tenth transistor T10 under the control of the gate drive signal output from the gate drive signal output terminal OUT.

[0092] Exemplarily, in the above embodiment, the shift register includes a first second-level signal input terminal VGH1 and a second second-level signal input terminal VGH2, and the voltage value of the second-level signal input by the second second-level signal input terminal VGH2 is less than the voltage value of the second-level signal input by the first second-level signal input terminal VGH1. The first electrode of the second output transistor T9 is coupled to the first second-level signal input terminal VGH1 or the second second-level signal input terminal VGH2.

[0093] Exemplarily, the leakage control circuit 50 includes an eleventh transistor T11, the gate of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT, the first electrode of the eleventh transistor T11 is coupled to the first voltage signal input terminal, and the second electrode of the eleventh transistor T11 is coupled to the second electrode of the tenth transistor T10. For example: the first voltage signal input terminal is an independent high voltage source, and the voltage value of the first voltage signal inputted thereto can be set to be less than or equal to the voltage value of the second level signal inputted by the first second level signal input terminal VGH1, and the voltage value of the first voltage signal inputted thereto can also be set to be less than or equal to the voltage value of the second level signal inputted by the second second level signal input terminal VGH2.

[0094] The shift register is configured as described above to include the first output transistor T8, the tenth transistor T10 and the eleventh transistor T11, so that when the cascade signal output terminal CR controls the second output transistor T9 to be turned on and the gate drive signal outputted from the gate drive signal output terminal OUT is at a high level, the eleventh transistor T11 is controlled to be turned on, so that the first electrode of the first output transistor T8 is written with the first voltage signal, so that the first output transistor T8 is controlled to be turned off more thoroughly, thereby avoiding the problem of leakage of the first output transistor T8 and ensuring that the gate drive signal outputted from the gate drive signal output terminal OUT is more stable.

[0095] like Figure 2As shown, in some embodiments, the shift register includes a first second-level signal input terminal VGH1 and a second second-level signal input terminal VGH2, the voltage value of the second-level signal input by the second second-level signal input terminal VGH2 is less than or equal to the voltage value of the second-level signal input by the first second-level signal input terminal VGH1; the first electrode of the second output transistor T9 is coupled to the first second-level signal input terminal VGH1 or the second second-level signal input terminal VGH2;

[0096] The shift register further includes:

[0097] A first cascade control circuit 20 is coupled to the first node Q1, the cascade signal output terminal CR and the second clock signal input terminal CB respectively, and is used to control the conduction or disconnection of the electrical connection between the cascade signal output terminal CR and the second clock signal input terminal CB under the control of the potential of the first node Q1;

[0098] The second cascade control circuit 30 is coupled to the second node QB, the cascade signal output terminal CR and the first second level signal input terminal VGH1, respectively, and is used to control the conduction or disconnection of the electrical connection between the cascade signal output terminal CR and the first second level signal input terminal VGH1 under the control of the potential of the second node QB.

[0099] It should be noted that the low voltage of the first clock signal input to the first clock signal input terminal CK is the same as the voltage of the first level signal input to the first first level signal input terminal VGL1, and the high voltage of the first clock signal input to the first clock signal input terminal CK is the same as the voltage of the second level signal input to the first second level signal input terminal VGH1. The low voltage of the second clock signal input to the second clock signal input terminal CB is the same as the voltage of the first level signal input to the first first level signal input terminal VGL1, and the high voltage of the second clock signal input to the second clock signal input terminal CB is the same as the voltage of the second level signal input to the first second level signal input terminal VGH1.

[0100] like Figure 3 As shown, in some embodiments, the shift register further includes:

[0101] A first node control circuit 41 is coupled to the first node Q1, the first first level signal input terminal VGL1 and the third node Q3 respectively, and is used to control the conduction or disconnection of the electrical connection between the first node Q1 and the third node Q3 under the control of the first second level signal input terminal VGH1;

[0102] The third node control circuit 43 is coupled to the third node Q3, the start signal input terminal STV and the first clock signal input terminal CK, respectively, and is used to control the conduction or disconnection of the electrical connection between the third node Q3 and the start signal input terminal STV under the control of the first clock signal input at the first clock signal input terminal CK.

[0103] like Figure 4 As shown, in some embodiments, the shift register further includes:

[0104] A second node control circuit 42 is coupled to the second node QB, the first clock signal input terminal CK and the fourth node QB1 respectively, and is used to control the conduction or disconnection of the electrical connection between the second node QB and the fourth node QB1 under the control of the first clock signal inputted by the first clock signal input terminal CK;

[0105] The fourth node control circuit 44 is respectively coupled to the fourth node QB1, the start signal input terminal STV, the first level signal input terminal and the first second level signal input terminal VGH1, and is used for controlling the conduction or disconnection of the electrical connection between the fourth node QB1 and the first level signal input terminal, and controlling the conduction or disconnection of the electrical connection between the fourth node QB1 and the first second level signal input terminal VGH1, under the control of the start signal input by the start signal input terminal STV.

[0106] The shift register is configured to include the above structure, so that the first node control circuit 41 and the third node control circuit 43 can control the potential of the first node Q1, the potential of the first node Q1 can control the conduction of the first cascade control circuit 20, the second node control circuit 42 and the fourth node control circuit 44 can control the potential of the second node QB, the potential of the second node QB can control the conduction of the second cascade control circuit 30, thereby realizing the control of the cascade signal output by the cascade signal output terminal CR; when the shift register adopts the above structure, the circuit structure is simple, and when it is applied to display products, it is conducive to realizing the narrow frame of the display products.

[0107] like Figure 5 and Figure 6 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a third first-level signal input terminal VGL3, and the level value of the first-level signal input by the first first-level signal input terminal VGL1 is greater than the level value of the first-level signal input by the third first-level signal input terminal VGL3;

[0108] The fourth node control circuit 44 includes a fifth transistor T5 and a sixth transistor T6;

[0109] The fifth transistor T5 comprises an oxide transistor of a dual-gate structure, a top gate of the fifth transistor T5 is coupled to the start signal input terminal STV, a bottom gate of the fifth transistor T5 is coupled to the third first-level signal input terminal VGL3, a first electrode of the fifth transistor T5 is coupled to the first first-level signal input terminal VGL1, and a second electrode of the fifth transistor T5 is coupled to the fourth node QB1;

[0110] A gate of the sixth transistor T6 is coupled to the start signal input terminal STV, a first electrode of the sixth transistor T6 is coupled to the first second level signal input terminal VGH1, and a second electrode of the sixth transistor T6 is coupled to the fourth node QB1.

[0111] The above-mentioned setting of coupling the bottom gate of the fifth transistor T5 to the third first-level signal input terminal VGL3 and coupling the first electrode of the fifth transistor T5 to the first first-level signal input terminal VGL1 can not only better ensure that the threshold voltage of the fifth transistor T5 does not have a negative bias, but also ensure that the fifth transistor T5 is better turned on and the first-level signal is written to the fourth node QB1.

[0112] like Figure 7 and Figure 8 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a second first-level signal input terminal VGL2, and the level value of the first-level signal inputted by the first first-level signal input terminal VGL1 is smaller than the level value of the first-level signal inputted by the second first-level signal input terminal VGL2;

[0113] The fourth node control circuit 44 includes a fifth transistor T5 and a sixth transistor T6;

[0114] The fifth transistor T5 comprises an oxide transistor of a dual-gate structure, a top gate of the fifth transistor T5 is coupled to the start signal input terminal STV, a bottom gate of the fifth transistor T5 is coupled to the first first-level signal input terminal VGL1, a first electrode of the fifth transistor T5 is coupled to the second first-level signal input terminal VGL2, and a second electrode of the fifth transistor T5 is coupled to the fourth node QB1;

[0115] A gate of the sixth transistor T6 is coupled to the start signal input terminal STV, a first electrode of the sixth transistor T6 is coupled to the first second level signal input terminal VGH1, and a second electrode of the sixth transistor T6 is coupled to the fourth node QB1.

[0116] The above-mentioned setting of coupling the bottom gate of the fifth transistor T5 to the first first-level signal input terminal VGL1 and coupling the first electrode of the fifth transistor T5 to the second first-level signal input terminal VGL2 can not only better ensure that the threshold voltage of the fifth transistor T5 does not have a negative bias, but also ensure that the fifth transistor T5 is better turned on and the first-level signal is written to the fourth node QB1.

[0117] In some embodiments, the fifth transistor T5 is an NMOS transistor, and the sixth transistor T6 is a PMOS transistor.

[0118] The fourth node control circuit 44 is configured to include the fifth transistor T5 and the sixth transistor T6, so that the fourth node control circuit 44 is formed into an inverter structure, so that the start signal input from the start signal input terminal STV can synchronously control the potential of the fourth node QB1.

[0119] like Fig. 9 As shown, in some embodiments, the shift register further includes:

[0120] The anti-noise control circuit 60 is coupled to the second clock signal input terminal CB, the second node QB, the first second level signal input terminal VGH1 and the third node Q3, respectively, and is used to control the conduction or disconnection of the electrical connection between the first second level signal input terminal VGH1 and the third node Q3 under the joint control of the second clock signal input to the second clock signal input terminal CB and the potential of the second node QB.

[0121] Exemplarily, the anti-noise control circuit 60 includes a twelfth transistor T12 and a thirteenth transistor T13; the gate of the twelfth transistor T12 is coupled to the second node QB, the first electrode of the twelfth transistor T12 is coupled to the first second-level signal input terminal VGH1, the second electrode of the twelfth transistor T12 is coupled to the first electrode of the thirteenth transistor T13, the gate of the thirteenth transistor T13 is coupled to the second clock signal input terminal CB, and the second electrode of the thirteenth transistor T13 is coupled to the third node Q3.

[0122] The above-mentioned setting of the shift register includes the anti-noise control circuit 60, so that the anti-noise control circuit 60 can control whether to write the second level signal to the third node Q3 under the control of the second node QB and the second clock signal, thereby better stabilizing the potential of the third node Q3 and improving the overall anti-noise function of the shift register.

[0123] like Figures 5 to 9As shown, in some embodiments, the first cascade control circuit 20 includes a second transistor T2 and a first capacitor C1; the gate of the second transistor T2 is coupled to the first node Q1, the first electrode of the second transistor T2 is coupled to the second clock signal input terminal CB, and the second electrode of the second transistor T2 is coupled to the cascade signal output terminal CR; the first electrode of the first capacitor C1 is coupled to the first node Q1, and the second electrode of the first capacitor C1 is coupled to the cascade signal output terminal CR;

[0124] The second cascade control circuit 30 includes a first transistor T1 and a second capacitor C2; the gate of the first transistor T1 is coupled to the second node QB, the first electrode of the first transistor T1 is coupled to the first second level signal input terminal VGH1, and the second electrode of the first transistor T1 is coupled to the cascade signal output terminal CR; the first electrode of the second capacitor C2 is coupled to the second node QB, and the second electrode of the second capacitor C2 is coupled to the first second level signal input terminal VGH1;

[0125] The first node control circuit 41 includes a fourth transistor T4, a gate of the fourth transistor T4 is coupled to the first first level signal input terminal VGL1, a first electrode of the fourth transistor T4 is coupled to the third node Q3, and a second electrode of the fourth transistor T4 is coupled to the first node Q1;

[0126] The third node control circuit 43 includes a third transistor T3, a gate of the third transistor T3 is coupled to the first clock signal input terminal CK, a first electrode of the third transistor T3 is coupled to the start signal input terminal STV, and a second electrode of the third transistor T3 is coupled to the third node Q3;

[0127] The second node control circuit 42 includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the first clock signal input terminal CK, a first electrode of the seventh transistor T7 is coupled to the fourth node QB1, and a second electrode of the seventh transistor T7 is coupled to the second node QB;

[0128] In the case where the shift register includes the leakage control circuit 50, the leakage control circuit 50 includes an eleventh transistor T11, a gate of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT, a first electrode of the eleventh transistor T11 is coupled to the first voltage signal input terminal, and a second electrode of the eleventh transistor T11 is coupled to the second electrode of the tenth transistor T10;

[0129] Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the second output transistor T9, the twelfth transistor T12 and the thirteenth transistor T13 are all PMOS transistors; the fifth transistor T5, the first output transistor T8, the tenth transistor T10 and the eleventh transistor T11 are all NMOS transistors.

[0130] It should be noted that in the shift register provided in the above embodiment, the PMOS transistor used can be a single-gate structure transistor or a double-gate transistor. When a double-gate transistor is selected, the top gate and the bottom gate are connected. The selected double-gate transistor can have a separate metal layer as the bottom gate, which can achieve the effect of improving the reliability of the transistor.

[0131] The shift register provided in the above embodiment is not only applicable to LTPS and LTPO OLED display panels, but also applicable to LTPS PMOS GOA circuits and CMOS GOA circuits used in LCD display panels, and BP GOA circuits under the integrated circuit process used in ARVR display panels.

[0132] The shift register of the above structure adopts a CMOS circuit structure, which can effectively reduce the number of transistors used in the shift register while outputting a gate drive signal with a positive pulse. When the shift register is applied to a display product, the border area of ​​the display product can be further narrowed.

[0133] In some embodiments, the first node control circuit 41 can be coupled to the second first level signal input terminal VGL2, that is, under the control of the second first level signal input terminal VGL2, control the conduction or disconnection of the electrical connection between the first node Q1 and the third node Q3. It is worth noting that the first node control circuit 41 is not coupled to the third first level signal input terminal VGL3 as much as possible to avoid the third first level signal input terminal VGL3 making the fourth transistor T4 fully turned on, which is not conducive to the control of the potential of the first node Q1.

[0134] like Fig.11 As shown, when the shift register adopts the above structure, the specific working process is as follows:

[0135] In the P1 period, when the voltage of the start signal input by the start signal input terminal STV changes from high to low, the first clock signal input by the first clock signal input terminal CK is a high voltage, the third node Q3 and the first node Q1 maintain a high voltage, the voltage of the fourth node QB1 changes from low to high, the second node QB maintains a low voltage, the cascade signal output by the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output by the gate drive signal output terminal OUT is a low voltage.

[0136] In the P2 period, when the start signal input by the start signal input terminal STV is a low voltage and the voltage of the first clock signal input by the first clock signal input terminal CK changes from high to low, the fourth node QB1 maintains a high voltage, the voltage of the second node QB changes from low to high, and the voltages of the third node Q3 and the first node Q1 are pulled down by the start signal signal input by the start signal input terminal STV; since the second clock signal input by the second clock signal input terminal CB is a high voltage at this time, the cascade signal output by the cascade signal output terminal CR is a high voltage, and the gate drive signal output by the gate drive signal output terminal OUT is a low voltage.

[0137] In the P3 period, when the start signal input by the start signal input terminal STV is a low voltage and the voltage of the first clock signal input by the first clock signal input terminal CK changes from low to high, the fourth node QB1 maintains a high voltage. Due to the voltage stabilizing effect of the first capacitor C1 and the second capacitor C2, the third node Q3 and the first node Q1 maintain a low voltage, and the second node QB maintains a high voltage. Since the second clock signal input by the second clock signal input terminal CB is a high voltage at this time, the cascade signal output by the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output by the gate drive signal output terminal OUT is a low voltage.

[0138] In the P4 period, when the start signal inputted by the start signal input terminal STV is a low voltage, the first clock signal inputted by the first clock signal input terminal CK is a high voltage, and the second clock signal inputted by the second clock signal input terminal CB changes from a high voltage to a low voltage, the fourth node QB1 maintains a high voltage, and due to the coupling effect of the second capacitor C2, the voltage of the first node Q1 is pulled down due to the voltage change of the cascade signal outputted by the cascade signal output terminal CR, and due to the voltage limiting effect of the fourth transistor T4, the potential of the third node Q3 is pulled down by a magnitude much smaller than that of the first node Q1. At this time, the voltage of the cascade signal outputted by the cascade signal output terminal CR changes from high to low, and the voltage of the gate drive signal outputted by the gate drive signal output terminal OUT changes from low to high.

[0139] In the P5 period, when the start signal input by the start signal input terminal STV is a low voltage and the first clock signal input by the first clock signal input terminal CK is a high voltage, the fourth node maintains a high voltage, the third node Q3 and the first node Q1 maintain a low voltage, the cascade signal output by the cascade signal output terminal CR remains consistent with the second clock signal input by the second clock signal input terminal CB, and the gate drive signal output by the gate drive signal output terminal OUT is opposite to the second clock signal input by the second clock signal input terminal CB.

[0140] In the P6 period, when the start signal input by the start signal input terminal STV is a high voltage and the voltage of the first clock signal input by the first clock signal input terminal CK changes from high to low, the second clock signal input by the second clock signal input terminal CB is a high voltage, the voltage of the fourth node QB1 changes from high to low, the voltage of the third node Q3 and the first node Q1 changes from low to high, the second transistor T2 is turned off, the first transistor T1 is turned on, the cascade signal output by the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output by the gate drive signal output terminal OUT is a low voltage.

[0141] An embodiment of the present invention further provides a gate driving circuit, comprising a plurality of the shift registers connected in cascade.

[0142] By cascading a plurality of the shift registers together, the shifting of the gate driving signal with a positive pulse can be achieved.

[0143] The cascade signal outputted from the cascade signal output terminal CR in the shift register provided in the above embodiment is coupled to the top gate of the first output transistor T8 in the output circuit 10, and can control the conduction state of the first output transistor T8, thereby controlling the gate drive signal output terminal OUT to output the gate drive signal. Therefore, in the shift register provided in the above embodiment, there is no need to introduce an additional control circuit part to control the output circuit 10. By using the existing cascade signal in the shift register to control the first output transistor T8 in the output circuit 10, the gate drive signal output terminal OUT can be controlled to output a gate drive signal that meets the requirements; therefore, the shift register provided in the above embodiment effectively simplifies the circuit complexity, and when the shift register is applied to display products, the border area of ​​the display product can be further narrowed.

[0144] Moreover, in the shift register provided in the above embodiment, the control end is coupled to the bottom gate of the first output transistor T8, and the control signal output by the control end can control the characteristic parameters of the first output transistor, which can specifically include the magnitude of the on-current and the degree of offset of the threshold voltage, thereby ensuring that the first output transistor can achieve better working characteristics.

[0145] The gate driving circuit provided in the embodiment of the present invention also has the above-mentioned beneficial effects when including the above-mentioned shift register, which will not be described in detail here.

[0146] In some embodiments, the cascade signal output terminal CR of the nth stage shift register is coupled to the start signal input terminal STV of the (n+m)th stage shift register, where n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

[0147] like Fig.12 As shown, exemplarily, m=1, that is, the cascade signal output terminal CR of the nth shift register is coupled to the start signal input terminal STV of the n+1th shift register. In this case, the gate drive circuit can be connected to two clock signal lines (such as: CK1, CK2), for example: the first clock signal input terminal CK in the odd-numbered shift register is coupled to the first clock signal line CK1, and the second clock signal input terminal CB in the odd-numbered shift register is coupled to the second clock signal line CK2; the first clock signal input terminal CK in the even-numbered shift register is coupled to the second clock signal line CK2, and the second clock signal input terminal CB in the even-numbered shift register is coupled to the first clock signal line CK1. At the same time, the gate drive circuit can be connected to a frame start signal line, that is, the start signal input terminal STV of the first-stage shift register is coupled to the frame start signal line. It should be noted that GOA-1 shown in the figure represents the first-stage shift register, GOA-2 represents the second-stage shift register, GOA-3 represents the third-stage shift register, GOA-4 represents the fourth-stage shift register, GOA-5 represents the fifth-stage shift register, and GOA-6 represents the sixth-stage shift register.

[0148] like Fig.13 and Fig.14As shown, for example, m=2, that is, the cascade signal output terminal CR of the n-th stage shift register is coupled to the start signal input terminal STV of the n+2-th stage shift register. In this case, the gate drive circuit can be connected to four clock signal lines (such as: CK1, CK2, CK3, CK4), and the multi-stage shift register included in the gate drive circuit can be divided into multiple groups of register groups, each group of register groups includes two adjacent stages of shift registers; in the odd-numbered group of shift registers, the first clock signal input terminal CK of the first stage of the two-stage shift register is coupled to the first clock signal line CK1, and the second clock signal input terminal CB is coupled to the third clock signal line CK3. The first clock signal input terminal CK of the other stage shift register in the two-stage shift register is coupled to the second clock signal line CK2, and the second clock signal input terminal CB is coupled to the fourth clock signal line CK4; in the even-group shift register, the first clock signal input terminal CK of the first stage shift register in the two-stage shift register is coupled to the third clock signal line CK3, and the second clock signal input terminal CB is coupled to the first clock signal line CK1; the first clock signal input terminal CK of the other stage shift register in the two-stage shift register is coupled to the fourth clock signal line CK4, and the second clock signal input terminal CB is coupled to the second clock signal line CK2. At the same time, the gate drive circuit can be connected to a frame start signal line, that is, the start signal input terminals STV of the first stage shift register and the second stage shift register are both coupled to the frame start signal line.

[0149] It is worth noting that when m=2, the gate drive circuit can also be set to connect to two frame start signal lines, that is, the start signal input terminal STV of the first-stage shift register is coupled to the first frame start signal line, and the start signal input terminal STV of the second-stage shift register is coupled to the second frame start signal line.

[0150] Exemplarily, m=3, that is, the cascade signal output terminal CR of the n-th shift register is coupled to the start signal input terminal STV of the n+3-th shift register. In this case, the gate drive circuit can be connected to six clock signal lines. At the same time, the gate drive circuit can be connected to a frame start signal line, that is, the start signal input terminals STV of the first-stage shift register, the second-stage shift register, and the third-stage shift register are all coupled to the frame start signal line. It is worth noting that, in the case of m=3, the gate drive circuit can also be set to access three frame start signal lines, that is, the start signal input terminal STV of the first-stage shift register is coupled to the first frame start signal line, the start signal input terminal STV of the second-stage shift register is coupled to the second frame start signal line, and the start signal input terminal STV of the third-stage shift register is coupled to the third frame start signal line.

[0151] Exemplarily, m=4, that is, the cascade signal output terminal CR of the nth shift register is coupled to the start signal input terminal STV of the n+4th shift register. In this case, the gate drive circuit can be connected to eight clock signal lines. At the same time, the gate drive circuit can be connected to a frame start signal line, that is, the start signal input terminals STV of the first shift register, the second shift register, the third shift register and the fourth shift register are all coupled to the frame start signal line. It is worth noting that in the case of m=4, the gate drive circuit can also be set to access four frame start signal lines, that is, the start signal input terminal STV of the first shift register is coupled to the first frame start signal line, the start signal input terminal STV of the second shift register is coupled to the second frame start signal line, the start signal input terminal STV of the third shift register is coupled to the third frame start signal line, and the start signal input terminal STV of the fourth shift register is coupled to the fourth frame start signal line.

[0152] An embodiment of the present invention further provides a display device, comprising: the gate driving circuit provided by the above embodiment.

[0153] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0154] The gate drive circuit provided in the above embodiment can effectively simplify the circuit complexity and ensure that the gate drive circuit can achieve better working characteristics. Therefore, when the display device provided in the embodiment of the present invention includes the above gate drive circuit, the frame area of ​​the display product can be further narrowed.

[0155] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0156] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0157] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0158] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0159] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0160] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0161] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: Output circuit; The output circuit includes a first output transistor, the first output transistor includes a dual-gate transistor, a top gate of the first output transistor is coupled to the cascade signal output terminal, a bottom gate of the first output transistor is coupled to the regulation terminal, a first electrode of the first output transistor is coupled to the first level signal input terminal, and a second electrode of the first output transistor is coupled to the gate drive signal output terminal; The cascade signal output terminal is used to control the first output transistor to be turned on or off, and the regulation terminal is used to control the characteristic parameters of the first output transistor.

2. The shift register according to claim 1, characterized in that: The output circuit further includes a second output transistor; the first output transistor includes an oxide transistor, and the second output transistor includes a low temperature polysilicon transistor; The gate of the second output transistor is coupled to the cascade signal output terminal, the first electrode of the second output transistor is coupled to the second level signal input terminal, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal.

3. The shift register according to claim 2, characterized in that: The shift register comprises a first first-level signal input terminal and a third first-level signal input terminal; the voltage value of the first-level signal inputted to the third first-level signal input terminal is smaller than the voltage value of the first-level signal inputted to the first first-level signal input terminal; The regulating end is coupled to the third first-level signal input end, and the first electrode of the first output transistor is coupled to the first first-level signal input end.

4. The shift register according to claim 2, characterized in that: The shift register comprises a second first level signal input terminal; The regulating end is coupled to the cascade signal output end, and the first electrode of the first output transistor is coupled to the second first level signal input end.

5. The shift register according to claim 2, characterized in that: The shift register comprises a first first-level signal input terminal and a second first-level signal input terminal; the voltage value of the first-level signal inputted to the first first-level signal input terminal is smaller than the voltage value of the first-level signal inputted to the second first-level signal input terminal; The output circuit further includes a tenth transistor, wherein the tenth transistor includes an oxide transistor with a dual-gate structure; A top gate of the tenth transistor is coupled to the cascade signal output terminal, a bottom gate of the tenth transistor is coupled to the cascade signal output terminal, a first electrode of the tenth transistor is coupled to the first first-level signal input terminal or the second first-level signal input terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the first output transistor; The shift register further includes: The leakage control circuit is coupled to the gate drive signal output terminal, the first voltage signal input terminal and the second electrode of the tenth transistor, respectively, and is used to control the conduction or disconnection of the electrical connection between the first voltage signal input terminal and the second electrode of the tenth transistor under the control of the gate drive signal output by the gate drive signal output terminal.

6. The shift register according to any one of claims 2 to 5, characterized in that: The shift register comprises a first second-level signal input terminal and a second second-level signal input terminal, wherein a voltage value of the second-level signal inputted by the second second-level signal input terminal is less than or equal to a voltage value of the second-level signal inputted by the first second-level signal input terminal; The first electrode of the second output transistor is coupled to the first second-level signal input terminal or the second second-level signal input terminal; The shift register further includes: A first cascade control circuit is coupled to the first node, the cascade signal output terminal and the second clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the cascade signal output terminal and the second clock signal input terminal under the control of the potential of the first node; The second cascade control circuit is coupled to the second node, the cascade signal output terminal and the first second level signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the cascade signal output terminal and the first second level signal input terminal under the control of the potential of the second node.

7. The shift register according to claim 6, characterized in that: The shift register further includes: A first node control circuit is coupled to the first node, the first first level signal input terminal and the third node respectively, and is used to control the conduction or disconnection of the electrical connection between the first node and the third node under the control of the first second level signal input terminal; The third node control circuit is coupled to the third node, the start signal input terminal and the first clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the third node and the start signal input terminal under the control of the first clock signal input terminal.

8. The shift register according to claim 7, characterized in that: The shift register further includes: A second node control circuit is coupled to the second node, the first clock signal input terminal and the fourth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second node and the fourth node under the control of the first clock signal input terminal; The fourth node control circuit is respectively coupled to the fourth node, the start signal input terminal, the first level signal input terminal and the first second level signal input terminal, and is used for controlling the conduction or disconnection of the electrical connection between the fourth node and the first level signal input terminal, and controlling the conduction or disconnection of the electrical connection between the fourth node and the first second level signal input terminal under the control of the start signal input at the start signal input terminal.

9. The shift register according to claim 8, characterized in that: The shift register comprises a first first-level signal input terminal and a third first-level signal input terminal, and the level value of the first-level signal inputted by the first first-level signal input terminal is greater than the level value of the first-level signal inputted by the third first-level signal input terminal; The fourth node control circuit includes a fifth transistor and a sixth transistor; The fifth transistor comprises an oxide transistor of a dual-gate structure, a top gate of the fifth transistor is coupled to the start signal input terminal, a bottom gate of the fifth transistor is coupled to the third first-level signal input terminal, a first electrode of the fifth transistor is coupled to the first first-level signal input terminal, and a second electrode of the fifth transistor is coupled to the fourth node; A gate of the sixth transistor is coupled to the start signal input terminal, a first electrode of the sixth transistor is coupled to the first second level signal input terminal, and a second electrode of the sixth transistor is coupled to the fourth node.

10. The shift register according to claim 8, characterized in that: The shift register comprises a first first-level signal input terminal and a second first-level signal input terminal, wherein the level value of the first-level signal inputted to the first first-level signal input terminal is smaller than the level value of the first-level signal inputted to the second first-level signal input terminal; The fourth node control circuit includes a fifth transistor and a sixth transistor; The fifth transistor comprises an oxide transistor of a dual-gate structure, a top gate of the fifth transistor is coupled to the start signal input terminal, a bottom gate of the fifth transistor is coupled to the first first-level signal input terminal, a first electrode of the fifth transistor is coupled to the second first-level signal input terminal, and a second electrode of the fifth transistor is coupled to the fourth node; A gate of the sixth transistor is coupled to the start signal input terminal, a first electrode of the sixth transistor is coupled to the first second level signal input terminal, and a second electrode of the sixth transistor is coupled to the fourth node.

11. The shift register according to claim 8, characterized in that: The shift register further includes: The anti-noise control circuit is coupled to the second clock signal input terminal, the second node, the first second-level signal input terminal and the third node respectively, and is used to control the conduction or disconnection of the electrical connection between the first second-level signal input terminal and the third node under the joint control of the second clock signal input to the second clock signal input terminal and the potential of the second node.

12. The shift register according to claim 11, characterized in that: The first cascade control circuit includes a second transistor and a first capacitor; the gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the second clock signal input terminal, and the second electrode of the second transistor is coupled to the cascade signal output terminal; the first electrode of the first capacitor is coupled to the first node, and the second electrode of the first capacitor is coupled to the cascade signal output terminal; The second cascade control circuit includes a first transistor and a second capacitor; the gate of the first transistor is coupled to the second node, the first electrode of the first transistor is coupled to the first second level signal input terminal, and the second electrode of the first transistor is coupled to the cascade signal output terminal; the first electrode of the second capacitor is coupled to the second node, and the second electrode of the second capacitor is coupled to the first second level signal input terminal; The first node control circuit comprises a fourth transistor, a gate of the fourth transistor is coupled to the first first level signal input terminal, a first electrode of the fourth transistor is coupled to the third node, and a second electrode of the fourth transistor is coupled to the first node; The third node control circuit comprises a third transistor, a gate of the third transistor is coupled to the first clock signal input terminal, a first electrode of the third transistor is coupled to the start signal input terminal, and a second electrode of the third transistor is coupled to the third node; The second node control circuit comprises a seventh transistor, a gate of the seventh transistor is coupled to the first clock signal input terminal, a first electrode of the seventh transistor is coupled to the fourth node, and a second electrode of the seventh transistor is coupled to the second node; In the case where the shift register includes a leakage control circuit, the leakage control circuit includes an eleventh transistor, a gate of the eleventh transistor is coupled to the gate drive signal output terminal, a first electrode of the eleventh transistor is coupled to the first voltage signal input terminal, and a second electrode of the eleventh transistor is coupled to a second electrode of the tenth transistor; The anti-noise control circuit includes a twelfth transistor and a thirteenth transistor; The gate of the twelfth transistor is coupled to the second node, the first electrode of the twelfth transistor is coupled to the first second-level signal input terminal, the second electrode of the twelfth transistor is coupled to the first electrode of the thirteenth transistor, the gate of the thirteenth transistor is coupled to the second clock signal input terminal, and the second electrode of the thirteenth transistor is coupled to the third node.

13. A gate drive circuit, characterized in that: The invention comprises a plurality of shift registers according to any one of claims 1 to 12 connected in cascade.

14. The gate driving circuit according to claim 13, characterized in that: The cascade signal output terminal of the nth stage shift register is coupled to the start signal input terminal of the n+mth stage shift register, where n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

15. A display device, characterized in that: include: The gate drive circuit as claimed in claim 13 or 14.

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