Method for controlling chip output mode and chip control circuit

Abstract

The present application relates to the field of chip technology, and more particularly to a method for controlling chip output modes and a chip control circuit. In the present application, the method for controlling chip output modes changes the output mode of the target chip by changing the input signals of different control pins of the target chip during the initial power-on process, thereby expanding the applicable scenarios of the target chip. This method does not require the use of an external control chip and also reduces hardware costs.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method for controlling a chip output mode and a chip control circuit. Background Art

[0002] After the chip is manufactured, its output mode is fixed, which limits its application scenarios. Figure 1a Take the touch lamp shown in the figure as an example. Generally, the chip output mode corresponding to the touch lamp is the switch output mode, that is, after the chip detects a touch operation, the lamp is turned on (that is, the output is high level) and the lamp remains on (that is, the high level is latched to continuously output a high level). After the touch operation is detected again, the lamp is turned off (that is, the output is low level). However, in some scenarios, users want the touch lamp to be turned on and off immediately, such as Figure 1b As shown, the chip corresponding to the touch lamp detects a touch operation and lights the bulb. When it detects that the touch lamp is no longer touched (for example, the user's hand leaves the touch lamp), it turns off the bulb. The chip output mode corresponding to the latter working mode is direct output mode. Obviously, the chip with switch output mode cannot meet the working requirements of the latter, which limits the application scenarios of the manufactured chip. Summary of the Invention

[0003] An embodiment of the present application provides a method for controlling a chip output mode and a chip control circuit, which reduces hardware costs by changing the output mode of a target chip by changing the input signals of different control pins of the target chip during the initial power-on process of the target chip.

[0004] In the first aspect, an embodiment of the present application provides a chip control circuit, including a control chip and a switch module; the control chip includes a first control pin, a first voltage control unit and a first latch unit; the switch module includes an output mode control switch, wherein the output mode control switch is connected to the first control pin; corresponding to the output mode control switch being closed, the first voltage control unit controls the first control pin to output a first level to the first latch unit, and the first level corresponds to the switch output mode; corresponding to the output mode control switch being turned on, the first voltage control unit controls the first control pin to output a second level to the first latch unit, and the second level corresponds to the direct output mode.

[0005] In a possible implementation of the first aspect above, the control chip further includes a first electrode, a second electrode, and an output pin, wherein the first end of the first control pin is connected to the first electrode through the output mode control switch, and the second end of the first control pin is connected to the first end of the first latch unit, for outputting a level signal to the first latch unit; the first end of the first voltage control unit is connected to the second end of the first control pin, and the second end of the first voltage control unit is connected to the second electrode, the first voltage control unit is used to control the level signal according to the opening and closing of the output mode control switch, and, corresponding to the output mode control switch being closed, the first voltage control unit controls the level corresponding to the level signal to be the first level; corresponding to the output mode control switch being turned on, the first voltage control unit controls the level corresponding to the level signal to be the second level.

[0006] In a possible implementation of the first aspect above, the first voltage control unit is further configured to receive a first pulse signal during power-on of the control chip, where the first pulse signal is configured to control the operation of the first voltage control unit.

[0007] In a possible implementation of the first aspect, a level corresponding to the first electrode is greater than a level corresponding to the second electrode, and the first level is greater than the second level.

[0008] In a possible implementation of the first aspect, the level corresponding to the first electrode is lower than the level corresponding to the second electrode, and the first level is lower than the second level.

[0009] In a possible implementation of the first aspect above, the first voltage control unit includes a first MOS tube and a first resistor, wherein the first end of the first resistor serves as the first end of the first voltage control unit, the second end of the first resistor is connected to the first end of the first MOS tube, the second end of the first MOS tube serves as the second end of the first voltage control unit, and the third end of the first MOS tube is used to receive the first pulse signal.

[0010] In a possible implementation of the first aspect, the first MOS transistor includes a P-type MOS transistor or an N-type MOS transistor.

[0011] In a possible implementation of the first aspect above, the control chip also includes a second control pin, a second voltage control unit and a second latch unit, and the switch module includes a polarity control switch, wherein the output mode control switch is connected to the second control pin, and the polarity control switch is connected to the second control pin; corresponding to the polarity control switch being closed, the second voltage control unit controls the second control pin to output a third level to the second latch unit, and the third level effectively corresponds to the output high level; corresponding to the polarity control switch being turned on, the second voltage control unit controls the second control pin to output a fourth level to the second latch unit, and the fourth level effectively corresponds to the output low level.

[0012] In a second aspect, embodiments of the present application provide a method for controlling a chip output mode, which is applied to a chip control circuit, wherein the chip control circuit includes a control chip and a switch module, the control chip includes a first control pin, a first voltage control unit, and a first latch unit; the switch module includes an output mode control switch, wherein the output mode control switch is connected to the first control pin; the method includes: corresponding to the output mode control switch being closed, controlling the first control pin to output a first level to the first latch unit via the first voltage control unit, wherein the first level corresponds to the switch output mode;

[0013] Corresponding to the output mode control switch being turned on, the first voltage control unit controls the first control pin to output a second level to the first latch unit, wherein the second level corresponds to the direct output mode.

[0014] In a possible implementation of the second aspect above, the control chip also includes a second control pin, a second voltage control unit and a second latch unit, and the switch module includes a polarity control switch, wherein the output mode control switch is connected to the second control pin, and the polarity control switch is connected to the second control pin; corresponding to the polarity control switch being closed, the second control pin is controlled by the second voltage control unit to output a third level to the second latch unit, and the third level effectively corresponds to the output high level; corresponding to the polarity control switch being turned on, the second control pin is controlled by the second voltage control unit to output a fourth level to the second latch unit, and the fourth level corresponds to the output low level.

[0015] In a third aspect, an embodiment of the present application provides a chip control circuit, comprising a control chip, the control chip comprising a first control pin and a signal selection circuit; the first control pin is used to receive and send a preset type of control signal to the signal selection circuit, the signal selection circuit is used to control the output mode of the control chip according to the preset type of control signal, wherein, corresponding to the first preset type of control signal, the signal selection circuit outputs a first type of signal to the control chip, the first type of signal corresponds to a direct output mode and is valid at a high level; corresponding to the second preset type of control signal, the signal selection circuit outputs a second type of signal to the control chip, the second type of signal corresponds to a direct output mode and is valid at a low level; corresponding to the third preset type of control signal, the signal selection circuit outputs a third type of signal to the control chip, the third type of signal corresponds to a switch output mode and is valid at a high level; corresponding to the fourth preset type of control signal, the signal selection circuit outputs a fourth type of signal to the control chip, the fourth type of signal corresponds to a switch output mode and is valid at a low level.

[0016] In a possible implementation of the third aspect above, the second preset type of control signal includes a pulse signal having one rising edge, the third preset type of control signal includes a pulse signal having two rising edges, and the fourth preset type of control signal includes a pulse signal having three rising edges.

[0017] In a possible implementation of the third aspect above, the signal selection circuit includes a master trigger, a slave trigger and a first logic circuit, wherein the master trigger is used to receive a preset type of control signal input by a first control pin, and the preset type of control signal is also used to control the master trigger to output a first output signal from the first output pin to the first logic circuit, and to output a second output signal different from the first output signal from the second output pin to the first logic circuit, and the preset type of control signal is also used to control the master trigger to input a second control signal to the slave trigger through the first output pin, and the second control signal is used to control the slave trigger to output a third output signal to the third input pin of the first logic circuit and to output a fourth output signal different from the third output signal to the fourth input pin of the first logic circuit, and the preset type of control signal is also used to control the first logic circuit to select at least one output signal from the received first output signal and second output signal, and to select at least one output signal from the received third output signal and fourth output signal, and output the at least two selected output signals to control the output mode of the chip to be a preset output mode corresponding to the at least two output signals.

[0018] In a possible implementation of the third aspect, the master trigger includes a rising-edge trigger, and the slave trigger includes a rising-edge trigger.

[0019] In a possible implementation of the third aspect above, the control signal of the first preset type includes a level signal whose voltage is lower than the first preset voltage, the control signal of the second preset type includes a level signal whose voltage is greater than the first preset voltage and less than the second preset voltage, the control signal of the third preset type includes a level signal whose voltage is greater than the second preset voltage and less than the third preset voltage, and the control signal of the fourth preset type includes a level signal whose voltage is greater than the third preset voltage.

[0020] In a possible implementation of the third aspect, the signal selection circuit includes a second logic circuit, a first comparator, a second comparator, and a third comparator, wherein a first preset voltage of the first comparator is less than a second preset voltage of the second comparator, the second preset voltage is less than a third preset voltage of the third comparator, and,

[0021] The first control pin is used to output a preset type of control signal to the first comparator, the second comparator, and the third comparator, wherein the preset type of control signal is used to control the first comparator to generate a first comparison signal, and to control the second comparator to generate a second comparison signal, and further to control the third comparator to generate a third comparison signal.

[0022] The first logic circuit generates an output signal according to the first comparison signal, the second comparison signal and the third comparison signal, and outputs the output signal to control the output mode of the chip to be a preset output mode corresponding to the output signal.

[0023] In a fourth aspect, an embodiment of the present application provides a method for controlling a chip output mode, using a chip control circuit, the chip control circuit including a control chip, the control chip including a first control pin and a signal selection circuit;

[0024] The first control pin is used to receive and send a preset type of control signal to the signal selection circuit, and the signal selection circuit is used to control the output mode of the control chip according to the preset type of control signal. The method includes: corresponding to the first preset type of control signal, outputting a first type of signal to the control chip through the signal selection circuit, the first type of signal corresponds to the direct output mode and the high level is valid; corresponding to the second preset type of control signal, outputting a second type of signal to the control chip through the signal selection circuit, the second type of signal corresponds to the direct output mode and the low level is valid; corresponding to the third preset type of control signal, outputting a third type of signal to the control chip through the signal selection circuit, the third type of signal corresponds to the switch output mode and the high level is valid; corresponding to the fourth preset type of control signal, outputting a fourth type of signal to the control chip through the signal selection circuit, the fourth type of signal corresponds to the switch output mode and the low level is valid.

[0025] In a possible implementation of the fourth aspect above, the second preset type of control signal includes a pulse signal having one rising edge, the third preset type of control signal includes a pulse signal having two rising edges, and the fourth preset type of control signal includes a pulse signal having three rising edges.

[0026] In a possible implementation of the fourth aspect above, the signal selection circuit includes a master trigger, a slave trigger and a first logic circuit, wherein the master trigger is used to receive a preset type of control signal input by a first control pin, and the preset type of control signal is also used to control the master trigger to output a first output signal from the first output pin to the first logic circuit, and to output a second output signal different from the first output signal from the second output pin to the first logic circuit, and the preset type of control signal is also used to control the master trigger to input a second control signal to the slave trigger through the first output pin, and the second control signal is used to control the slave trigger to output a third output signal to the third input pin of the first logic circuit and to output a fourth output signal different from the third output signal to the fourth input pin of the first logic circuit, and the preset type of control signal is also used to control the first logic circuit to select at least one output signal from the received first output signal and second output signal, and to select at least one output signal from the received third output signal and fourth output signal, and output the at least two selected output signals to control the output mode of the chip to be a preset output mode corresponding to the at least two output signals.

[0027] In a possible implementation manner of the fourth aspect above, the master trigger includes a rising-edge trigger, and the slave trigger includes a rising-edge trigger.

[0028] In a possible implementation of the fourth aspect above, the control signal of the first preset type includes a level signal whose voltage is lower than the first preset voltage, the control signal of the second preset type includes a level signal whose voltage is greater than the first preset voltage and less than the second preset voltage, the control signal of the third preset type includes a level signal whose voltage is greater than the second preset voltage and less than the third preset voltage, and the control signal of the fourth preset type includes a level signal whose voltage is greater than the third preset voltage.

[0029] In a possible implementation of the fourth aspect above, the signal selection circuit includes a second logic circuit, a first comparator, a second comparator and a third comparator, wherein the first preset voltage of the first comparator is less than the second preset voltage of the second comparator, the second preset voltage is less than the third preset voltage of the third comparator, and the first control pin is used to output a preset type of control signal to the first comparator, the second comparator and the third comparator, the preset type of control signal is used to control the first comparator to generate a first comparison signal, and to control the second comparator to generate a second comparison signal, and also to control the third comparator to generate a third comparison signal, the second logic circuit generates an output signal according to the first comparison signal, the second comparison signal and the third comparison signal, and outputs the output signal to control the output mode of the chip to be a preset output mode corresponding to the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a According to an embodiment of the present application, a working mode of a touch lamp in a switch output mode is shown;

[0031] Figure 1b According to an embodiment of the present application, a working mode of a touch lamp in direct output mode is shown;

[0032] Figure 2 According to an embodiment of the present application, a method of controlling the output mode of the target chip 01 by means of an external control chip 02 is shown;

[0033] Figure 3 According to an embodiment of the present application, a circuit structure diagram of a target chip 01 for implementing the method of the present application is shown;

[0034] Figure 4a According to the embodiment of the present application, Figure 3 Schematic diagram of a circuit structure for controlling the output mode of the target chip 01 through the first control pin 011;

[0035] Figure 4b According to the embodiment of the present application, Figure 3 Schematic diagram of a circuit structure for controlling the output mode of the target chip 01 through the second control pin 012;

[0036] Figure 5 According to an embodiment of the present application, a circuit structure diagram of a target chip 01 for implementing the method of the present application is shown;

[0037] Figure 6a According to the embodiment of the present application, Figure 5 Schematic diagram of a circuit structure for controlling the output mode of the target chip 01 through the first control pin 011;

[0038] Figure 6b According to the embodiment of the present application, Figure 5 Schematic diagram of a circuit structure for controlling the output mode of the target chip 01 through the second control pin 012;

[0039] Figure 7a According to an embodiment of the present application, a circuit structure diagram of a target chip 01 for implementing the method of the present application is shown;

[0040] Figure 7b According to the embodiment of the present application, Figure 7a After the first control pin 011 inputs different types of control pulse signals, Figure 7a Schematic diagram of the output signals of each trigger;

[0041] Figure 8a According to an embodiment of the present application, a circuit structure diagram of a target chip 01 for implementing the method of the present application is shown;

[0042] Figure 8b According to the embodiment of the present application, Figure 8a After applying different voltages to the first control pin 011, Figure 8a Schematic diagram of the output signals of each trigger;

[0043] Figure 9 According to an embodiment of the present application, a schematic diagram of the internal structure of a chip 900 is shown. Specific embodiments

[0044] The present application provides a method for controlling the output mode of a chip. The following will use terms commonly used by those skilled in the art to describe various aspects of the illustrative embodiments. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A or B exists at the same time, and B exists alone. In addition, in the description of the implementation of the present application, "multiple" refers to two or more than two.

[0045] In the following, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. Thus, a feature designated "first," "second," or "third" may explicitly or implicitly include one or more of such features.

[0046] In order to solve the above technical problems, in some implementations, an external control chip can be introduced, and R&D personnel can input preset input signals corresponding to various output modes into the external control chip to change the output mode of the target chip.

[0047] For example, Figure 2 FIG. 1 shows a schematic diagram of controlling the output mode of the target chip through the control chip. Figure 2 As shown, the output pin 021 of the control chip 02 is connected to the first control pin 011 of the target chip 01, and is used to output different types of signals to the target chip 01 to control the output pin of the target chip 01 to output different types of signals, that is, to control the output mode of the target chip, so that the output mode of the target chip can change according to specific needs, thereby expanding the applicable scenarios of the target chip.

[0048] In some implementations, the correspondence between different types of signals input to the external control chip and the output modes of the target chip may be as shown in Table 1 below:

[0049] Table 1 Correspondence between different types of signals input to the control chip and the output modes of the target chip

[0050] Different types of signals input to the control chip Output mode of the target chip 0001 High level valid, direct output mode 0010 High level valid, direct output mode 0011 Low level is valid, switch output mode 0100 Low level is valid, switch output mode

[0051] Among them, high level active means that when the output is high level, the electronic device is turned on, for example, when the output is high level, the touch light is turned on. Low level active means that when the output is low level, the electronic device is turned on, for example, when the output is low level, the touch light is turned on.

[0052] In this way, the output mode of the target chip can be changed, thereby expanding the applicable scenarios of the target chip.

[0053] However, this approach requires the introduction of an additional control chip, which increases the design cost of the circuit.

[0054] In this regard, the present application provides a method for controlling chip output mode. In the method for controlling chip output mode of the present application, the output mode of the target chip is changed by changing the level signals of different control pins of the target chip during the initial power-on process of the target chip.

[0055] Figure 3 A chip capable of implementing the method of controlling chip output mode of the present application is shown. Figure 3 As shown, target chip 01 includes a first control pin 011, a second control pin 012, and an output pin 013. In some implementations, first control pin 011 can be configured as an output mode control pin, and second control pin 012 can be configured as an output polarity control pin. A switch S1 is provided between first control pin 011 and the VDD terminal (connected to the chip's internal operating power supply), and a switch S2 is provided between second control pin 012 and the VDD terminal. Switch S1 is then opened and closed to control the connection and disconnection of the circuit between first control pin 011, the VDD terminal, and the VSS (ground) terminal, while switch S2 is opened and closed to control the connection and disconnection of the circuit between second control pin 012, the VDD terminal, and the VSS terminal. The output polarity determines whether the output is active high or active low. The output mode determines whether the output mode of output pin 013 of target chip 01 is the switch output mode described above or the direct output mode.

[0056] When the output mode of the output pin 013 of the target chip 01 needs to be changed, the target chip 01 is powered on again, and the input signals (or levels) of the first control pin 011 and the second control pin 012 are changed by controlling the opening and closing of switches S1 and S2 to achieve the output mode of the output pin 013.

[0057] For example, for Figure 1a Assume that the circuit corresponding to the touch lamp is as follows Figure 3As shown, in this circuit, if you need to change the operating mode of the chip corresponding to the touch lamp to the switch output mode, then before performing a touch operation on the touch lamp, first cut off the power supply to the touch lamp and repower on the chip only for the touch lamp. During the power-on process, close switch S1, making the level of the first control pin 011 high, so that the level signal output by the output pin 013 is also high, that is, the output mode corresponding to the output pin 013 is the direct output mode. At the same time, close switch S2, making the level of the second control pin 012 high, so that the output polarity of the output pin 013 is high (i.e., the touch lamp is lit when the output is high). Then, after the touch lamp chip is powered on, connect the power supply to the touch lamp. At this time, the output mode of the touch lamp chip is the direct output mode.

[0058] More specifically, Figure 4a A circuit diagram showing how to control the output polarity of the target chip 01 by controlling the first control pin 011 of the target chip 01 is shown. Figure 4b The circuit diagram of controlling the output mode of the target chip 01 by controlling the second control pin 012 of the target chip 01 is shown. Figure 3 as well as Figure 4a 、 Figure 4b This article introduces the implementation process of the output mode of the control chip in this application.

[0059] Combine Figure 3 like Figure 4a As shown, the circuit includes a VDD electrode, a switch S1, a first control pin 011, a voltage control unit consisting of a first resistor R1 and a first MOS transistor 017, a VSS electrode, and a latch unit S consisting of a first trigger 015 and a first comparator 016. One end of the first control pin 011 is connected to the VDD electrode through the switch S1, and the other end is connected to a first end 0151 of the first trigger 015. A second end 0152 of the first trigger 015 is connected to a first end 0161 of the first comparator 016. The first end 0161 of the first comparator 016 is connected to an output pin 013 of the target chip 01.

[0060] At the same time, the other end of the first control pin 011 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the first end 0171 of the first MOS transistor 017, and the second end 0172 of the first MOS transistor 017 is connected to the input pin 014 of the target chip 01 for receiving a first pulse (PLUSE). The first pulse is used to control the latch unit S to latch the high or low level signal input by the first control pin 011. The third end 0173 of the first MOS transistor 017 is connected to the VSS electrode.

[0061] In some implementations, the first MOS transistor 017 includes a MOS transistor that operates when receiving a high-level pulse signal, such as an N-type MOS transistor.

[0062] In some implementations, during the power-on process of the target chip 01, a first pulse is generated inside the target chip 01. The first pulse is input to the first MOS transistor 017 through the second terminal 0172 of the first MOS transistor 017, thereby conducting the circuit between the first resistor R1, the first MOS transistor 017, and the VSS terminal. At this time, by adjusting the opening and closing of the switch S1, the conduction of the circuit between the VDD terminal, the first control pin 011, and R1 can be controlled, thereby changing the level of the end of the first control pin 011 connected to the first resistor R1 (to change it to the power supply voltage VDD or VSS voltage), thereby controlling the level signal latched by the latch unit S, and controlling the output signal of the output pin 013 after power-on is completed, thereby achieving the purpose of changing the output mode of the target chip 01.

[0063] For example, Figure 4a As shown, during the power-up process of target chip 01, first MOS transistor 017 is turned on by the first pulse. At this point, switch S1 is closed, connecting the VDD terminal, first control pin 011, first resistor R1, first MOS transistor 017, and VSS terminal. First control pin 011 is at VDD voltage. Latch unit S latches the high level input to first control pin 011 and outputs it through output pin 013, setting output pin 013 to direct output mode.

[0064] For example, during the power-up process of target chip 01, switch S1 is not closed, and the circuit between the VDD terminal, first control pin 011, first resistor R1, first MOS transistor 017, and VSS terminal is disconnected. At this time, the voltage level at end 0151, one end of first control pin 011 connected to first trigger 015, is at the same low level (VSS terminal level) as the voltage level of first resistor R1 due to the action of first resistor R1. Latch unit S latches the low level input by first control pin 011 and outputs it through output pin 013, setting the output mode of output pin 013 to switch output mode.

[0065] In some implementations, the output mode corresponding to when the latch unit S latches a high level may be set to a direct output mode, and the output mode corresponding to when the latch unit S latches a low level may be set to a switch output mode. This application does not impose any restrictions on this.

[0066] Through the above method, the output mode of the target chip 01 can be controlled by opening and closing the switch S1.

[0067] In some implementations, as mentioned above, other control pins of the target chip 01 may be further used to control the output polarity of the target chip 01. Figure 3 like Figure 4b As shown, the circuit includes a VDD terminal, a switch S2, a second control pin 012, a voltage control unit consisting of a first resistor R2 and a second MOS transistor 018, a VSS terminal, and a latch unit S' consisting of a second flip-flop 015' and a second comparator 016'. One end of the second control pin 012 is connected to the VDD terminal via the switch S2, and the other end is connected to a first end 0151' of the second flip-flop 015'. The second end 0152' of the second flip-flop 015' is connected to a first end 0161' of the second comparator 016'. The first end 161' of the second comparator 016' is connected to the output pin 013 of the target chip 01. At the same time, the other end of the second control pin 012 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the first end 0181 of the second MOS transistor 018, and the second end 0182 of the second MOS transistor 017' is connected to the input pin 014 of the target chip 01 for receiving a first pulse. This first pulse is used to control the latch unit S' to latch the high or low level signal input by the second control pin 012. The third end 0183 of the second MOS transistor 018 is connected to the VSS electrode.

[0068] In some implementations, the second MOS transistor 018 includes a MOS transistor that operates when receiving a high-level pulse signal, such as an N-type MOS transistor.

[0069] In some implementations, such as Figure 4b As shown, during the power-up process of target chip 01, second MOS transistor 018 is turned on by the first pulse. At this point, switch S2 is closed, connecting the VDD terminal, second control pin 012, second resistor R2, and VSS terminal. Second control pin 012 is at a high level. Latch unit S′ latches the high level input to second control pin 012 and outputs it through output pin 013, making the output polarity of output pin 013 active high.

[0070] During the power-up process of target chip 01, if switch S2 is not closed, the circuit between VDD, second control pin 012, second resistor R2, and VSS is disconnected. The voltage level at the end of second control pin 012 connected to second trigger 015′, under the action of second resistor R1, becomes the same as the voltage level of second resistor R2, reaching a low level (VSS level). Latch unit S′ latches the low voltage input from second control pin 012 and outputs it through output pin 013, making the output polarity of output pin 013 active high.

[0071] In some implementations, the output polarity corresponding to when the latch unit S' latches a high level can be set to be low level active, and the output mode corresponding to when the latch unit S' latches a low level can be set to be high level active. This application does not limit this.

[0072] It is not difficult to understand that through the above method, when the output mode of target chip 01 needs to be direct output mode and high level is valid, switch S1 is closed and switch S2 is closed; when the output mode of target chip 01 needs to be direct output mode and low level is valid, switch S1 is closed and switch S2 is opened; when the output mode of target chip 01 needs to be switch output mode and high level is valid, switch S1 is opened and switch S2 is closed; when the output mode of target chip 01 needs to be switch output mode and low level is valid, switch S1 is opened and switch S2 is opened. In this way, the purpose of controlling the output polarity and output mode of the output pin of target chip 01 by controlling the opening and closing of switches S1 and S2 respectively is achieved, thereby expanding the applicable scenarios of target chip 01.

[0073] In some implementations, this can also be accomplished by Figure 5 The circuit structure of the target chip shown in FIG. 1 changes the target chip output mode. Specifically, compared to Figure 3 , Figure 5 The circuit difference of the target chip shown is that one end of the first control pin 011 is connected to the VSS pole, and one end of the second control pin 012 is also connected to the VSS pole. More specifically, Figure 6a A circuit diagram showing how to control the output polarity of the target chip 01 by controlling the first control pin 011 of the target chip 01 is shown. Figure 6b It shows a circuit diagram for controlling the output mode of the target chip 01 by controlling the second control pin 012 of the target chip 01 .

[0074] contrast Figure 4a , Figure 6a The difference between the circuits shown is that, to implement the present invention's method during the target chip power-up process, a first inverter 020 is added before the second end 0172' of the third MOS transistor 017'. The function of the first inverter 020 is to invert the first pulse to trigger the operation of the third MOS transistor 017'. In some implementations, the third MOS transistor 017' includes a MOS transistor that operates when receiving a low-level pulse signal, such as a P-type MOS transistor.

[0075] The third end of the third MOS transistor 017' is connected to the VDD pole, the first end of the third MOS transistor 017' is connected to one end of the first resistor R1, and one end of the first control pin 011 is connected to the VSS pole through the switch S1.

[0076] In some implementations, during the power-on process of the target chip 01, the third MOS transistor 017′ is turned on by the first pulse that has undergone the flipping process. At this time, if the switch S1 is closed, the circuit between the VDD electrode, the third MOS transistor 017′, the first resistor R1, and the first control pin 011 is connected, and the level of the end 0151 of the first control pin 011 connected to the first trigger 015 is low (VSS level). At this time, the latch unit S latches the low-level signal and outputs it through the output pin 013, so that the output mode of the target chip 01 changes to the switch output mode.

[0077] In some implementations, during the power-on process of the target chip 01, the third MOS transistor 017′ is turned on by the first pulse that has undergone a flipping process. At this time, if the switch S1 is not closed, the circuit between the VDD pole, the third MOS transistor 017′, the first resistor R1, and the first control pin 011 is disconnected. In addition, under the action of the first resistor R1, the level of the end 0151 of the first control pin 011 connected to the first trigger 015 is pulled up to a high level (but less than the power supply voltage VDD) by the first resistor R1. At this time, the latch unit S latches the high-level signal and outputs it through the output pin 013, so that the output mode of the target chip 01 changes to a direct output mode.

[0078] In some implementations, the output mode corresponding to when the latch unit S latches a low level may be set to a direct output mode, and the output mode corresponding to when the latch unit S latches a high level may be set to a switch output mode. This application does not impose any restrictions on this.

[0079] In the above manner, during the power-on process of the target chip 01 , the switch S1 is opened and closed to change the signal latched by the latch unit S, thereby changing the output mode of the output pin 013 of the target chip 01 .

[0080] Similarly, contrast Figure 4b , Figure 6b To implement the present invention's method during the target chip power-up process, the circuit shown includes a second inverter 030 located before the second terminal 0182' of the fourth MOS transistor 018'. The first inverter 030 inverts the first pulse to trigger the operation of the fourth MOS transistor 018'. In some implementations, the fourth MOS transistor 018' comprises a MOS transistor, such as a P-type MOS transistor, that operates upon receiving a low-level pulse signal.

[0081] The third terminal 0183' of the fourth MOS transistor 018' is connected to the VDD pole, the first terminal 0181' of the fourth MOS transistor 018' is connected to one end of the first resistor R1, and one end of the first control pin 011 is connected to the VSS pole through the switch S1.

[0082] In some implementations, during the power-on process of the target chip 01, the fourth MOS transistor 018′ is turned on by the first pulse that has undergone the flipping process. At this time, if the switch S2 is closed, the circuit between the VDD electrode, the fourth MOS transistor 018′, the second resistor R2, and the second control pin 012 is connected, and the level of the end 0151′ connected to the second trigger 015′ of the second control pin 012 is low (VSS level). At this time, the latch unit S latches the low-level signal and outputs it through the output pin 013, so that the output polarity of the target chip 01 becomes valid high.

[0083] In some implementations, during the power-on process of the target chip 01, the fourth MOS transistor 018′ is turned on by the first pulse that has undergone the flipping process. At this time, if the switch S2 is not closed, the circuit between the VDD pole, the fourth MOS transistor 018′, the second resistor R2, and the second control pin 012 is disconnected. In addition, under the action of the second resistor R2, the level of the end 0151′ of the second control pin 012 connected to the second trigger 015′ is pulled up to a high level (but less than the power supply voltage VDD) by the second resistor R2. At this time, the latch unit S′ latches the high-level signal and outputs it through the output pin 013, so that the output polarity of the target chip 01 becomes a low-level valid output.

[0084] In some implementations, the output polarity corresponding to when the latch unit S' latches a low level can be set to output a high level valid, and the output polarity corresponding to when the latch unit S' latches a high level can be set to output a low level valid. This application does not limit this.

[0085] In the above manner, during the power-on process of the target chip 01 , the switch S2 is opened and closed to change the signal latched by the latch unit S′, thereby changing the output polarity of the output pin 013 of the target chip 01 .

[0086] In summary, through Figure 6a as well as Figure 6b The circuit shown can change the output mode of the target chip 01 by controlling the opening and closing of the switches S1 and S2 respectively, thereby expanding the application scenarios of the target chip 01.

[0087] In other implementations of the present application, the latching function of the trigger inside the target chip and the selection function of the logic circuit can also be utilized. During the power-on process of the target chip (i.e., when the above-mentioned first pulse is generated inside the target chip), different pulses are input to the first control pin 011, so that the trigger inside the target chip generates different output signals. The different output signals generated by the trigger are then selected by the logic circuit to obtain output signals corresponding to different output modes. In some implementations, the correspondence between different output signals and output modes can be pre-set by the R&D personnel, and this application does not impose any restrictions on this.

[0088] Specifically, Figure 7a The internal circuit diagram of the target chip 01 implementing the method of the present application is shown. Figure 7b Shown with Figure 7a The corresponding relationship between the different pulse signals received by the corresponding first control pin and the corresponding trigger output signal.

[0089] refer to Figure 7a The target chip 01 includes a first control pin 011, a first trigger 04, a second trigger 05, a logic circuit 03, and an output pin 013. The first control pin 011 is connected to the CK pin of the first trigger 04, and is used to output different control pulse signals received by the first trigger 04 to the first trigger 04 to trigger the first trigger 04 to work. The QN pin of the first trigger 04 has a level opposite to that of the Q pin. In some implementations, when the first trigger 04 is working, the Q pin of the first trigger 04 is at a high level, that is, Q1 is at a high level (1); when the first trigger 04 is not working, the Q pin of the first trigger 04 is at a low level, that is, Q1 is at a low level (0).

[0090] At the same time, the QN pin of the first flip-flop 04 inputs different control pulse signals to the CK pin of the second flip-flop 05 to control the operation of the second flip-flop 05. Similarly, in some implementations, when the first flip-flop 05 is operating, the Q pin of the first flip-flop 05 is at a high level, that is, Q2 is at a high level (1); when the first flip-flop 05 is not operating, the Q pin of the first flip-flop 05 is at a low level, that is, Q2 is at a low level (0).

[0091] The Q pin of the first trigger 04 is connected to the first pin 031 of the logic circuit 03, and the Q1 signal is input to the logic circuit 03. The QN1 pin of the first trigger 04 is connected to the second pin 032 of the logic circuit 03, and the QN1 signal is input to the logic circuit 03. The Q pin of the second trigger 05 is connected to the third pin 033 of the logic circuit 03, and the Q2 signal is input to the logic circuit 03. The QN pin of the second trigger 05 is connected to the fourth pin 034 of the logic circuit 03, and the QN2 signal is input to the logic circuit 03.

[0092] Then, an output pin (not shown in the figure) of the logic circuit 03 is connected to the output pin 013 of the target chip 01 .

[0093] Based on the above Figure 7a In the circuit shown, when different control pulse signals are input to the first control pin 011, the first trigger 04 will generate corresponding Q1 and QN1 signals, and the second trigger 05 will generate corresponding Q2 and QN2 signals. Then, through the selection of Q1, QN1, Q2, and QN2 by the logic circuit 03, different output signals can be obtained to control the target chip 01 to output different output modes.

[0094] In some implementations, such as Figure 7b As shown, assuming that a type 1 control pulse signal is input to the first control pin 011, then since the first flip-flop 04 is a rising edge flip-flop, it will only work when it receives a rising edge pulse signal. Since the type 1 control pulse signal does not have a rising edge pulse, the first flip-flop 04 does not work, and therefore the Q pin level Q1 of the first flip-flop 04 is low level (0), and the corresponding QN pin level QN1 of the first flip-flop 04 is high level (1). Correspondingly, the CK pin of the second flip-flop 05 receives the QN1 signal output by the QN pin of the first flip-flop 04. Since the QN1 signal also does not have a rising edge pulse, the second flip-flop 05 does not work either, and therefore the Q pin level Q2 of the second flip-flop 05 is low level (0). The corresponding QN pin level QN2 of the second flip-flop 05 is high level (1).

[0095] After the above Q1, QN1, Q2, and QN2 signals pass through the logic circuit 03, the logic circuit 03 selects and outputs the Q1 and Q2 signals, so that the final output signal of the logic circuit 03 is <00> , thereby converting the output mode corresponding to the target chip 01 into an output signal <00> The corresponding output mode and output polarity, such as the output signal <00> The corresponding output mode is a switching output mode, and the output polarity is active high. In some implementations, the logic circuit 03 may also select to output the QN1 and QN2 signals, or the Q1 and QN2 signals, or the Q2 and QN1 signals, but this application does not limit this. For ease of description, the following description will continue using the example of the logic circuit 03 selecting to output the Q1 and Q2 signals.

[0096] In some implementations, continue as Figure 7bAs shown, assuming that a type 2 control pulse signal is input to the first control pin 011, then since the first flip-flop 04 is a rising edge flip-flop, it will only work when it receives a rising edge pulse signal. Since the type 2 control pulse signal only has one rising edge pulse at time t1, the first flip-flop 04 works at time t1. Therefore, at time t1, the Q pin level Q1 of the first flip-flop 04 is high (1), and the corresponding QN pin level QN1 of the first flip-flop 04 is low (0). Correspondingly, from time t1 to t2, the QN1 signal output by the QN pin of the first flip-flop 04 received by the CK pin of the second flip-flop 05 changes from high (1) to low (0), and does not have a rising edge pulse. Therefore, the second flip-flop 05 does not work, and the Q pin level Q2 of the second flip-flop 05 is still low (0). The corresponding QN pin level QN2 of the second flip-flop 05 is still high (1).

[0097] After the above Q1, QN1, Q2, and QN2 signals pass through the logic circuit 03, the logic circuit 03 selects and outputs the Q1 and Q2 signals, so that the final output signal of the logic circuit 03 is <10> , thereby converting the output mode corresponding to the target chip 01 into an output signal <10> The corresponding output mode and output polarity, such as the output signal <10> The corresponding output mode is switch output mode, and the output polarity is low level valid.

[0098] In some implementations, continue as Figure 7b As shown, assuming that a type 3 control pulse signal is input to the first control pin 011, then since the first trigger 04 is a rising edge trigger, it will only work when it receives a rising edge pulse signal. Since the type 3 control pulse signal only has a rising edge pulse at t1 and t3, the first trigger 04 works at t1 and t3, that is, at t1, the Q pin level Q1 of the first trigger 04 is high (1), and the corresponding level QN1 of the QN pin of the first trigger 04 is low (0). At t3, the Q pin level Q1 of the first trigger 04 changes to low (0), and the corresponding level QN1 of the QN pin of the first trigger 04 is high (1). Correspondingly, from t1 to t3, the QN1 signal output by the QN pin of the first trigger 04 received by the CK pin of the second trigger 05 changes from low (0) to high (1), with a rising edge pulse. Therefore, the second trigger 05 works, and therefore the Q pin level Q2 of the second trigger 05 is high (1). The corresponding QN pin level QN2 of the second flip-flop 05 is low level (0).

[0099] After the above Q1, QN1, Q2, and QN2 signals pass through the logic circuit 03, the logic circuit 03 selects and outputs the Q1 and Q2 signals, so that the final output signal of the logic circuit 03 is <01> , thereby converting the output mode corresponding to the target chip 01 into an output signal <01> The corresponding output mode and output polarity, such as the output signal <01> The corresponding output mode is direct output mode, and the output polarity is high level valid.

[0100] In some implementations, continue as Figure 7b As shown, assuming that a type 3 control pulse signal is input to the first control pin 011, the first trigger 04 will only work when it receives a rising edge pulse signal because the type 4 control pulse signal has a rising edge pulse only at t1, t3, and t5. Therefore, the first trigger 04 works at t1, t3, and t5. That is, at t1, the Q pin level Q1 of the first trigger 04 is high (1), and the corresponding QN pin level QN1 of the first trigger 04 is low (0). At t3, the Q pin level Q1 of the first trigger 04 changes to low (0), and the corresponding QN pin level QN1 of the first trigger 04 is high (1). At t5, the Q pin level Q1 of the first trigger 04 changes to high (1), and the corresponding QN pin level QN1 of the first trigger 04 is low (0).

[0101] Accordingly, from time t1 to t5, the QN1 signal outputted by the QN pin of the first flip-flop 04 and received by the CK pin of the second flip-flop 05 changes from a low level (0) to a high level (1) and then to a low level (0), with one rising edge pulse. Therefore, the second flip-flop 05 operates, and therefore the Q pin level Q2 of the second flip-flop 05 is a high level (1). Correspondingly, the QN pin level QN2 of the second flip-flop 05 is a low level (0).

[0102] After the above Q1, QN1, Q2, and QN2 signals pass through the logic circuit 03, the logic circuit 03 selects and outputs the Q1 and Q2 signals, so that the final output signal of the logic circuit 03 is <11> , thereby converting the output mode corresponding to the target chip 01 into an output signal <11> The corresponding output mode and output polarity, such as the output signal <11> The corresponding output mode is direct output mode, and the output polarity is low level valid.

[0103] Through the above method, the output mode of the target chip can be controlled by the trigger and logic circuit inside the target chip. Figure 2In the manner shown, the implementation of the present application does not require the help of an external control chip, and can achieve the purpose of changing the output mode of the target chip by only using the trigger and logic circuit already inside the target chip. Moreover, the implementation of the present application only uses one control pin (i.e., the first control pin) to achieve the purpose of changing the output mode of the target chip, which is different from the above. Figures 3 to 5 As shown in the embodiment, the implementation of the present application can effectively improve the utilization rate of the target chip pins.

[0104] Similarly, in some implementations, multiple comparators, each with a different rated voltage, can be added to the target chip. The voltage signal input to the first control pin is then compared with the rated voltage values ​​corresponding to the multiple comparators. The comparators output different comparison signals based on the different comparison results. These comparison signals are then selected using the logic circuitry within the target chip to output different output signals. These output signals correspond to different output modes, and the target chip's output signal, and thus its output mode, can be changed by controlling the input voltage to the first control pin.

[0105] Specifically, Figure 8a FIG. 1 shows an internal circuit diagram of the target chip 01 capable of implementing the method of the present application. Figure 8a As shown, the target chip 01 includes a first control pin 011 , a first comparator 06 , a second comparator 07 , a third comparator 08 , a logic circuit 03 ′ and an output pin 013 .

[0106] The first control pin 011 is connected to the first terminal 061 of the first comparator 06, the first terminal 071 of the second comparator 07, and the first terminal 081 of the third comparator 08, respectively. The second terminal 062 of the first comparator 06 is a rated voltage vref1, and the third terminal 063 is connected to the first pin 031′ of the logic circuit 03′. The second terminal 072 of the second comparator 07 is a rated voltage vref2, and the third terminal 073 of the second comparator 07 is connected to the second pin 032′ of the logic circuit 03′. The second terminal 082 of the third comparator 08 is a rated voltage vref3, and the third terminal 083 of the third comparator 08 is connected to the third pin 033′ of the logic circuit 03′. The rated voltages vref1, vref2, and vref3 have the following relationship: vref1 < vref2 < vref3. An output pin (not shown) of the logic circuit 03′ is connected to the output pin 013 of the target chip 01.

[0107] Based on the above Figure 8aIn the circuit shown, when different voltage signals are input to the first control pin 011, the first comparator 06 compares the voltage at its first end (i.e., the voltage input to the first control pin 011) with its rated voltage vref1 to obtain a first comparison signal (OUT1), the second comparator 07 compares the voltage at its first end (i.e., the voltage input to the first control pin 011) with its rated voltage vref2 to obtain a second comparison signal (OUT2), and the third comparator 08 compares the voltage at its first end (i.e., the voltage input to the first control pin 011) with its rated voltage vref3 to obtain a third comparison signal (OUT3).

[0108] After the comparison signals are selected by the logic circuit 03', different output signals are obtained, each of which corresponds to an output mode. The correspondence between each output signal and the output mode can be pre-set by the R&D personnel, and this application does not impose any restrictions on this.

[0109] Specifically, in some implementations, such as Figure 8b As shown, assuming that the voltage C1 input to the first control pin 011 is less than the rated voltage vref1 of the first comparator, the first comparison signal OUT1 output by the first comparator 06 is a low level (0). Since the rated voltages of the first comparator 06, the second comparator 07 and the third comparator 08 have the above relationship, the second comparison signal output by the second comparator 07 is also a low level (0), and the third comparison signal output by the third comparator 08 is also a low level (0).

[0110] After the above comparison signals pass through the logic circuit 03′, the logic circuit 03′ outputs all three comparison signals to obtain the output signal <0,0,0>, thereby changing the output mode corresponding to the target chip 01 to the output mode and output polarity corresponding to the output signal <0,0,0>. For example, the output mode corresponding to the output signal <0,0,0> is the direct output mode, and the output polarity is low level valid.

[0111] In some implementations, such as Figure 8b As shown, assuming that the voltage C1 input to the first control pin 011 is greater than the rated voltage vref1 of the first comparator and less than the rated voltage vref2 of the second comparator 07, the first comparison signal OUT1 output by the first comparator 06 is a high level (1), and the second comparison signal OU2 output by the second comparator 07 is a low level (0). Since the rated voltages of the first comparator 06, the second comparator 07 and the third comparator 08 have the above relationship, the third comparison signal output by the third comparator 08 is also a low level (0).

[0112] After the above comparison signals pass through the logic circuit 03′, the logic circuit 03′ outputs all three comparison signals to obtain the output signal <1,0,0>, thereby changing the output mode corresponding to the target chip 01 to the output mode and output polarity corresponding to the output signal <1,0,0>. For example, the output mode corresponding to the output signal <1,0,0> is the direct output mode, and the output polarity is high level valid.

[0113] In some implementations, such as Figure 8b As shown, assuming that the voltage C1 input to the first control pin 011 is greater than the rated voltage vref2 of the second comparator 07 and less than the rated voltage vref3 of the third comparator 08, the first comparison signal OUT1 output by the first comparator 06 is a high level (1), the second comparison signal OUT2 output by the second comparator 07 is also a high level (0), and the third comparison signal output by the third comparator 08 is a low level (0).

[0114] After the above comparison signals pass through the logic circuit 03′, the logic circuit 03′ outputs all three comparison signals to obtain the output signal <1,1,0>, thereby changing the output mode corresponding to the target chip 01 to the output mode and output polarity corresponding to the output signal <1,0,0>. For example, the output mode corresponding to the output signal <1,1,0> is a switching output mode, and the output polarity is high level valid.

[0115] In some implementations, such as Figure 8b As shown, assuming that the voltage C1 input to the first control pin 011 is the rated voltage vref3 of the third comparator 08, since the rated voltages of the first comparator 06, the second comparator 07 and the third comparator 08 have the above-mentioned relationship, the first comparison signal OUT1 output by the first comparator 06 is a high level (1), the second comparison signal OUT2 output by the second comparator 07 is a low level (0), and the third comparison signal output by the third comparator 08 is also a high level (1).

[0116] After the above comparison signals pass through the logic circuit 03′, the logic circuit 03′ outputs all three comparison signals to obtain the output signal <1,1,1>, thereby changing the output mode corresponding to the target chip 01 to the output mode and output polarity corresponding to the output signal <1,1,1>. For example, the output mode corresponding to the output signal <1,1,1> is a switching output mode, and the output polarity is low level valid.

[0117] Through the above method, the comparator and logic circuit added inside the target chip can be used to control the output mode of the target chip. It can be understood that the implementation method of the present application only uses one control pin (i.e., the first control pin) to achieve the purpose of changing the output mode of the target chip. Figures 3 to 5As shown in the embodiment, the implementation of the present application can effectively improve the utilization rate of the target chip pins.

[0118] Figure 9 A block diagram of a SoC (System on Chip) provided according to some embodiments of the present application is shown. Figure 9 In FIG, similar components have the same reference numerals. In addition, the dashed boxes are optional features of more advanced SoCs. Figure 9 In the embodiment, SoC 900 includes: an interconnect unit 950 coupled to a processor 99; a system agent unit 970; a bus controller unit 980; an integrated memory controller unit 940; a set or one or more coprocessors 920, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 930; and a direct memory access (DMA) unit 960. In one embodiment, the coprocessors 920 include specialized processors such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor.

[0119] According to the method and device for controlling chip output type provided in the present application, the output type of the target chip can be changed during the power-on process of the target chip, thereby expanding the applicable scenarios of the target chip.

[0120] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0121] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0122] Program code can be implemented with a high-level programming language or an object-oriented programming language to communicate with the processing system. Where necessary, program code can also be implemented in assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0123] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0124] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0125] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0126] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "including a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0127] Each method implementation method of the present application can be implemented in software, magnetic components, firmware, etc.

[0128] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0129] Program code can be implemented with a high-level programming language or an object-oriented programming language to communicate with the processing system. Where necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0130] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a computer-readable storage medium, which represent various logic within a processor and, when read by a machine, cause the machine to fabricate logic for performing the techniques described herein. These representations, known as "IP cores," may be stored on a tangible computer-readable storage medium and supplied to multiple customers or manufacturing facilities to be loaded into fabrication machines that actually manufacture the logic or processor.

[0131] In some cases, an instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can transform (e.g., using static binary transformation, dynamic binary transformation including dynamic compilation), deform, simulate, or otherwise convert instructions into one or more other instructions to be processed by the IP core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on-processor, off-processor, or partially on-processor and partially off-processor.

[0132] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A chip control circuit, characterized in that: Including control chip and switch module; The control chip includes a first control pin, a first voltage control unit and a first latch unit; The switch module includes an output mode control switch, wherein the output mode control switch is connected to the first control pin; In response to the output mode controlling the switch to be closed, the first voltage control unit controls the first control pin to output a first level to the first latch unit, where the first level corresponds to the switch output mode; In response to the output mode control switch being turned on, the first voltage control unit controls the first control pin to output a second level to the first latch unit, where the second level corresponds to a direct output mode; The switch output mode means that after the control chip detects a touch operation, the output is a high level, and the high level is latched to continuously output a high level. After the touch operation is detected again, the output is a low level. The direct output mode means that after the control chip detects a touch operation, the output is a high level, and when the control chip cannot detect a touch operation, the output is a low level.

2. The chip control circuit according to claim 1, characterized in that: The control chip further includes a first electrode, a second electrode, and an output pin, wherein: The first end of the first control pin is connected to the first electrode through the output mode control switch, and the second end of the first control pin is connected to the first end of the first latch unit, for outputting a level signal to the first latch unit; The first end of the first voltage control unit is connected to the second end of the first control pin, the second end of the first voltage control unit is connected to the second electrode, the first voltage control unit is used to control the level signal according to the opening and closing of the output mode control switch, and, Corresponding to the output mode control switch being turned off, the first voltage control unit controls the level corresponding to the level signal to be the first level; Corresponding to the output mode control switch being turned on, the first voltage control unit controls the level corresponding to the level signal to be the second level.

3. The chip control circuit according to claim 1, wherein: The first voltage control unit is further configured to receive a first pulse signal during the power-on process of the control chip, where the first pulse signal is configured to control the operation of the first voltage control unit.

4. The chip control circuit according to claim 3, characterized in that: The first voltage control unit includes a first MOS tube and a first resistor, wherein: The first end of the first resistor serves as the first end of the first voltage control unit, the second end of the first resistor is connected to the first end of the first MOS transistor, the second end of the first MOS transistor serves as the second end of the first voltage control unit, and the third end of the first MOS transistor is used to receive the first pulse signal.

5. The chip control circuit according to claim 1, characterized in that: The control chip further includes a second control pin, a second voltage control unit and a second latch unit. The switch module includes a polarity control switch, wherein the output mode control switch is connected to the second control pin, and the polarity control switch is connected to the second control pin; In response to the polarity control switch being closed, the second voltage control unit controls the second control pin to output a third level to the second latch unit, where the third level corresponds to an output high level being valid; Corresponding to the polarity control switch being turned on, the second voltage control unit controls the second control pin to output a fourth level to the second latch unit, where the fourth level corresponds to an active low level output.

6. A method for controlling chip output mode, characterized in that: Applied to chip control circuit, where The chip control circuit includes a control chip and a switch module. The control chip includes a first control pin, a first voltage control unit and a first latch unit; The switch module includes an output mode control switch, wherein the output mode control switch is connected to the first control pin; The method comprises: In response to the output mode controlling the switch to be closed, the first voltage control unit controls the first control pin to output a first level to the first latch unit, wherein the first level corresponds to the switch output mode; In response to the output mode control switch being turned on, the first voltage control unit controls the first control pin to output a second level to the first latch unit, wherein the second level corresponds to a direct output mode; The switch output mode means that after the control chip detects a touch operation, the output is a high level, and the high level is latched to continuously output a high level. After the touch operation is detected again, the output is a low level. The direct output mode means that after the control chip detects a touch operation, the output is a high level, and when the control chip cannot detect a touch operation, the output is a low level.

7. The method according to claim 6, characterized in that The control chip further includes a second control pin, a second voltage control unit and a second latch unit. The switch module includes a polarity control switch, wherein the output mode control switch is connected to the second control pin, and the polarity control switch is connected to the second control pin; In response to the polarity control switch being closed, the second voltage control unit controls the second control pin to output a third level to the second latch unit, where the third level corresponds to an output high level; Corresponding to the polarity control switch being turned on, the second voltage control unit controls the second control pin to output a fourth level to the second latch unit, where the fourth level corresponds to an output low level.

8. A chip control circuit, characterized in that: Comprising a control chip, the control chip comprising a first control pin and a signal selection circuit; The first control pin is used to receive and send a control signal of a preset type to the signal selection circuit, The signal selection circuit is used to control the output mode of the control chip according to the preset type of control signal, wherein, Corresponding to a first preset type of control signal, the signal selection circuit outputs a first type of signal to the control chip, the first type of signal corresponding to a direct output mode and being high level valid; Corresponding to a second preset type of control signal, the signal selection circuit outputs a second type of signal to the control chip, the second type of signal corresponding to a direct output mode and being active at a low level; Corresponding to a third preset type of control signal, the signal selection circuit outputs a third type of signal to the control chip, the third type of signal corresponding to a switch output mode and being high level valid; Corresponding to a fourth preset type of control signal, the signal selection circuit outputs a fourth type of signal to the control chip, the fourth type of signal corresponding to the switch output mode and being effective at a low level; The switch output mode means that after the control chip detects a touch operation, the output is a high level, and the high level is latched to continuously output a high level. After the touch operation is detected again, the output is a low level. The direct output mode means that after the control chip detects a touch operation, the output is a high level, and when the control chip cannot detect a touch operation, the output is a low level.

9. The chip control circuit according to claim 8, characterized in that: The second preset type of control signal includes a pulse signal with one rising edge, the third preset type of control signal includes a pulse signal with two rising edges, and the fourth preset type of control signal includes a pulse signal with three rising edges.

10. The chip control circuit according to claim 8, characterized in that: The signal selection circuit includes a master trigger, a slave trigger, and a first logic circuit, wherein the master trigger is used to receive a preset type of control signal input from the first control pin, and the preset type of control signal is further used to control the master trigger to output a first output signal from a first output pin to the first logic circuit, and to output a second output signal different from the first output signal from a second output pin to the first logic circuit, and The preset type of control signal is further used to control the master trigger to input a second control signal to the slave trigger through the first output pin, and the second control signal is used to control the slave trigger to output a third output signal to the third input pin of the first logic circuit and to output a fourth output signal different from the third output signal to the fourth input pin of the first logic circuit. The preset type of control signal is also used to control the first logic circuit to select at least one output signal from the received first output signal and second output signal, and to select at least one output signal from the received third output signal and fourth output signal, and to output the at least two selected output signals to control the output mode of the chip to be a preset output mode corresponding to the at least two output signals.

11. The chip control circuit according to claim 10, characterized in that: The master trigger includes a rising edge trigger, and the slave trigger includes a rising edge trigger.

12. The chip control circuit according to claim 10, characterized in that: The control signal of the first preset type includes a level signal whose voltage is lower than the first preset voltage, the control signal of the second preset type includes a level signal whose voltage is greater than the first preset voltage and less than the second preset voltage, the control signal of the third preset type includes a level signal whose voltage is greater than the second preset voltage and less than the third preset voltage, and the control signal of the fourth preset type includes a level signal whose voltage is greater than the third preset voltage.

13. The chip control circuit according to claim 8, wherein: The signal selection circuit includes a second logic circuit, a first comparator, a second comparator, and a third comparator, wherein a first preset voltage of the first comparator is less than a second preset voltage of the second comparator, and the second preset voltage is less than a third preset voltage of the third comparator, and The first control pin is used to output a preset type of control signal to the first comparator, the second comparator, and the third comparator, wherein the preset type of control signal is used to control the first comparator to generate a first comparison signal, and to control the second comparator to generate a second comparison signal, and further to control the third comparator to generate a third comparison signal. The first logic circuit generates an output signal according to the first comparison signal, the second comparison signal, and the third comparison signal, and outputs the output signal to control the output mode of the chip to be a preset output mode corresponding to the output signal.

14. A method for controlling chip output mode, characterized in that: An application chip control circuit includes a control chip, and the control chip includes a first control pin and a signal selection circuit; The first control pin is used to receive and send a control signal of a preset type to the signal selection circuit, The signal selection circuit is used to control the output mode of the control chip according to the preset type of control signal, The method comprises: Corresponding to a first preset type of control signal, a first type of signal is output to the control chip through the signal selection circuit, wherein the first type of signal corresponds to a direct output mode and is high level valid; Corresponding to a second preset type of control signal, a second type of signal is output to the control chip through the signal selection circuit, wherein the second type of signal corresponds to a direct output mode and is active at a low level; Corresponding to a third preset type of control signal, the third type of signal is output to the control chip through the signal selection circuit, wherein the third type of signal corresponds to a switch output mode and is high level valid; Corresponding to a fourth preset type of control signal, a fourth type of signal is output to the control chip through the signal selection circuit, wherein the fourth type of signal corresponds to a switch output mode and is active low; The switch output mode means that after the control chip detects a touch operation, the output is a high level, and the high level is latched to continuously output a high level. After the touch operation is detected again, the output is a low level. The direct output mode means that after the control chip detects a touch operation, the output is a high level, and when the control chip cannot detect a touch operation, the output is a low level.

15. The method according to claim 14, characterized in that The second preset type of control signal includes a pulse signal with one rising edge, the third preset type of control signal includes a pulse signal with two rising edges, and the fourth preset type of control signal includes a pulse signal with three rising edges.

16. The method according to claim 15, characterized in that The signal selection circuit includes a master trigger, a slave trigger, and a first logic circuit, wherein the master trigger is used to receive a preset type of control signal input from the first control pin, and the preset type of control signal is further used to control the master trigger to output a first output signal from a first output pin to the first logic circuit, and to output a second output signal different from the first output signal from a second output pin to the first logic circuit, and The preset type of control signal is further used to control the master trigger to input a second control signal to the slave trigger through the first output pin, and the second control signal is used to control the slave trigger to output a third output signal to the third input pin of the first logic circuit and to output a fourth output signal different from the third output signal to the fourth input pin of the first logic circuit. The preset type of control signal is also used to control the first logic circuit to select at least one output signal from the received first output signal and second output signal, and to select at least one output signal from the received third output signal and fourth output signal, and to output the at least two selected output signals to control the output mode of the chip to be a preset output mode corresponding to the at least two output signals.

17. The method according to claim 16, characterized in that The master trigger includes a rising edge trigger, and the slave trigger includes a rising edge trigger.

18. The method according to claim 14, characterized in that The control signal of the first preset type includes a level signal whose voltage is lower than the first preset voltage, the control signal of the second preset type includes a level signal whose voltage is greater than the first preset voltage and less than the second preset voltage, the control signal of the third preset type includes a level signal whose voltage is greater than the second preset voltage and less than the third preset voltage, and the control signal of the fourth preset type includes a level signal whose voltage is greater than the third preset voltage.

19. The method according to claim 18, characterized in that The signal selection circuit includes a second logic circuit, a first comparator, a second comparator, and a third comparator, wherein a first preset voltage of the first comparator is less than a second preset voltage of the second comparator, and the second preset voltage is less than a third preset voltage of the third comparator, and The first control pin is used to output a preset type of control signal to the first comparator, the second comparator, and the third comparator, wherein the preset type of control signal is used to control the first comparator to generate a first comparison signal, and to control the second comparator to generate a second comparison signal, and further to control the third comparator to generate a third comparison signal. The second logic circuit generates an output signal according to the first comparison signal, the second comparison signal, and the third comparison signal, and outputs the output signal to control the output mode of the chip to be a preset output mode corresponding to the output signal.

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