A cloud-native hardware logic simulation FPGA acceleration method and system

Abstract

The present invention proposes a cloud-native hardware logic simulation FPGA acceleration method and system, including: building a hardware logic simulation acceleration platform based on a loosely coupled FPGA cluster, dividing each FPGA node into a static logic area for carrying functions provided by the acceleration platform and multiple dynamic logic areas with the same logic resource scale for carrying target logic circuits to be simulated; a matching customized tool can obtain the hardware design to be simulated of each tenant of the current acceleration platform and insert the simulation control circuit; the matching tool can generate an FPGA configuration file that can be deployed in several dynamic logic areas; simulation software running on a tightly coupled integrated processor in the FPGA node controls the operation of the hardware design on the FPGA node, each FPGA node dynamic logic area generates simulation data, and the status data inside the FPGA node circuit is returned to the tenant as a simulation result; at the same time, simulation data is interacted with other FPGA nodes through the static logic area of ​​each FPGA node to support large-scale logic circuit simulation operation.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, simulation and debugging, and in particular to a cloud-native hardware logic simulation FPGA acceleration method and system. Background Art

[0002] Various processor chips are facing the challenges of growing logic design scale and time-to-market compression. During the design and debugging phase of processor chips, software simulators are needed to simulate and debug the hardware logic design of processor chips. Although software logic simulation can provide observability of all logic signals of processor design, the simulation speed is slow. In particular, as application scenarios continue to change, the design scale of single processing cores and complete processor chips has increased significantly, resulting in increased complexity in processor chip design and increasing the difficulty of verifying and debugging the logic functions of processor designs.

[0003] Another method to verify and debug the processor logic design is to use the hardware programmable device FPGA to perform hardware prototype verification on the processor design. During the prototype verification process, the processor hardware design needs to be converted into a programmable bitstream configuration file through the FPGA tool; after programming and configuration, the processor under test can be run on the FPGA. Since it runs in a real hardware environment, FPGA prototype verification can increase the speed of verifying the correctness of the processor design function. However, since the logic resources inside the FPGA chip are often extremely limited, it is impossible to fully record all the logic signal states of the design under test, and it is impossible to provide a friendly debugging environment like a software simulator.

[0004] In order to balance the performance of logic simulation and signal observability, logic simulation based on FPGA acceleration is a feasible solution. FPGA-accelerated logic simulation inserts a specific simulation control circuit into the processor design under test, thereby using real hardware to obtain better simulation performance than software simulators, and using customized software tools to achieve cycle-accurate and bit-accurate observation of all logic signals of the design under test. However, the current dedicated logic simulation FPGA acceleration platform and supporting tools (such as Synopsys ZeBu and AldecHES built on FPGA) are often expensive and complicated to use. The chip design team needs to divide the use threshold, which reduces the agility of chip design.

[0005] On the other hand, as the deployment scale of FPGA devices in data centers continues to grow, it has become an important trend to use FPGA as a type of public cloud computing resource that can be shared and used by tenants to rent and deploy customized hardware accelerator designs on demand. Amazon AWS first launched rentable FPGA computing instances in 2016; domestic Internet leaders such as Alibaba Cloud, Tencent Cloud, and Huawei Cloud have also followed suit and launched FPGA public cloud infrastructure and rental services. Unlike local FPGA development methods, users cannot physically connect to cloud FPGA boards, making traditional FPGA hardware logic debugging methods unusable. There is an urgent need to provide a cloud-native FPGA hardware logic debugging method.

[0006] Although the existing dedicated logic simulation platform based on FPGA acceleration can provide a logic simulation rate of 1-10MHz for register transfer level (RTL) code or netlist, it still has the following problems:

[0007] 1) In existing FPGA simulation acceleration and prototype verification platforms, large-scale FPGA chips or boards use tightly coupled interconnection, that is, using the ordinary I / O pins of the FPGA chip for pin-to-pin data transmission through time-division multiplexing. However, as the scale of the design under test continues to grow, the tightly coupled platform is limited by the fixed topology structure and cannot flexibly expand resources, thereby limiting the scale of the design under test that can support simulation acceleration or prototype verification. In particular, as the design scale continues to grow, the limited-scale simulation acceleration platform cannot meet the verification requirements, resulting in reduced verification quality.

[0008] 2) Existing FPGA simulation acceleration platforms and tools require high purchase costs, which makes it impossible for chip design teams to purchase sufficient simulation acceleration computing power to meet team needs. On the one hand, limited simulation acceleration resources will make it impossible for chip design teams to conduct large-scale verification of target designs, reducing verification efficiency.

[0009] Problems faced by existing FPGA cloud hardware debugging methods:

[0010] 1) Although FPGA cloud has been commercialized on a large scale, the FPGA hardware logic debugging method on the cloud still relies on the traditional Embedded Logic Analyzer (ELA) method, and provides debugging control to users through a virtual debugging interface based on the network or PCIe interface (such as Xilinx XVC, etc.). However, this method is similar to the traditional FPGA debugging method. Due to the limited logic resource capacity inside the FPGA chip, it cannot fully record all the logic signal states of the tested design. At the same time, ELA's state monitoring of logic signals needs to be controlled by dedicated logic trigger conditions, and cannot provide cycle-accurate hardware logic operation state monitoring.

[0011] 2) Existing cloud FPGA computing resources are often provided to tenants in an exclusive manner. In the future, there may be a model where multiple tenants share FPGAs. However, the existing cloud FPGA debugging mechanism requires tenants to exclusively use ELA and related FPGA on-chip debugging resources and interfaces, which cannot support the hardware logic debugging needs of multiple tenants. Summary of the invention

[0012] Specifically, the present invention proposes a cloud-native hardware logic simulation FPGA acceleration method, which includes:

[0013] Step 1: Build a hardware logic simulation acceleration platform based on a loosely coupled FPGA cluster. The acceleration platform includes a top-level switch in a data center and multiple loosely coupled FPGA cluster racks. Each loosely coupled FPGA cluster rack includes a switch and multiple FPGA nodes connected to the switch. Each switch is connected to the top-level switch in the data center.

[0014] Step 2: Divide each FPGA node into a static logic area for carrying functions provided by the acceleration platform and multiple dynamic logic areas with the same logic resource scale for carrying user logic, obtain the hardware design to be simulated for each tenant of the current acceleration platform, insert the simulation control circuit, perform FPGA logic synthesis and layout and routing operations on the hardware design inserted into the control circuit, generate a configuration file for the FPGA node, and configure the dynamic logic area of ​​the FPGA node;

[0015] Step 3: The simulation software running on the integrated processor in the FPGA node controls the operation of the hardware design on the FPGA node. Each dynamic logic area of ​​the FPGA node generates simulation data, and interacts with other FPGA nodes through its static logic area for simulation data. Finally, the status data inside the FPGA node circuit is sent back to the tenant as a simulation result through the user operation interface.

[0016] The cloud-native hardware logic simulation FPGA acceleration method, wherein in step 2, when inserting the simulation control circuit, each clock-driven register and memory inside the logic to be simulated is identified, and the scan chain logic is inserted in sequence according to the identification order, and the position of each register and memory in the scan chain is recorded; according to the logic synthesis and layout and wiring method of the FPGA, a configuration bitstream file that can be deployed on the cloud FPGA is generated; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, it will read out the status values ​​of each register and memory from the scan chain in sequence through the addressable control register, and determine the status values ​​of each register and memory according to the acquired position information of each register and memory in the scan chain.

[0017] The cloud-native hardware logic simulation FPGA acceleration method, wherein when the simulation control circuit is inserted in step 2, each clock driving register inside the logic to be simulated is identified, and a netlist name list of all register circuits is generated; according to the acquired register netlist name, a constraint file for marking DONT_TOUCH for all registers is generated to ensure that the marked register name will not be modified in the FPGA logic synthesis stage; according to the logic synthesis and layout and routing method of the FPGA, a configuration bitstream file that can be deployed on the cloud FPGA is generated; in the process of generating the bitstream, a logiclocation file is synchronously generated to mark the location information of each register and memory on the FPGA chip; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, the FPGAreadback function is used to read the status of each register and memory inside the current FPGA, and combined with the logiclocation file, the determined output value of each register and memory in the user logic design is restored.

[0018] The cloud-native hardware logic simulation FPGA acceleration method, wherein the way in which the simulation signal in step 3 interacts between FPGA nodes includes a hardware communication protocol stack located in a static area to provide reliability assurance for cross-chip communication of a loosely coupled FPGA cluster; the protocol stack is used for the receiving end FPGA to generate an ACK response after receiving the data fragment, to notify the sending end FPGA of the received fragment number, indicating that all data packets less than or equal to the current fragment number have been received; before receiving the response, the sending end FPGA needs to maintain all sent data fragment windows; if the response is received within the specified time, the corresponding data packet can be released; otherwise, all data fragments in the fragment window are resent.

[0019] The present invention also proposes a cloud-native hardware logic simulation FPGA acceleration system, which includes:

[0020] An acceleration platform construction module is used to build a hardware logic simulation acceleration platform based on a loosely coupled FPGA cluster. The acceleration platform includes a top-level switch in a data center and multiple loosely coupled FPGA cluster racks. Each loosely coupled FPGA cluster rack includes a switch and multiple FPGA nodes connected to the switch. Each switch is connected to the top-level switch in the data center.

[0021] The FPGA configuration module is used to divide each FPGA node into a static logic area for carrying the functions provided by the acceleration platform and multiple dynamic logic areas with the same logic resource scale for carrying user logic. In order to cooperate with the above-mentioned FPGA logic area division method, a customized tool chain is used to obtain the hardware design to be simulated for each tenant of the current acceleration platform, and a simulation control circuit is inserted. The hardware design inserted into the control circuit is subjected to FPGA logic synthesis and layout and routing operations, and a configuration file of the FPGA node is generated to configure the dynamic logic area of ​​the FPGA node;

[0022] The FPGA simulation module is used to run the simulation software on the tightly coupled integrated processor in the FPGA node and control the operation of the hardware design on the FPGA node. Each dynamic logic area of ​​the FPGA node generates simulation data and interacts with other FPGA nodes through its static logic area to perform simulation data to achieve large-scale logic circuit simulation. Finally, the status data of the relevant circuits in the FPGA node are sent back to the tenant as simulation results.

[0023] The cloud-native hardware logic simulation FPGA acceleration system, wherein the FPGA configuration module, when inserted into the simulation control circuit, identifies each clock-driven register and memory inside the logic to be simulated, and inserts them into the scan chain logic in sequence according to the identification order, and records the position of each register and memory in the scan chain; generates a configuration bitstream file that can be deployed on the cloud FPGA according to the logic synthesis and layout and wiring method of the FPGA; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, it will read out the status values ​​of each register and memory from the scan chain in sequence through the addressable control register, and determine the status values ​​of each register and memory according to the acquired position information of each register and memory in the scan chain.

[0024] The cloud-native hardware logic simulation FPGA acceleration method, wherein the FPGA configuration module, when inserted into the simulation control circuit, identifies each clock driving register inside the logic to be simulated, and generates a netlist name list of all register circuits; generates a constraint file for marking DONT_TOUCH for all registers according to the acquired register netlist name, to ensure that the marked register name will not be modified during the FPGA logic synthesis stage; generates a configuration bitstream file that can be deployed on the cloud FPGA according to the FPGA logic synthesis and layout and routing method; in the process of generating the bitstream, synchronously generates a logic location file for marking the location information of each register and memory on the FPGA chip; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, the FPGA readback function is used to read out the status of each register and memory inside the current FPGA, and combined with the logic location file, restores the determined output value of each register and memory in the user logic design.

[0025] The cloud-native hardware logic simulation FPGA acceleration method, wherein the way in which the simulation signal in the FPGA simulation module interacts between FPGA nodes, includes a hardware communication protocol stack located in a static area, which provides reliability guarantee for cross-chip communication of a loosely coupled FPGA cluster to support larger-scale logic circuit simulation acceleration; the protocol stack is used for the receiving end FPGA to generate an ACK response after receiving the data fragment, to notify the sending end FPGA of the received fragment number, indicating that all data packets less than or equal to the current fragment number have been received; before receiving the response, the sending end FPGA needs to maintain all sent data fragment windows; if the response is received within the specified time, the corresponding data packet can be released; otherwise, all data fragments in the fragment window are resent.

[0026] The present invention also proposes a storage medium for storing a program for executing any one of the cloud-native hardware logic simulation FPGA acceleration methods.

[0027] The present invention also proposes a client for use in any of the cloud-native hardware logic simulation FPGA acceleration systems.

[0028] It can be seen from the above scheme that the advantages of the present invention are:

[0029] The present invention provides loosely coupled and scalable FPGA clusters to users in the form of computing power infrastructure services (Infrastructure-as-a-Service), and abstracts FPGA simulation acceleration tools into a series of software services, allowing users to quickly customize the hardware debugging process based on simulation acceleration according to the target design situation, reducing the deployment cost and usage threshold of chip design users, and improving simulation verification performance based on large-scale cloud computing power. At the same time, the relevant methods of the present invention can be applied to cloud FPGA hardware logic debugging in multi-tenant scenarios, reducing the dependence of existing cloud FPGA debugging interfaces on FPGA on-chip ELA resources, so that multiple tenants can concurrently observe all logic signal states of their respective target logic designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the loosely coupled FPGA cluster structure of the present invention;

[0031] Figure 2 This is the schematic diagram of the logic circuit after splitting;

[0032] Figure 3 It is a schematic diagram of the simulation process of the present invention;

[0033] Figure 4 It is a diagram illustrating a specific embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention can provide cycle-accurate and bit-accurate full-signal-level hardware debugging means for processor chip logic design based on FPGA (Field Programmable Gate Array) acceleration, which not only avoids the time overhead caused by using logic simulation software tools, but also solves the problem of limited number of adjustable signals in FPGA prototype verification of processor chip design. At the same time, the present invention can also provide a hardware logic signal-level debugging method for FPGA public cloud, enriching the technical means of FPGA public cloud for application acceleration debugging.

[0035] The present invention aims to improve the hardware debugging efficiency of large-scale hardware logic design, and proposes a cloud-native logic simulation FPGA acceleration platform construction method, so that the operating status of the target hardware circuit can be monitored at high speed with cycle accuracy and bit accuracy, and can provide users with elastic and scalable simulation acceleration computing power and software tool services, thereby lowering the threshold for using logic simulation acceleration tools.

[0036] In addition, the above method can also eliminate tenants' reliance on ELA when debugging hardware logic in existing commercial public FPGA cloud services, thereby providing a new method for cloud FPGA hardware logic debugging and providing debugging means for future scenarios where multiple tenants share and use cloud FPGA. To this end, the present invention includes the following key technical points:

[0037] Key point 1: The cloud-based infrastructure service platform for hardware logic simulation acceleration built on loosely coupled FPGA clusters breaks through the scalability limitations of traditional dedicated FPGA simulation acceleration platforms through standard network interconnection;

[0038] Key point 2: A cloud-native logic simulation FPGA acceleration tool packaging method, including 1) customized orchestration of tool usage based on continuous integration technology, and 2) decoupling the tool process links through container technology, disassembling the single FPGA simulation acceleration tool into a series of generalized functions.

[0039] Key point 3: A hardware logic debugging method for FPGA public cloud environment in multi-tenant scenarios, which can support multiple tenants to perform FPGA hardware logic debugging concurrently.

[0040] In order to make the above features and effects of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

[0041] 1. Hardware logic simulation acceleration cloud infrastructure based on loosely coupled FPGA cluster

[0042] A circuit board card built with an FPGA chip as the core is called an FPGA node. The cloud service provider pre-divides the logic area in the FPGA into a static area and a dynamic area. The static area is used to implement the functions provided by the cloud service provider and remains unchanged during the service; the dynamic area is used to carry user logic and can be reprogrammed according to user needs to implement different functions. The present invention proposes a loosely coupled FPGA cluster that is interconnected based on a standard Ethernet interface and existing data center network infrastructure, and FPGA resources can be flexibly added to the cluster as needed. To achieve hardware logic simulation acceleration based on a loosely coupled FPGA cluster. Figure 1 As shown, the present invention proposes the following technical contents:

[0043] 1) Static division and dynamic use of programmable logic areas within FPGA nodes: Based on partial reconfiguration technology, FPGA nodes are divided into static logic areas and several dynamic areas with the same logic resource scale. The design to be tested can occupy one to multiple dynamic areas. The static logic area supports the coordinated operation of dynamic areas within the same FPGA chip Die, within different FPGA chip Dies, and between different FPGA chips.

[0044] 2) Delay-insensitive cross-dynamic area hardware logic deployment: Figure 2As shown in the figure, a target hardware logic partitioning method based on delay-insensitive channel queues is used. This method divides the complete logic design to be simulated into several independent sub-modules that do not generate data dependencies by encapsulating the output of a certain register into a data packet and inserting it into a delay-insensitive channel queue. Different sub-modules can be deployed in different dynamic logic areas and exchange data through delay-insensitive channel queues under different clock drives. In a simulated target clock cycle, each module will write a valid register output data packet to the delay-insensitive output channel queue and read a valid data packet passed by other sub-modules from the delay-insensitive input channel queue.

[0045] For a submodule, when its corresponding delay-insensitive input channel is empty or the delay-insensitive output channel is full, the submodule will suspend simulation. At this time, in order to ensure that each register in the submodule can maintain the current logical state, the physical clock needs to be gated (Clock-Gating). The gating process uses the clock gating element on the FPGA to control the physical clock signal to no longer flip, so that each register stops updating the state, and the Q-end output value does not change with the D-end input value.

[0046] 3) Loosely coupled FPGA cluster cross-chip communication reliability guarantee: FPGA node-to-node communication based on loosely coupled Ethernet physical paths in the data center cannot guarantee the reliability of communication, and network packet loss is very likely to occur. However, the FPGA acceleration of hardware logic simulation has extremely strict requirements on data transmission and does not allow data loss. Therefore, the present invention proposes a node-to-node communication reliability guarantee mechanism for a loosely coupled FPGA cluster based on a streamlined TCP protocol. By designing a customized hardware protocol stack that supports a data retransmission mechanism, it ensures zero packet loss network packet transmission and ensures platform robustness.

[0047] The TCP protocol uses data fragment numbers and the ACK response mechanism specified in the TCP protocol to ensure reliability. After receiving the data fragment, the receiver will generate an ACK response to notify the sender of the received fragment number (indicating that all data packets less than or equal to the current fragment number have been received). Before receiving the response, the data sender needs to maintain the window of all sent data fragments. If the response is received within the specified time, the corresponding data packet can be released (i.e., the window slides); otherwise, all data fragments in the fragment window are resent.

[0048] 2. Cloud-native logic simulation FPGA acceleration tool packaging method

[0049] In order to make full use of the characteristics of rich computing resources and elastic scalability in cloud computing environment, the present invention proposes the following technical improvements:

[0050] 1) Use continuous integration technology to decouple the workflow of FPGA-accelerated logic simulation tools into two stages: "target design mapping" and "simulation acceleration operation". Continuous integration tool languages ​​(such as YML scripts) can be used within each stage to customize the operating environment, input and output files, and file saving methods of each step;

[0051] 2) Further decouple the steps within a certain stage, and use container technology to containerize its operating environment (including program libraries, tool sets, etc.) to form a series of generalized functional functions that can be directly deployed and run;

[0052] 3) Based on cloud infrastructure resources and container resource scheduling, it can support multiple simulation instances to run concurrently on the cloud platform, improving the concurrent service capabilities of hardware logic simulation FPGA acceleration.

[0053] 3. FPGA public cloud environment hardware logic debugging method for multi-tenant scenarios

[0054] Applying FPGA simulation acceleration to FPGA public cloud hardware logic debugging in multi-tenant scenarios can be divided into two stages: "target design mapping" and "simulation acceleration operation". In the "target design mapping" stage, a simulation control circuit is inserted into the user's hardware design to be debugged. This circuit is used to receive commands from the simulation acceleration control software, control the running status of the hardware design, and access the status data inside the hardware design. Subsequently, the hardware design with the control circuit inserted is subjected to FPGA logic synthesis, layout and routing, and other process operations are generated to generate a bitstream file that can be configured on the FPGA.

[0055] In the "simulation acceleration operation" stage, the processor integrated in the FPGA runs the simulation acceleration control software to control the operation process of the hardware design on the FPGA, and allows users to pause and save the internal state data of the circuit at any time through the user operation interface. By storing the state data in the form of a file, it can be loaded in the simulation software to reproduce the circuit state information from the time of saving, and finally generate and save it as a user-observable waveform file, which is provided to users for logical behavior observation, thereby supporting users to perform hardware logic debugging on the FPGA public cloud.

[0056] There are two specific methods for obtaining and saving the status of hardware logic circuits:

[0057] 1) Implementation method 1: Logic state monitoring based on scan chain insertion:

[0058] Step 1: In the simulation control circuit insertion phase of the target design mapping, identify each clock-driven register (Register) and memory (Memory) inside the logic to be simulated, and insert them into the scan chain logic in the order of identification, and record the position of each register and memory in the scan chain.

[0059] Step 2: Generate a configuration bitstream file that can be deployed on the cloud FPGA according to the logic synthesis and layout and routing methods of the existing FPGA public cloud.

[0060] Step 3: During the simulation acceleration operation phase, after pausing the simulation circuit, the simulation acceleration control software will read out the status values ​​of each register and memory from the scan chain in sequence through the addressable control register, and determine the status values ​​of each register and memory according to the acquired position information of each register and memory in the scan chain.

[0061] 2) Implementation method 2: Logic state monitoring based on FPGA readback function

[0062] Step 1: During the simulation control circuit insertion phase of the target design mapping, identify each clock driver register inside the logic to be simulated and generate a netlist name list of all register circuits.

[0063] Step 2: Generate a constraint file for all registers marked with DONT_TOUCH according to the acquired register netlist name to ensure that the marked register name will not be modified during the FPGA logic synthesis stage.

[0064] Step 3: Generate a configuration bitstream file that can be deployed on the cloud FPGA according to the logic synthesis and layout and routing methods of the existing FPGA public cloud. In the process of generating the bitstream, a logiclocation (ll) file is generated synchronously to mark the location information of each register and memory on the FPGA chip.

[0065] Step 4: During the simulation acceleration operation phase, after the simulation acceleration control software pauses the simulation circuit, it uses the FPGAreadback function to read out the status of each register and memory inside the current FPGA, and combines the ll file extracted in step 3 to restore the determined output values ​​of each register and memory in the user logic design.

[0066] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0067] The present invention also proposes a cloud-native hardware logic simulation FPGA acceleration system, which includes:

[0068] An acceleration platform construction module is used to build a hardware logic simulation acceleration platform based on a loosely coupled FPGA cluster. The acceleration platform includes a top-level switch in a data center and multiple loosely coupled FPGA cluster racks. Each loosely coupled FPGA cluster rack includes a switch and multiple FPGA nodes connected to the switch. Each switch is connected to the top-level switch in the data center.

[0069] The FPGA configuration module is used to divide each FPGA node into a static logic area for carrying the functions provided by the acceleration platform and multiple dynamic logic areas with the same logic resource scale for carrying user logic. In order to cooperate with the above-mentioned FPGA logic area division method, a customized tool chain is used to obtain the hardware design to be simulated for each tenant of the current acceleration platform, and a simulation control circuit is inserted. The hardware design inserted into the control circuit is subjected to FPGA logic synthesis and layout and routing operations, and a configuration file of the FPGA node is generated to configure the dynamic logic area of ​​the FPGA node;

[0070] The FPGA simulation module is used to run the simulation software on the tightly coupled integrated processor in the FPGA node and control the operation of the hardware design on the FPGA node. Each dynamic logic area of ​​the FPGA node generates simulation data and interacts with other FPGA nodes through its static logic area to perform simulation data to achieve large-scale logic circuit simulation. Finally, the status data of the relevant circuits in the FPGA node are sent back to the tenant as simulation results.

[0071] The cloud-native hardware logic simulation FPGA acceleration system, wherein the FPGA configuration module, when inserted into the simulation control circuit, identifies each clock-driven register and memory inside the logic to be simulated, and inserts them into the scan chain logic in sequence according to the identification order, and records the position of each register and memory in the scan chain; generates a configuration bitstream file that can be deployed on the cloud FPGA according to the logic synthesis and layout and wiring method of the FPGA; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, it will read out the status values ​​of each register and memory from the scan chain in sequence through the addressable control register, and determine the status values ​​of each register and memory according to the acquired position information of each register and memory in the scan chain.

[0072] The cloud-native hardware logic simulation FPGA acceleration method, wherein the FPGA configuration module, when inserted into the simulation control circuit, identifies each clock driving register inside the logic to be simulated, and generates a netlist name list of all register circuits; generates a constraint file for marking DONT_TOUCH for all registers according to the acquired register netlist name, to ensure that the marked register name will not be modified during the FPGA logic synthesis stage; generates a configuration bitstream file that can be deployed on the cloud FPGA according to the FPGA logic synthesis and layout and routing method; in the process of generating the bitstream, synchronously generates a logic location file for marking the location information of each register and memory on the FPGA chip; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, the FPGA readback function is used to read out the status of each register and memory inside the current FPGA, and combined with the logic location file, restores the determined output value of each register and memory in the user logic design.

[0073] The cloud-native hardware logic simulation FPGA acceleration method, wherein the way in which the simulation signal in the FPGA simulation module interacts between FPGA nodes, includes a hardware communication protocol stack located in a static area, which provides reliability guarantee for cross-chip communication of a loosely coupled FPGA cluster to support larger-scale logic circuit simulation acceleration; the protocol stack is used for the receiving end FPGA to generate an ACK response after receiving the data fragment, to notify the sending end FPGA of the received fragment number, indicating that all data packets less than or equal to the current fragment number have been received; before receiving the response, the sending end FPGA needs to maintain all sent data fragment windows; if the response is received within the specified time, the corresponding data packet can be released; otherwise, all data fragments in the fragment window are resent.

[0074] The present invention also proposes a storage medium for storing a program for executing any one of the cloud-native hardware logic simulation FPGA acceleration methods.

[0075] The present invention also proposes a client for use in any of the cloud-native hardware logic simulation FPGA acceleration systems.

Claims

1. A cloud-native hardware logic simulation FPGA acceleration method, characterized in that: include: Step 1: Build a hardware logic simulation acceleration platform based on a loosely coupled FPGA cluster. The acceleration platform includes a top-level switch in a data center and multiple loosely coupled FPGA cluster racks. Each loosely coupled FPGA cluster rack includes a switch and multiple FPGA nodes connected to the switch. Each switch is connected to the top-level switch in the data center. Step 2: Divide each FPGA node into a static logic area for carrying functions provided by the acceleration platform and multiple dynamic logic areas with the same logic resource scale for carrying user logic. To cooperate with the above FPGA logic area division method, obtain the hardware design to be simulated of each tenant of the current acceleration platform through a customized tool chain, insert the simulation control circuit, perform FPGA logic synthesis and layout and routing operations on the hardware design inserted into the control circuit, and generate a configuration file for the FPGA node to configure the dynamic logic area of ​​the FPGA node; Step 3: The simulation software running on the tightly coupled integrated processor in the FPGA node controls the operation of the hardware design on the FPGA node. Each dynamic logic area of ​​the FPGA node generates simulation data, and interacts with the simulation data of other FPGA nodes through its static logic area to achieve large-scale logic circuit simulation. Finally, the status data of the relevant circuits in the FPGA node are sent back to the tenant as the simulation result.

2. The cloud-native hardware logic simulation FPGA acceleration method according to claim 1, characterized in that: When inserting the simulation control circuit in step 2, each clock-driven register and memory inside the logic to be simulated is identified, and the scan chain logic is inserted in sequence according to the identification order, and the position of each register and memory in the scan chain is recorded; according to the logic synthesis and layout and wiring method of the FPGA, a configuration bitstream file that can be deployed on the cloud FPGA is generated; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, it will read out the status values ​​of each register and memory from the scan chain in sequence through the addressable control register, and determine the status values ​​of each register and memory according to the acquired position information of each register and memory in the scan chain.

3. The cloud-native hardware logic simulation FPGA acceleration method according to claim 1, characterized in that: When inserting the simulation control circuit in step 2, each clock driving register inside the logic to be simulated is identified, and a netlist name list of all register circuits is generated; according to the acquired register netlist name, a constraint file is generated for marking DONT_TOUCH for all registers to ensure that the marked register name will not be modified during the FPGA logic synthesis stage; according to the logic synthesis and layout and routing method of the FPGA, a configuration bitstream file that can be deployed on the cloud FPGA is generated; in the process of generating the bitstream, a logic location file is synchronously generated to mark the location information of each register and memory on the FPGA chip; in the simulation acceleration running stage, after the simulation acceleration control software pauses the simulation circuit, the FPGAreadback function is used to read out the status of each register and memory inside the current FPGA, and combined with the logic location file, the determined output value of each register and memory in the user logic design is restored.

4. The cloud-native hardware logic simulation FPGA acceleration method according to claim 1, characterized in that: The method of interaction of the simulation signal between FPGA nodes in step 3 includes a hardware communication protocol stack located in the static area, which provides reliability guarantee for cross-chip communication of loosely coupled FPGA clusters to support larger-scale logic circuit simulation acceleration; This protocol stack is used for the receiving end FPGA to generate an ACK response after receiving the data fragment, notifying the sending end FPGA of the received fragment number, indicating that all data packets less than or equal to the current fragment number have been received; before receiving the response, the sending end FPGA needs to maintain all the sent data fragment windows; If a response is received within the specified time, the corresponding data packet can be released; otherwise, all data fragments in the fragment window are resent.

5. A cloud-native hardware logic simulation FPGA acceleration system, characterized in that: include: An acceleration platform construction module is used to build a hardware logic simulation acceleration platform based on a loosely coupled FPGA cluster. The acceleration platform includes a top-level switch in a data center and multiple loosely coupled FPGA cluster racks. Each loosely coupled FPGA cluster rack includes a switch and multiple FPGA nodes connected to the switch. Each switch is connected to the top-level switch in the data center. The FPGA configuration module is used to divide each FPGA node into a static logic area for carrying the functions provided by the acceleration platform and multiple dynamic logic areas with the same logic resource scale for carrying user logic. In order to cooperate with the above-mentioned FPGA logic area division method, a customized tool chain is used to obtain the hardware design to be simulated for each tenant of the current acceleration platform, and a simulation control circuit is inserted. The hardware design inserted into the control circuit is subjected to FPGA logic synthesis and layout and routing operations, and a configuration file of the FPGA node is generated to configure the dynamic logic area of ​​the FPGA node; The FPGA simulation module is used to run the simulation software on the tightly coupled integrated processor in the FPGA node and control the operation of the hardware design on the FPGA node. Each dynamic logic area of ​​the FPGA node generates simulation data and interacts with other FPGA nodes through its static logic area to perform simulation data to achieve large-scale logic circuit simulation. Finally, the status data of the relevant circuits in the FPGA node are sent back to the tenant as simulation results.

6. The cloud-native hardware logic simulation FPGA acceleration system according to claim 5, characterized in that: When the FPGA configuration module is inserted into the simulation control circuit, it identifies each clock-driven register and memory inside the logic to be simulated, and inserts them into the scan chain logic in sequence according to the recognition order, and records the position of each register and memory in the scan chain; according to the logic synthesis and layout and routing method of the FPGA, it generates a configuration bitstream file that can be deployed on the cloud FPGA; in the simulation acceleration running stage, when the simulation acceleration control software pauses the simulation circuit, it will read out the status values ​​of each register and memory from the scan chain in sequence through the addressable control register, and determine the status values ​​of each register and memory based on the acquired position information of each register and memory in the scan chain.

7. The cloud-native hardware logic simulation FPGA acceleration system according to claim 5, characterized in that: When the FPGA configuration module is inserted into the simulation control circuit, it identifies each clock driving register inside the logic to be simulated and generates a netlist name list of all register circuits; according to the acquired register netlist name, it generates a constraint file that marks all registers with DONT_TOUCH to ensure that the marked register name will not be modified during the FPGA logic synthesis stage; according to the FPGA logic synthesis and layout and routing method, it generates a configuration bitstream file that can be deployed on the cloud FPGA; in the process of generating the bitstream, it synchronously generates a logic location file to mark the location information of each register and memory on the FPGA chip; in the simulation acceleration running stage, after the simulation acceleration control software pauses the simulation circuit, it uses the FPGA readback function to read out the status of each register and memory inside the current FPGA, and combines the logiclocation file to restore the determined output value of each register and memory in the user logic design.

8. The cloud-native hardware logic simulation FPGA acceleration system according to claim 5, characterized in that: The way in which the simulation signal interacts between FPGA nodes in the FPGA simulation module includes a hardware communication protocol stack located in the static area to provide reliability guarantee for cross-chip communication of loosely coupled FPGA clusters to support larger-scale logic circuit simulation acceleration; This protocol stack is used for the receiving end FPGA to generate an ACK response after receiving the data fragment, notifying the sending end FPGA of the received fragment number, indicating that all data packets less than or equal to the current fragment number have been received; before receiving the response, the sending end FPGA needs to maintain all the sent data fragment windows; If a response is received within the specified time, the corresponding data packet can be released; otherwise, all data fragments in the fragment window are resent.

9. A storage medium for storing a program for executing the cloud-native hardware logic simulation FPGA acceleration method as described in any one of claims 1 to 4.

10. A client for use in any one of the cloud-native hardware logic simulation FPGA acceleration systems of claims 5 to 8.

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