Edge wordline data retention improvement for memory devices utilizing pitch half circle drain side select gate technology

Abstract

The present invention provides a memory device and an operating method. The device includes memory cells connected to word lines, the word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and configured to maintain threshold voltages corresponding to data states. The strings are organized by rows, and a control device is coupled to the word lines and the strings and identifies the at least one edge word line. The control device programs the memory cells of the strings located in a specific row of the rows and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more data states during programming operations, compared to the memory cells of the strings not located in a specific row of the rows and not associated with the at least one edge word line.

Description

Technical Field

[0001] This application relates to the operation of non-volatile memory devices. Background Technology

[0002] This section provides background information related to the technology associated with this disclosure, and is not necessarily prior art.

[0003] Semicircular drain-side selected gate (“SC-SGD”) memory technology offers several advantages, including reduced die size. To manufacture SC-SGDs, an etching technique is used to cut memory holes, giving them a semicircular shape and dividing blocks or rows into strings. Depending on the process used to form the SC-SGD, some inefficiencies may occur. For example, cutting the memory holes removes at least some portion of the SC-SGD, such as a metal layer that would otherwise shield the electric field from the channel and / or charge trapping layer. Therefore, the SC-SGD can be affected by “adjacent” electric fields, leading to parasitic transistor leakage along the SC-SGD transistor. In some cases, this causes the sense amplifier to incorrectly determine that the SC-SGD is on, which can affect some sensing operations. Furthermore, due to etching variations, some dies may be cut into SGD layers while others may be cut into layers forming dummy word lines. Therefore, data retention problems may arise because the cuts are close to the data word lines. Thus, improved non-volatile memory devices and operating methods are needed. Summary of the Invention

[0004] This section provides a general overview of the disclosure and is not a full disclosure of its entire scope or all its features and advantages.

[0005] The purpose of this disclosure is to provide a memory device and a method for operating the memory device that solves and overcomes the above-mentioned disadvantages.

[0006] Therefore, one aspect of this disclosure is to provide a memory device comprising memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The strings are organized in rows, and a control means is coupled to the plurality of word lines and the strings. The control means is configured to identify the at least one edge word line. The control means programs the memory cells of the string located in a specific row of the row and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation, compared to the memory cells of the string not located in a specific row of the row and not associated with the at least one edge word line.

[0007] According to another aspect of this disclosure, a controller for communicating with a memory device is also provided, the memory device including memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The strings are organized by rows. The controller is configured to identify the at least one edge word line. The controller is further configured to instruct the memory device to program the memory cells of the string located in a specific row of the string and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation, compared to the memory cells of the string not located in a specific row of the string and not associated with the at least one edge word line.

[0008] According to an additional aspect of this disclosure, a method of operating a memory device is provided. The memory device includes memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The strings are organized by rows. The method includes the step of identifying the at least one edge word line. The method further includes the step of programming the memory cells of the string located in a specific row of the string and associated with the at least one edge word line to have a changed threshold voltage distribution for one or more of the plurality of data states during a programming operation, compared to the memory cells of the string not located in a specific row of the string and not associated with the at least one edge word line.

[0009] Further applicable fields will become apparent from the description provided herein. The descriptions and specific examples in this invention are intended for illustrative purposes only and are not intended to limit the scope of the invention. Attached Figure Description

[0010] The accompanying drawings described herein are for illustrative purposes only, and not for all possible specific implementations, and are not intended to limit the scope of this disclosure.

[0011] Figure 1A A block diagram of an exemplary memory device according to various aspects of this disclosure;

[0012] Figure 1B A block diagram of an exemplary control circuit including a programming circuit, a counting circuit, and a determining circuit according to various aspects of this disclosure;

[0013] Figure 2 Schematic diagrams are shown of three types of memory architectures utilizing interleaved memory strings according to various aspects of this disclosure;

[0014] Figure 3A A cross-sectional view of an exemplary floating-gate memory cell in a NAND string according to various aspects of this disclosure is shown;

[0015] Figure 3B The following are shown along the aspects according to this disclosure. Figure 3A A cross-sectional view of the contact line shown;

[0016] Figure 4A and Figure 4B A non-volatile memory according to various aspects of this disclosure is shown, wherein the charge trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate in order to store charge in a non-volatile manner;

[0017] Figure 5 An exemplary block diagram of the sensing block of FIG1 is shown according to various aspects of the present disclosure;

[0018] Figure 6A It is a perspective view of a set of blocks in an exemplary three-dimensional configuration of a memory array according to various aspects of the present disclosure;

[0019] Figure 6B The various aspects shown in this disclosure are as follows Figure 6A An exemplary cross-sectional view of a portion of a block;

[0020] Figure 6C The various aspects shown in this disclosure are as follows Figure 6B A diagram showing the diameter of memory holes in a stack;

[0021] Figure 6D The various aspects shown in this disclosure are as follows Figure 6B A close-up view of the stacked areas;

[0022] Figure 7A A schematic plan view of a memory array having multiple memory holes according to various aspects of the present disclosure is shown;

[0023] Figure 7B A cross-sectional view of a memory array according to various aspects of this disclosure is shown;

[0024] Figure 8A and Figure 8B An alternative memory structure without dummy holes is shown according to various aspects of this disclosure;

[0025] Figure 9 A set of exemplary threshold voltage distributions according to various aspects of this disclosure are depicted;

[0026] Figure 10 A cross-sectional top view of a memory hole taken at the drain-side gate layer and edge word line layer according to various aspects of the present disclosure is shown.

[0027] Figure 11 The following diagram illustrates the threshold voltage distribution and corresponding data or memory states of an exemplary memory device before and after a high-temperature data retention test, according to various aspects of this disclosure.

[0028] Figure 12 The threshold voltage distribution of memory cells according to various aspects of this disclosure is shown, illustrating exemplary pre-compensation by programming memory cells programmed to the highest data state only in the semicircular row of edge word lines after programming and immediately after high-temperature data retention testing to a higher threshold voltage.

[0029] Figure 13 The threshold voltage distribution of memory cells according to various aspects of this disclosure is shown, illustrating another exemplary pre-compensation by programming memory cells that will be programmed to the highest data state for both the semicircular and full-circular rows of edge word lines after programming and immediately after the high-temperature data retention test to a higher threshold voltage.

[0030] Figure 14 The threshold voltage distribution of memory cells according to various aspects of this disclosure is shown, illustrating another exemplary pre-compensation by programming memory cells that will be programmed to the seventh, sixth, and fifth data states, respectively, for both the semicircular and full-circular rows of edge word lines after programming and immediately after the high-temperature data retention test, to a higher threshold voltage.

[0031] Figure 15 The threshold voltage distribution of memory cells according to various aspects of this disclosure is illustrated, showing another exemplary pre-compensation achieved by programming memory cells, which will be programmed to the seventh, sixth, and fifth data states for both semi-circular and full-circular rows of edge word lines immediately after programming and following a high-temperature data retention test, to a tighter threshold voltage distribution; and

[0032] Figure 16 The steps of a method for operating a memory device according to various aspects of this disclosure are shown.

[0033] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0034] In the following description, details are set forth to provide an understanding of this disclosure. In some instances, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure this disclosure.

[0035] Generally, this disclosure relates to a type of nonvolatile memory device that is well-suited to many applications. The nonvolatile memory device and associated methods of operation of this disclosure will be described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are merely for the purpose of clearly describing the concepts, features, advantages, and objects of the invention to allow those skilled in the art to understand and practice this disclosure. Specifically, exemplary embodiments are provided so that this disclosure will be comprehensive and will fully convey the scope to those skilled in the art. Numerous specific details, such as examples of specific components, apparatus, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, exemplary embodiments may be embodied in many different forms, and none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0036] In some memory devices or apparatuses, memory cells are joined together, such as in NAND strings within a block or sub-block. Each NAND string comprises a plurality of memory cells connected in series between one or more drain-side selected-gate SG transistors (SGD transistors) located on the drain side of the NAND string connected to a bit line and one or more source-side selected-gate SG transistors (SGS transistors) located on the source side of the NAND string connected to a source line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) serving as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells may be connected in other types of string connections and in other ways.

[0037] In a 3D memory architecture, memory cells can be arranged in a stacked vertical string, wherein the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Memory cells may include data memory cells eligible to store user data, as well as dummy memory cells or non-data memory cells not eligible to store user data.

[0038] Before programming certain non-volatile memory devices, memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gate of the erased memory cell. Alternatively, the erase operation removes electrons from the charge trapping layer.

[0039] Each memory cell can be associated with a data state based on the data written in the program commands. Based on the data state of that memory cell, the memory cell will remain in an erase state or be programmed into a programmed data state. For example, in a three-bit memory device, there are eight data states, including erase and programmed states.

[0040] During the programming operation, memory cells are programmed according to the word line programming sequence. For example, programming can begin with a word line on the source side of the block and proceed to a word line on the drain side of the block. In one approach, programming of each word line is completed before programming of the next word line. For example, the first word line WL0 is programmed using one or more programming pulses until programming is complete. Next, the second word line WL1 is programmed using one or more programming pulses until programming is complete, and so on. The programming pulses may include a set of increasing programming voltages, which are applied to the word lines in the corresponding programming cycle or program-verify iteration. A verification operation or stage can be performed after each programming voltage to determine whether the memory cell has been programmed. When programming of a memory cell is complete, further programming of that memory cell can be suppressed while programming of other memory cells continues in subsequent programming cycles.

[0041] When creating various rows and strings for memory structures, dicing operations (e.g., shallow hole etching (SHE)) can be used. This SHE dicing divides a block (in memory) into multiple strings within the block. While SHE can form / define strings, SHE dicing can further separate strings, i.e., cut the edge memory holes in the string in half (or approximately two equal halves). At this point, both the SGD and the channel are separated. Ideally, SHE dicing only needs to reach down to the SGD layer. However, due to process (etching) variations, precise dicing at the SGD is extremely difficult, and some dies may be diced down to one of the dummy word line layers (e.g., ...). Figure 6B The DWLD0 layer), but some dies can also be cut to another dummy word line layer in the dummy word line layer (e.g., ...). Figure 6B (DWLD1 layer) or even the top or edge word line (e.g., Figure 6B (WLL10). When the SHE cut is closer to the top or edge of the word line (without physical cutting), the data retention (e.g., high temperature data retention / HTDR) becomes significantly worse (unacceptable).

[0042] Several aspects of this disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware implementation or a software implementation (including, but not limited to, firmware, resident software, microcode, etc.), or may be a combination of hardware and software components, which are generally referred to collectively as a “circuit,” “module,” “apparatus,” or “system.” Additionally, aspects of this disclosure may be, for example, in the form of a computer program process embodied in one or more non-transitory computer-readable storage media storing computer-readable program code and / or computer-executable program code.

[0043] Additionally, various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this document is not intended to distinguish components with different names rather than different functions. With regard to the various functional units described in the following disclosure being referred to as “modules,” this designation is intended not to unduly limit the scope of possible implementation mechanisms. For example, a “module” may be implemented as hardware circuitry comprising custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In another example, modules may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic units, programmable logic devices, etc. Furthermore, modules may also be implemented, at least in part, by software executed by various types of processors. For example, a module may include executable code segments that constitute one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such modules be physically located together, but rather that they may include different instructions stored in different locations, and when executed together, constitute the identified module and achieve the stated purpose of the module. Executable code may include a single instruction or a collection of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In specific implementations of software or portions of software modules, the software portions may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs for use by or in connection with an instruction execution system, apparatus, processor, or device.

[0044] Similarly, for the purposes of this disclosure, the term "component" can refer to any tangible, physical, and non-transient device. For example, a component can be in the form of hardware logic circuitry composed of custom VLSI circuitry, gate arrays, or other integrated circuits, or of off-the-shelf semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic equipment. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic components, programmable logic devices, etc. Additionally, a component can be composed of one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices, which are electrically connected to one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0045] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths allowing current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components may provide a return path for current. In contrast, in an open-loop configuration, the circuit components may be considered to form a circuit, although a return path for current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether it is grounded (as a return path for current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuitry, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are electrically connected to one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic components, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, in some embodiments, modules as defined above may be embodied or implemented as circuits.

[0046] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions that control one or more microprocessors to implement some, most, or all of the functions disclosed herein in conjunction with certain non-processor circuitry and other elements. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combinations of certain functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the reference to “controller” below should be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0047] Furthermore, as may be used herein, the terms “program,” “software,” “software application,” etc., refer to a sequence of instructions designed to be executed on a computer-implemented system. Therefore, “program,” “software,” “application,” “computer program,” or “software application” can include subroutines, functions, procedures, object methods, object implementations, executable applications, applets, service applets, source code, object code, shared libraries / dynamically loaded libraries, and / or other sequences of specific instructions designed to be executed on a computer system.

[0048] Additionally, as may be used herein, the terms “coupled,” “coupled,” or “connected” are intended to indicate a direct or indirect connection. Thus, if a first device is coupled to or is coupled to a second device, the connection may be made either directly or indirectly via another device (or component) and connection.

[0049] Regarding the use of terms such as “implementation,” “one implementation,” “exemplary implementation,” “specific implementation,” or other similar terms herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with that implementation exists in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one implementation,” “in an implementation,” “in a particular implementation,” etc., may, but not necessarily, refer to the same implementation, but rather to “one or more, but not all, implementations,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…,” unless expressly stated otherwise. Additionally, an element preceded by “comprising…” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element, unless further limited.

[0050] The terms “a,” “an,” and “the” also mean “one or more” unless otherwise expressly stated. Furthermore, the phrase “at least one of A and B” (where A and B are variables indicating a particular object or property) used herein and / or in the appended claims indicates a choice of A or B, or a choice of both A and B, similar to the phrase “and / or.” Where more than two variables are present in such a phrase, the phrase is thereby defined as including only one of the variables, any of the variables, any combination (or subcombination) of any of the variables, and all of the variables.

[0051] Furthermore, as used herein, the terms “about” or “approximately” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to (e.g., having the same function or result) the value referenced. In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0052] Furthermore, any enumerated list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly stated. Additionally, as used herein, the term “group” should be interpreted as “one or more” according to the established theory, and in the case of “multiple groups”, it should be interpreted as a plural (multiple) of “one or more” and / or “many or more”, unless otherwise expressly stated.

[0053] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. It will be appreciated that the foregoing summary is merely exemplary and not intended to be limiting in any way. In addition to the illustrative aspects, exemplary embodiments, and features described above, further aspects, exemplary embodiments, and features will become apparent from the accompanying drawings and the following detailed description. The description of elements in each figure may refer to elements in the preceding figures. Similar reference numerals may refer to similar elements in the drawings, including alternative exemplary embodiments of similar elements.

[0054] Figure 1AThis is a block diagram of an exemplary memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines via row decoder 124 and via bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sense blocks SB1, SB2, ..., SBp (sensor circuitry system) and allows for parallel reading or programming of pages of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0055] Memory structure 126 can be two-dimensional or three-dimensional. Memory structure 126 may include an array of one or more memory cells, including a three-dimensional array. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed on (but not in) a single substrate such as a wafer, without an intervening substrate. Memory structure 126 may include any type of non-volatile memory integrally formed in an array of memory cells having one or more physical levels having active regions disposed above a silicon substrate. Memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is above or within the substrate.

[0056] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0057] Storage area 113 may be provided, for example, for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, the location of the memory cell on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector, the substrate or material constituting the contact connector, etc.

[0058] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to word lines and bit lines during memory operation. This power control module may include drivers for word lines, SGS transistors, and SGD transistors with source lines. In one approach, a sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0059] In some implementations, some of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ... SBp, read / write circuit 128, controller 122, etc.

[0060] The control circuitry may include programming circuitry configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells allocated to represent one of a plurality of data states, and memory cells allocated to represent another of the plurality of data states; the programming and verification operations include multiple programming and verification iterations; and in each programming and verification iteration, the programming circuitry performs programming on a word line, after which the programming circuitry applies a verification signal to a word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for one data state. The control circuitry may further include a determining circuit configured to determine a specific programming and verification iteration among the plurality of programming and verification iterations based on an amount by which the count exceeds a threshold, in which a verification test is performed on the memory cells allocated to represent the other data state.

[0061] For example, Figure 1B This is a block diagram of an exemplary control circuit 150 including a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0062] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0063] Memory devices 122a and 122b include code, such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or otherwise, processor 122c may access code from storage device 126a of memory structure 126, such as reserved areas of memory cells in one or more word lines. For example, controller 122 may use code to access memory structure 126, such as for programming operations, read operations, and erase operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is software that initializes controller 122 during boot or startup and enables controller 122 to access memory structure 126. Controller 122 may use code to control one or more memory structures 126. Upon power-up, processor 122c fetches boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0064] Generally speaking, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below.

[0065] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0066] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0067] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0068] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0069] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0070] NAND memory arrays can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or on the substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0071] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0072] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0073] A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the main surface of the substrate).

[0074] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., along the y-direction), each column having multiple memory cells. The columns can be arranged in a two-dimensional configuration, for example, in the xy-plane, resulting in a three-dimensional arrangement of memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0075] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0076] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or may have intervening layers between memory device classes.

[0077] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0078] Figure 2 Schematic diagrams of three types of memory architectures utilizing interleaved memory strings are shown. For example, reference numeral 201 shows a schematic diagram of a first exemplary memory architecture, reference numeral 203 shows a schematic diagram of a second exemplary memory architecture, and reference numeral 205 shows a schematic diagram of a third exemplary memory architecture. In some embodiments, as shown, the memory architecture may include an array of interleaved NAND strings.

[0079] Figure 2 Blocks 200 and 210 of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG1 are shown. The memory array 126 may include a plurality of such memory blocks 200 and 210. Each exemplary block 200, 210 includes multiple NAND strings and corresponding bit lines, such as BL0, BL1, ... shared between blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The NAND string is connected at its other end to a source-side select gate (SGS), which is then connected to a common source line 220. Sixteen word lines, such as WL0-WL15, extend between the SGS and the SGD. In some cases, dummy word lines that do not contain user data may also be used in memory arrays adjacent to select-gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0080] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, such as... Figure 3A and Figure 3B The floating-gate memory shown is of this type. However, other types of non-volatile memory can also be used. As discussed in further detail below, Figure 4A and Figure 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between the surface of a conductive control gate and a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a limited area. The stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided with a split-gate configuration, where a doped polysilicon gate extends above a portion of the memory cell channel to form a separate selection transistor.

[0081] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over a channel between the source and drain diffusion regions. The charge for one data bit is located in the dielectric layer adjacent to the drain, and the charge for the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separated charge storage regions within the dielectric, respectively. Other types of non-volatile memories are also known.

[0082] Figure 3A Cross-sectional views of exemplary floating-gate memory cells 300, 310, and 320 in a NAND string are shown. In this figure, bit lines or NAND string directions enter the page, and word lines are oriented from left to right. For example, word line 324 extends across a NAND string that includes corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each of memory cells 300, 310, and 320 is located in a different corresponding NAND string. A polysilicon interlayer dielectric (IPD) layer 328 is also shown. Control gates 302, 312, and 322 are part of the word line. Figure 3B A cross-sectional view along the contact line connector 329 is provided.

[0083] Control gates 302, 312, and 322 are wound around floating gates 304, 314, and 321, thereby increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, which in turn leads to a higher coupling ratio, making programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is almost no space between two adjacent floating gates 302, 312, and 322 for control gates 302, 312, and 322 and the IPD layer 328.

[0084] As an alternative, such as Figure 4A and Figure 4B As shown, planar or flat memory cells 400, 410, 420 have been developed in which the control gates 402, 412, 422 are flat or planar; that is, the control gate is not wrapped around the floating gate, and the only contact between the control gate and the charge storage layer 428 is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the ballistic electron transport problem, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0085] Figure 4A A cross-sectional view of exemplary charge-trapping memory cells 400, 410, and 420 in a NAND string is shown. This view is in the word line direction of the memory cells 400, 410, and 420, including planar control gates and charge-trapping regions, as a two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126 of FIG. 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, compared to floating-gate MOSFET technology which uses conductors such as doped polysilicon to store electrons. For example, word lines 424 extend across a NAND string including corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. IPD layers 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunnel layers 409, 407, and 408 are located below the word lines. Each charge trapping layer 404, 414, 421 extends continuously within its respective NAND string. The flat configuration of the control gates allows for a thinner fabrication compared to floating gates. Furthermore, memory cells can be placed closer together.

[0086] Figure 4B It shows Figure 4AThe structure is shown in a cross-sectional view along the contact line connector 429. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. Passages in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate layer 402 and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0087] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0088] Figure 5An exemplary block diagram of the sensing block SB1 of Figure 1 is shown. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, exemplary sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with this group of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage may be provided to each sensing circuit independently, for example, via a data bus and a local bus. In another possible approach, a common voltage may be provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include the precharge circuit 561, a memory 562, and a processor 563. Memory 562 may store code that can be executed by a processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, and 553b associated with sensing circuits 550a, 551a, 552a, and 553a, setting bit values ​​in the latches, and providing voltages for setting pre-charge levels in the sensing nodes of sensing circuits 550a, 551a, 552a, and 553a. Further exemplary details of the sensing circuit controller 560 and the sensing circuits 550a, 551a, 552a, and 553a are provided below.

[0089] In some embodiments, a memory cell may include a tag register comprising a set of latches storing tag bits. In some embodiments, the number of tag registers may correspond to the number of data states. In some embodiments, one or more tag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the tag bits may modify associated logic of the device, such as address decoding circuitry, to select a specified cell block. Body operations (e.g., erase operations, etc.) may be performed using tags set in the tag register, or a combination of tag registers and address registers, as in implicit addressing, or alternatively by direct addressing using only address registers.

[0090] Figure 6AThis is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG1. ​​On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include voltage drivers 605 connectable to the control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are commonly driven. The substrate 601 may also carry circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, along with one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a central region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry circuit signals. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, where alternating stacked levels represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides from which vertical contacts extend upwards to the upper metal layer to form connections with the conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are shown as an example, two or more blocks extending in the x and / or y directions can be used.

[0091] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0092] Figure 6B It shows Figure 6AAn exemplary cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0-WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0-DL19. Furthermore, a region of stack 610 including NAND strings NS1 and NS2 is shown. Each NAND string contains memory vias 618 and 619 filled with material forming memory cells adjacent to the word lines. Region 622 of stack 610 is shown in… Figure 6D This is shown in more detail below, and discussed further in detail below.

[0093] Stack 610 includes a substrate 611, an insulating film 612 located on the substrate 611, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be provided periodically across the stack 610 as interconnects extending through the stack 610, such as to connect source lines to specific contact lines above the stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently metal-filled. A portion of a bit line BL0 is also shown. A conductive via 621 connects the drain terminal 615 to BL0.

[0094] Figure 6C It shows Figure 6B A graph showing the diameter of memory holes in a stack. The vertical axis is... Figure 6B The stacking alignment is shown, and the width (wMH) of memory holes 618 and 619, such as the diameter, is shown. Figure 6A Word line layers WLL0-WLL10 are repeated as an example, and are located at corresponding heights z0-z10 in the stack. In such memory devices, the memory vias etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter of the memory via gradually decreases from its top to its bottom. That is, the memory via is tapered, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the via near the select gate, causing the diameter of the memory via to slightly widen before gradually decreasing from its top to its bottom.

[0095] Due to the non-uniformity of memory via width, the programming speed, including the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory via (e.g., based on the height of the memory cell in the stack). For smaller diameter memory vias, the electric field across the tunnel oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define a group of adjacent word lines with a diameter similar to the memory via (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0096] Figure 6D It shows Figure 6B A close-up view of region 622 of stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680, 681 are disposed above dummy memory cells 682, 683 and data memory cell MC. Multiple layers may be deposited, for example, along the sidewalls (SW) of memory via 630 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. Word line layers may include a blocking oxide / bulk high-k material 660, a metal blocking layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided within memory via 630. In other methods, some layers within the layer can be in the control gate layer. Additional pillars are similarly formed in different memory vias. These pillars can form pillared active regions (AA) of the NAND string.

[0097] When a data memory cell MC is programmed, electrons are stored in a portion of the charge trapping layer 663 associated with the memory cell MC. These electrons are attracted from the channel 665 into the charge trapping layer 663 and pass through the tunnel layer 664. The Vth of the memory cell MC increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel 665.

[0098] Each memory via 630 may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer 663, a tunnel layer 664, and a channel layer 665. The core region of each memory via 630 is filled with the host material, and the multiple annular layers are located between the core region and the word line in each memory via 630.

[0099] NAND strings can be considered to have floating channels 665 because the length of the channels 665 is not formed on the substrate. In addition, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0100] Figure 7A A schematic plan view of a memory array 700 with multiple memory vias 722 and multiple dummy vias 705 is shown. These multiple memory vias can be vertical chains of memory cells as described herein, and the multiple dummy vias do not require a complete memory structure. Shallow trench etch or shallow etched feature (SHE) 710 extends through multiple word lines (e.g., five), but not completely through the chip, to electrically isolate adjacent strings from each other. The SHE extends directly through a set of aligned dummy vias 705, thereby preventing those dummy vias 705 from storing data or otherwise becoming functional memory cells.

[0101] Now for reference Figure 8A and 8B There are no fictitious holes. (And) Figure 7A and 7B Unlike the memory structure 700, the SHE 810 is located in the gap between two adjacent rows of memory cells 825 and overlaps with the memory holes 825 to form a working chain. This working chain has a trench etched into at least one side of the SGD switch at the top of the working memory chain, shown here as the memory hole 825. This configuration significantly improves yield and memory density because all memory holes 822, 825 are functional, i.e., fewer memory holes are wasted.

[0102] Unlike the fully circular memory hole 822, the memory hole 825 and SGD switch, which are partially cut by the SHE 810, have a semi-circular shape, which can be a semi-circle or larger or smaller than a semi-circle. In some cases, the memory hole 825 and SGD switch can be smaller than a semi-circle on one side of the SHE 810 and larger than a semi-circle on the other side of the SHE 810.

[0103] Memory holes 822, 825 and multiple bit lines 830 (labeled as) Figure 8A Bit lines 0-7 in the string are connected. For ease of illustration, only eight bit lines 830 are shown. Bit lines 830 extend above the memory holes and are connected to select the memory holes via connection points. The memory holes in each string region are also connected at one end to the SGD switch and at the other end to the SGS switch. The SHE trench 810 can be etched into a portion of the SGD switch.

[0104] At the end of a successful programming process (with verification), the threshold voltage of the memory cell should, where appropriate, be within one or more distributions of the threshold voltages for the programmed memory cell or within the distribution of the threshold voltages for the erased memory cell. Figure 9 An exemplary threshold voltage Vt distribution corresponding to the data state for a memory cell array is shown when each memory cell stores three bits of data. However, other embodiments may use more or fewer bits of data per memory cell. Figure 9 The distribution of eight threshold voltages Vt corresponding to the erase state and the programming state AG is shown. In one embodiment, the threshold voltages in the erase state are negative, and the threshold voltages in the programming state AG are positive.

[0105] However, the threshold voltage in one or more programming states of programming state AG can be negative. Therefore, in one implementation, at least VrA is negative. Other voltages such as VvA, VrB, VvB, etc., can also be negative.

[0106] Between each data state in the data state is a read reference voltage used to read data from the memory cell. For example, Figure 9 The diagram shows the read reference voltage VrA between the erase state and state A, and VrB between state A and state B. By testing whether the threshold voltage of a given memory cell is higher or lower than the corresponding read reference voltage, the system can determine the state of the memory cell.

[0107] At or near the lower edge of each programmed state is the verification reference voltage. For example, Figure 9 The diagram shows VvA for state A and VvB for state B. When memory cells are programmed to a given state, the system tests whether these memory cells have a threshold voltage greater than or equal to the verification reference voltage.

[0108] As discussed above, and referring back to [reference] Figure 8A and Figure 8B The SHE trench 810 can be etched into a portion of the drain-side select-gate SGD switch. Ideally, the SHE cut or trench 810 only needs to extend down to the drain-side select-gate SGD layer (i.e., Figure 6D (SGD1 in the middle). However, due to process (etching) variations, it can be extremely difficult to cut to the drain-side select gate SGD layer consistently and precisely; some dies will be cut to the first dummy word line or layer DD0 (i.e., Figure 6D In the DWLD0), and some dies were even cut to the second dummy word line or layer DD1 (i.e., Figure 6D(DWLD1 in the example). When the SHE cut or trench 810 is closer to the data word line (i.e., deeper), data retention becomes significantly worse. This is due to physical damage to the memory cells near the bottom of the physical SHE caused by SHE etching / cleaning. Figure 10 This illustrates the selection of the gate SGD layer on the drain side. Figure 10 The leftmost part) and the edge letter line layer ( Figure 10 The memory hole (MH) cut off at the far right part) Figure 10 A top-section cross-sectional view of the shaded circle in the image. Rows of memory holes with semicircular drain-side select gates (SC-SGDs) are indicated by dashed boxes, while other memory holes do not include semicircular drain-side select gates (SC-SGDs). Figure 11 The diagram illustrates the threshold voltage distribution and corresponding data or memory states for an exemplary memory device before (graph 850) and after (graph 852) a High Temperature Data Retention (HTDR) test. As shown, memory cells without a semi-circular drain-side selected gate SC-SGD (i.e., a full-circular drain-side selected gate FC-SGD) and memory vias associated with edge word lines exhibit relatively good data retention, while memory cells with a semi-circular drain-side selected gate SC-SGD and memory vias associated with edge word lines exhibit relatively poor data retention. In other words, memory cells with memory vias having a semi-circular drain-side selected gate SC-SGD lose more charge due to additional Sherie damage than memory cells without a semi-circular drain-side selected gate SC-SGD, but only at the edge word lines.

[0109] One solution to the data retention problem caused by the depth of the SHE trench 810 is to have one or more additional dummy word line layers to avoid this edge word line data retention loss. However, such additional dummy word lines increase process costs. Another solution is to introduce a plasma-induced oxidation (PIO) process to recover from RIE damage. This has proven effective in mitigating the edge word line data retention problem; however, it is not a complete repair because some states (e.g., F / G states) may still be contaminated under optimal conditions.

[0110] Therefore, this article describes a system including memory cells (e.g., Figure 6D The memory device (e.g., data memory unit MC and virtual memory units 682, 683) is a data memory unit MC and a virtual memory unit 682, 683. Figure 1A The memory device 100), the memory cell is connected to multiple word lines (e.g., Figure 6B Data word line layer (word line) WLL0-WLL10 or Figure 6D One word line in WLL10), the plurality of word lines including at least one edge word line (e.g., Figure 6BWLL10) and several other data word lines (e.g., Figure 6B (WLL0-WLL9). Memory cells are in strings (e.g., Figure 6B The NAND strings NS1 and NS2 are arranged and configured to maintain a threshold voltage Vt or Vth corresponding to one of a plurality of memory or data states. Figure 9 The string is organized row by row. The memory device also includes control circuitry or devices (e.g., control circuitry 110, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuitry 128, ...). Figure 1A Controller 122 Figure 1B Control circuit 150 and / or Figure 5 (One or any combination of the sensing circuit controller 560, etc.). The control device is configured to identify the at least one edge word line. The control device is also configured to program the memory cells of the string that are in a specific row of the row and associated with the at least one edge word line to have a changed threshold voltage Vt distribution for one or more of the plurality of data states during the programming operation, compared with the memory cells of the string that are not in a specific row of the row and are not associated with the at least one edge word line. Therefore, the purpose of the memory devices and methods disclosed herein is to implement a novel edge word line programming technique that can help alleviate edge word line data retention problems without adding an additional dummy word line layer. According to aspects of this disclosure and as will be discussed below, the memory devices and methods disclosed herein can program higher data states for edge word lines to a higher threshold voltage Vt in selective rows (e.g., semicircular rows), which provides sufficient threshold voltage Vt tolerance for higher states after HTDR.

[0111] Return to reference Figure 6B For example, multiple word lines (e.g., Figure 6B The word line layer (word line) WLL0-WLL10) and multiple dielectric layers (e.g., Figure 6B The DL0-DL19) extend horizontally and overlap each other in an alternating manner in a stack (e.g., stack 610), and the strings (e.g., Figure 6B The NAND strings NS1 and NS2 extend vertically through the stack. Memory cells are located on the drain side of each string (e.g., at the SGD0 or SGD1 layer) and connected to one of a plurality of bit lines (e.g., ...). Figure 6B At least one drain-side selected gate SGD transistor of BL0) is located on the source side of each string (e.g., at the SGS0 or SGS1 layer) and connected to the source line (e.g., Figure 6BAt least one source-side selected-gate transistor (SGD) is connected in series. The at least one edge word line is vertically disposed above and adjacent to at least one drain-side selected-gate transistor (SGD).

[0112] See back Figure 9 For each memory cell in the memory cell, the possible threshold voltage Vt spans a threshold window 900. Each memory cell is configured to store multiple bits. Multiple data states include an erase state at the first end 902 of the threshold window 900 (e.g., ...). Figure 9 The erase state in the data) and multiple programmed data states (e.g., Figure 9 States A, B, C, D, E, F, and G), each corresponding to a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state. Multiple programming data states include the highest data state (e.g., at the second end 904 of the threshold window opposite the first end 902) associated with a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state and at least one other programming data state among the multiple programming data states. Figure 9 State G).

[0113] The rows of a string may include full-circle rows and semi-circle rows, which include memory holes forming the string, the memory holes being partially cut by shallow hole etching (SHE) cuts 810 extending vertically into the stack. Thus, according to one aspect, a particular row within a string is a semi-circle row. Figure 12The threshold voltage Vt distribution of memory cells is shown, illustrating exemplary pre-compensation by programming memory cells programmed to the highest data state (e.g., G state) only in the semicircular rows of edge word lines after programming and immediately after a high-temperature data retention test to a higher threshold voltage Vt. Therefore, the control device is further configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to at least one edge word line during the programming operation until the memory cell programmed to the highest data state and associated with the full-circular row reaches a first highest verification voltage level GV_FC (low) for the highest data state. The control device is also configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with the semicircular row and at least one edge word line reaches a second highest verification voltage level GV_SC (high) for the highest data state. The second highest verification voltage level GV_SC (high) is higher than the first highest verification voltage level GV_FC (low). Additionally, the control device is configured to, when programming a memory cell associated with at least one edge word line to prevent programming of memory cells associated with full-circle rows in the string, simultaneously disable bit line voltages applied to the bit lines of the string coupled to full-circle rows among the multiple bit lines; and when programming a memory cell associated with at least one edge word line to facilitate programming of memory cells associated with half-circle rows in the string, select bit line voltages applied to the bit lines of the string coupled to half-circle rows among the multiple bit lines. Thus, memory holes or strings with semi-circular SGDs are pre-compensated by programming the highest data state (e.g., G state) to a higher threshold voltage Vt only in the half-circle rows of edge word lines. This technique is effective when edge word line problems are not severe. For example, this technique is effective when only half-circle G state memory cells are contaminated. It should be noted that programming full-circle rows with GV_FC (low) and programming half-circle rows with GV_SC (high) can occur in the same programming sequence or different programming sequences.

[0114] Similarly, rows can include full-circle rows and semi-circle rows. Depending on one aspect, a particular row in a row can be both a semi-circle row and a full-circle row. Figure 13The threshold voltage Vt distribution of memory cells is shown, illustrating another exemplary pre-compensation by programming memory cells programmed to the highest data state (e.g., G state) for both semicircular and full-circular rows of edge word lines after programming and immediately after a high-temperature data retention test to a higher threshold voltage Vt. Therefore, the control is further configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to a plurality of other data word lines during the programming operation until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches the low maximum verification voltage level GV(low) of the highest data state. The control is also configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to at least one edge word line during the programming operation until the memory cell programmed to the highest data state associated with at least one edge word line reaches the high maximum verification voltage level GV(higher) of the highest data state. The high maximum verification voltage level GV(higher) is magnitude greater than the low maximum verification voltage level GV(low). Therefore, all memory vias or strings with semi-circular and full-circular SGDs on the edge word line are pre-compensated by programming the highest data state (e.g., G state) to a higher threshold voltage Vt. This technique is effective when the edge word line problem is not too severe. For example, it will be effective when only half-circular G state memory cells are contaminated.

[0115] As mentioned above, rows can include full-circle rows and semi-circle rows. Depending on one aspect, a particular row within a row can be both a semi-circle and a full-circle row. Multiple bits comprise three bits, and the total number of states for multiple data states is eight. Therefore, multiple programmed data states (e.g., Figure 9 The states A, B, C, D, E, F, and G are listed in the order of increasing threshold voltage Vt, including the first data state (e.g., ...). Figure 9 State A) and second data state (e.g., Figure 9 State B) and third data state (e.g., Figure 9 State C) and the fourth data state (e.g., Figure 9 State D) and the fifth data state (e.g., Figure 9 State E) and the sixth data state (e.g., Figure 9 State F) and the seventh data state (e.g., Figure 9 The highest data state is the seventh data state. Figure 14The threshold voltage Vt distribution of memory cells is shown, illustrating another exemplary pre-compensation by programming memory cells, after programming and immediately after the high-temperature data retention test, to a higher threshold voltage Vt for both the semicircular and full-circular rows of edge word lines, which will be programmed to a seventh data state (e.g., G state), a sixth data state (e.g., F state), and a fifth data state (e.g., E state). Therefore, for a memory cell associated with a plurality of other data word lines and programmed during programming operations to one of a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the control device is further configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to the plurality of other data word lines during programming operations, until the memory cell programmed to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state reaches one of the following voltage levels: a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, a low fourth voltage level of the fourth data state, a low fifth voltage level of the fifth data state (EV (low), a low sixth voltage level of the sixth data state (FV (low), and a low seventh voltage level of the seventh data state (GV (low))). For a memory cell associated with at least one edge word line and programmed during programming to one of a first data state, a second data state, a third data state, and a fourth data state, the control device is configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to a plurality of other data word lines during programming operations, until the memory cell programmed to one of the first data state, the second data state, the third data state, and the fourth data state reaches one of a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, and a low fourth voltage level of the fourth data state, respectively. For a memory cell associated with at least one edge word line and programmed to one of the fifth, sixth, and seventh data states during a programming operation, the control device is configured to apply each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to a plurality of other data word lines during the programming operation, until the memory cell programmed to one of the fifth, sixth, and seventh data states reaches one of the high fifth voltage level EV (higher) of the fifth data state, the high sixth voltage level FV (higher) of the sixth data state, and the high seventh voltage level GV (higher) of the seventh data state, respectively.The higher fifth voltage level EV (higher) is greater than the lower fifth voltage level EV (low), and the higher sixth voltage level FV (higher) is greater than the lower sixth voltage level FV (low), and the higher seventh voltage level GV (higher) is greater than the lower seventh voltage level GV (low). Therefore, all memory holes or strings with semi-circular and full-circular SGDs on the edge word lines are pre-compensated by programming the seventh data state (e.g., G state), the sixth data state (e.g., F state), and the fifth data state (e.g., E state) to higher threshold voltages Vt. Although only three states are shown as being pre-compensated, it should be understood that memory cells programmed to other states can also be pre-compensated.

[0116] Similarly, a particular row in a row can be both a semicircle and a full circle. Figure 15The threshold voltage Vt distribution of a memory cell is illustrated, showing another exemplary pre-compensation performed by programming memory cells, after programming and immediately after a high-temperature data retention test, to a tighter threshold voltage Vt distribution for both the semicircular and full-circular rows of edge word lines, which would be programmed to a seventh data state (e.g., G state), a sixth data state (e.g., F state), and a fifth data state (e.g., E state). Therefore, for memory cells associated with multiple other data word lines and programmed to any of multiple programmed data states during programming operations, the control is further configured to apply multiple programming pulses to the multiple other data word lines. The magnitudes of the multiple programming pulses gradually increase by a first programming step voltage DVPGM(large) in each of multiple cycles. For memory cells associated with at least one edge word line and programmed to a third data state, a second data state, and a first data state during programming operations, the control is also configured to apply multiple programming pulses to at least one edge word line, the magnitudes of which gradually increase by the first programming step voltage DVPGM(large) in each of multiple cycles. For a memory cell associated with at least one edge word line and programmed to the seventh, sixth, fifth, and fourth data states during programming operations, the control is configured to apply a plurality of programming pulses to the at least one edge word line, the magnitude of which gradually increases in each of a plurality of cycles to a second programming step voltage less than the first programming step voltage DVPGM(large). Thus, all memory vias or strings with semi-circular and full-circular SGDs on the edge word line are pre-compensated by programming the seventh data state (e.g., G state), the sixth data state (e.g., F state), and the fifth data state (e.g., E state) to a tighter threshold voltage Vt distribution achieved using the reduced programming step voltage (DVPGM). This compensation using a tighter threshold voltage Vt distribution makes the increase in programming time negligible (i.e., Tprog can be slower), but only for a single word line (e.g., an edge word line). Although only three states are shown as being pre-compensated, it should be understood that memory cells programmed to other states can also be pre-compensated.

[0117] Figure 16 The steps of a method for operating a memory device are illustrated. As described above, a memory device (e.g., Figure 1A The memory device 100) includes a word line connected to a plurality of word lines (e.g., Figure 6B Data word line layer (word line) WLL0-WLL10 or Figure 6D The memory cells of WLL10 (e.g., Figure 6D The data storage unit MC and virtual memory units 682, 683). The memory units are arranged in one or more strings (e.g., Figure 6BThe method comprises NAND strings NS1 and NS2, and is configured to maintain a threshold voltage Vt or Vth corresponding to one of a plurality of memory states. The strings are organized by row. The method includes step 1100 of identifying at least one edge word line. The method further includes step 1102 of programming memory cells of strings located in a particular row and associated with at least one edge word line to have a changed threshold voltage Vt distribution for one or more data states among a plurality of data states during programming operations, compared with memory cells of strings not located in a particular row and not associated with at least one edge word line.

[0118] See again Figure 6B For example, multiple word lines (e.g., Figure 6B The word line layer (word line) WLL0-WLL10) and multiple dielectric layers (e.g., Figure 6B The strings (DL0-DL19) extend horizontally and overlap each other alternately in a stack (e.g., stack 610), and the strings (e.g., Figure 6B The NAND strings NS1 and NS2 extend vertically through the stack. Memory cells are located on the drain side of each string (e.g., at the SGD0 or SGD1 layer) and connected to one of a plurality of bit lines (e.g., ...). Figure 6B At least one drain-side selected gate SGD transistor of BL0) is located on the source side of each string (e.g., at the SGS0 or SGS1 layer) and connected to the source line (e.g., Figure 6B At least one source-side selected-gate transistor (SGD) is connected in series. The at least one edge word line is vertically disposed above and adjacent to at least one drain-side selected-gate transistor (SGD).

[0119] As discussed above, see [link / reference] Figure 9 For each memory cell in the memory cell, the possible threshold voltage Vt spans a threshold window 900. Each memory cell is configured to store multiple bits. Multiple data states include an erase state at the first end 902 of the threshold window 900 (e.g., ...). Figure 9 The erase state in the data) and multiple programmed data states (e.g., Figure 9 States A, B, C, D, E, F, and G), each corresponding to a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state. Multiple programming data states include the highest data state (e.g., at the second end 904 of the threshold window opposite the first end 902) associated with a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state and at least one other programming data state among the multiple programming data states. Figure 9 State G).

[0120] As described, one example of pre-compensation involves programming the highest data state (e.g., G state) to a higher threshold voltage Vt only in semicircular rows of edge word lines. Again, rows include full-circular rows and semicircular rows, which include memory holes forming a string, the memory holes being partially cut by shallow hole etching (e.g., SHE notch 810) extending vertically into the stack. A specific row within a row is a semicircular row. According to one aspect, the method further includes the step of applying each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, to a plurality of other data word lines during a programming operation, until the memory cell programmed to the highest data state and associated with the full-circular row reaches a first highest verification voltage level GV_FC (low) for the highest data state. The method continues with the following steps: during the programming operation, each of a plurality of programming pulses, in each of a plurality of loops with progressively increasing magnitudes, is applied to at least one edge word line until the memory cell programmed to be associated with the highest data state of the semicircular row and at least one edge word line reaches a second highest verification voltage level GV_SC (high) of the highest data state. The second highest verification voltage level GV_SC (high) is higher than the first highest verification voltage level GV_FC (low). The method further includes the steps of: when programming a memory cell associated with at least one edge word line to prevent programming of memory cells associated with a full-circular row in the string, simultaneously disabling bit line voltages applied to the bit lines of the string coupled to the full-circular row among the plurality of bit lines; and when programming a memory cell associated with at least one edge word line to facilitate programming of memory cells associated with a semicircular row in the string, selecting bit line voltages applied to the bit lines of the string coupled to the semicircular row among the plurality of bit lines.

[0121] As described above, another example of pre-compensation involves programming the highest data state (e.g., G state) to a higher threshold voltage Vt for both semi-circular and full-circular rows of edge word lines. Thus, a particular row within a row is both a semi-circular and a full-circular row. According to one aspect, the method further includes the step of applying each of a plurality of programming pulses, whose magnitudes are progressively increased in each of a plurality of cycles, to a plurality of other data word lines during a programming operation until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches a low highest verification voltage level GV(low) of the highest data state. A next step of the method is to apply each of a plurality of programming pulses, whose magnitudes are progressively increased in each of a plurality of cycles, to at least one edge word line during a programming operation until the memory cell programmed to the highest data state associated with at least one edge word line reaches a high highest verification voltage level GV(higher) of the highest data state. The high highest verification voltage level GV(higher) is magnitude greater than the low highest verification voltage level GV(low).

[0122] As previously mentioned, another example of pre-compensation involves programming the seventh data state (e.g., G state), the sixth data state (e.g., F state), and the fifth data state (e.g., E state) to a higher threshold voltage Vt for both semi-circular and full-circular rows of edge word lines. Thus, a particular row within a row is both a semi-circular and a full-circular row. Similarly, multiple bits comprise three bits, and the total number of states for multiple data states is eight. Multiple programmed data states (e.g., Figure 9 The states A, B, C, D, E, F, and G are listed in the order of increasing threshold voltage Vt, including the first data state (e.g., ...). Figure 9 State A) and second data state (e.g., Figure 9 State B) and third data state (e.g., Figure 9 State C) and the fourth data state (e.g., Figure 9 State D) and the fifth data state (e.g., Figure 9 State E) and the sixth data state (e.g., Figure 9 State F) and the seventh data state (e.g., Figure 9The highest data state is the seventh data state. According to one aspect, the method further includes the following steps: for memory cells associated with a plurality of other data word lines and programmed during programming operations to one of the first data state, second data state, third data state, fourth data state, fifth data state, sixth data state, and seventh data state, during programming operations, each of a plurality of programming pulses whose magnitudes gradually increase in each of a plurality of cycles is applied to the plurality of other data word lines until the memory cells programmed to one of the first data state, second data state, third data state, fourth data state, fifth data state, sixth data state, and seventh data state reach one of the following voltage levels: a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, a low fourth voltage level of the fourth data state, a low fifth voltage level of the fifth data state (EV (low), a low sixth voltage level of the sixth data state (FV (low), and a low seventh voltage level of the seventh data state (GV (low)) respectively. The next step of the method is to apply, during the programming operation, each of a plurality of programming pulses, in which the magnitude of each of the plurality of cycles gradually increases, to a plurality of other data word lines for memory cells associated with at least one edge word line and programmed to one of the first data state, the second data state, the third data state, and the fourth data state, until the memory cells programmed to one of the first data state, the second data state, the third data state, and the fourth data state reach one of the following voltage levels: a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, and a low fourth voltage level of the fourth data state. The method continues with the following steps: For a memory cell associated with at least one edge word line and programmed to one of the fifth, sixth, and seventh data states during a programming operation, each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, is applied to a plurality of other data word lines during the programming operation, until the memory cell programmed to one of the fifth, sixth, and seventh data states reaches one of the following: a high fifth voltage level EV (higher) for the fifth data state, a high sixth voltage level FV (higher) for the sixth data state, and a high seventh voltage level GV (higher) for the seventh data state. The high fifth voltage level EV (higher) is magnitude greater than the low fifth voltage level EV (low), and the high sixth voltage level FV (higher) is magnitude greater than the low sixth voltage level FV (low), and the high seventh voltage level GV (higher) is magnitude greater than the low seventh voltage level GV (low).

[0123] As discussed above, another example of pre-compensation involves programming the seventh data state (e.g., G state), sixth data state (e.g., F state), and fifth data state (e.g., E state) into a tighter threshold voltage Vt distribution for both semi-circular and full-circular rows of edge word lines. Similarly, a particular row within a row is both a semi-circular and a full-circular row. According to one aspect, the method further includes the step of applying a plurality of programming pulses to a plurality of other data word lines for memory cells associated with and programmed to any of a plurality of programmed data states during programming operations, the magnitudes of the plurality of programming pulses gradually increasing by a first programming step voltage DVPGM(large) in each of a plurality of cycles. The method further includes the step of applying a plurality of programming pulses to at least one edge word line for memory cells associated with at least one edge word line and programmed to a third, second, and first data state during programming operations, the magnitudes of the plurality of programming pulses gradually increasing by a first programming step voltage DVPGM(large) in each of a plurality of cycles. The method continues with the following steps: for a memory cell associated with at least one edge word line and programmed to a seventh data state, a sixth data state, a fifth data state, and a fourth data state during programming operations, a plurality of programming pulses are applied to at least one edge word line, the magnitude of the plurality of programming pulses in each of a plurality of cycles gradually increasing to a second programming step voltage less than a first programming step voltage.

[0124] The advantages of the memory devices and methods disclosed herein include mitigating edge word line HTDR problems without adding any additional dummy word line layers. Furthermore, because the memory devices and methods disclosed herein program higher data states for edge word lines to higher threshold voltages in selective rows (e.g., semicircular rows), sufficient threshold voltage Vt tolerance for higher states is provided after HTDR.

[0125] Obviously, changes may be made to what is described and shown herein without departing from the scope defined in the appended claims. The foregoing description of embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or limiting of this disclosure. Various elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and can be used in selected embodiments, even if not specifically shown or described. The same applies to many other aspects. Such variations should not be considered as departing from this disclosure, and all such modifications are intended to be included within the scope of this disclosure.

Claims

1. A memory device, comprising: A memory cell connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the string being organized by row; as well as A controller, coupled to the plurality of word lines and the string, is configured to: Identify the at least one edge character line, and The memory cells of the string located in a specific row of the row and associated with the at least one edge word line are programmed from an erased state to have a changed threshold voltage distribution for one or more of the plurality of data states during the programming operation, compared with the memory cells of the string not located in a specific row of the row and not associated with the at least one edge word line, the specific row of the row including a semicircular row including memory holes partially cut by shallow hole etching.

2. The memory device of claim 1, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked alternately on top of each other in a stack, the strings extend vertically through the stack, the memory cell is connected in series between at least one drain-side selected gate transistor located on the drain side of each string and connected to one of the plurality of bit lines and at least one source-side selected gate transistor located on the source side of each string and connected to the source line, and the at least one edge word line is vertically disposed above the plurality of other data word lines and adjacent to the at least one drain-side selected gate transistor.

3. The memory device of claim 2, wherein the possible threshold voltage for each memory cell in the memory cells spans a threshold window, each memory cell in the memory cells is configured to store a plurality of bits, the plurality of data states including the erase state at a first end of the threshold window and a plurality of programming data states each corresponding to a threshold voltage higher than the threshold voltage associated with the erase state, the plurality of programming data states including a highest data state at a second end of the threshold window opposite to the first end and associated with a threshold voltage higher than the threshold voltage associated with the erase state and at least one of the plurality of programming data states.

4. The memory device of claim 3, wherein the rows comprise full-circle rows and semi-circle rows, the full-circle rows and the semi-circle rows comprising memory holes forming the string, the memory holes being partially cut by etching of the shallow holes extending vertically into the stack, and wherein the controller is further configured to: During the programming operation, each of a plurality of programming pulses, in which the magnitude value is gradually increased in each of a plurality of cycles, is applied to the plurality of other data word lines until the memory cell programmed to the highest data state and associated with the full circle row reaches the first highest verification voltage level of the highest data state; During the programming operation, each of the plurality of programming pulses, whose magnitudes are gradually increased in each of the plurality of cycles, is applied to the at least one edge word line until the memory cell programmed to be associated with the highest data state of the semicircular row and the at least one edge word line reaches a second highest verification voltage level of the highest data state, the second highest verification voltage level being higher than the first highest verification voltage level. and When programming a memory cell associated with at least one edge word line to prevent programming of a memory cell in the string associated with the full-circle row, bit line voltages are simultaneously disabled on the bit lines of the string coupled to the full-circle row among the plurality of bit lines; while when programming a memory cell associated with at least one edge word line to facilitate programming of a memory cell in the string associated with the semi-circle row among the plurality of bit lines, bit line voltages are selected to be applied to the bit lines of the string coupled to the semi-circle row among the plurality of bit lines.

5. The memory device of claim 3, wherein the rows comprise full-circle rows and semi-circle rows, the specific row in the rows being both the semi-circle row and the full-circle row, and the controller is further configured to: During the programming operation, each of a plurality of programming pulses, whose magnitudes gradually increase in each of a plurality of cycles, is applied to the plurality of other data word lines until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches the low highest verification voltage level of the highest data state; and During the programming operation, each of the plurality of programming pulses, whose magnitudes are gradually increased in each of the plurality of cycles, is applied to the at least one edge word line until the memory cell programmed to be associated with the highest data state of the at least one edge word line reaches the high maximum verification voltage level of the highest data state, which is greater in magnitude than the low maximum verification voltage level.

6. The memory device of claim 3, wherein the rows comprise full-circle rows and semi-circle rows, the specific row in the rows is both the semi-circle row and the full-circle row, the plurality of bits comprises three bits, the total number of states of the plurality of data states is eight, the plurality of programming data states, in ascending order of magnitude of the threshold voltage, comprise a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the controller is further configured to: For a memory cell associated with the plurality of other data word lines and programmed during the programming operation to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, during the programming operation, each of a plurality of programming pulses in which the magnitude gradually increases in each of a plurality of cycles is applied to the plurality of other data word lines until the memory cell programmed to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state reaches one of the following voltage levels: a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, a low fourth voltage level of the fourth data state, a low fifth voltage level of the fifth data state, a low sixth voltage level of the sixth data state, and a low seventh voltage level of the seventh data state. For a memory cell associated with the at least one edge word line and programmed to one of the first data state, the second data state, the third data state, and the fourth data state during the programming operation, each of the plurality of programming pulses with progressively increasing magnitudes in each of the plurality of cycles is applied to the plurality of other data word lines during the programming operation until the memory cell programmed to one of the first data state, the second data state, the third data state, and the fourth data state reaches one of the low first voltage level of the first data state, the low second voltage level of the second data state, the low third voltage level of the third data state, and the low fourth voltage level of the fourth data state, respectively. and For a memory cell associated with the at least one edge word line and programmed to one of the fifth, sixth, and seventh data states during the programming operation, each of the plurality of programming pulses, whose magnitudes gradually increase in each of the plurality of cycles, is applied to the plurality of other data word lines during the programming operation until the memory cell programmed to one of the fifth, sixth, and seventh data states reaches one of the high fifth voltage level of the fifth data state, the high sixth voltage level of the sixth data state, and the high seventh voltage level of the seventh data state, respectively, wherein the high fifth voltage level is magnitude greater than the low fifth voltage level, the high sixth voltage level is magnitude greater than the low sixth voltage level, and the high seventh voltage level is magnitude greater than the low seventh voltage level.

7. The memory device of claim 3, wherein the row comprises a full-circle row and the semi-circle row, the full-circle row and the semi-circle row comprising memory holes forming the string, the memory holes being partially cut by shallow holes etched vertically extending into the stack, the particular row of the row being both the semi-circle row and the full-circle row, the plurality of bits comprising three bits, the total number of states of the plurality of data states being eight, the plurality of programmed data states comprising a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state in ascending order of magnitude of the threshold voltage, the highest data state being the seventh data state, and the controller being further configured to: For a memory cell associated with the plurality of other data word lines and programmed to any of the plurality of programmed data states during the programming operation, a plurality of programming pulses are applied to the plurality of other data word lines, the magnitude of the plurality of programming pulses gradually increasing by a first programming step voltage in each of a plurality of cycles. For the memory cell associated with the at least one edge word line and programmed to the third data state, the second data state, and the first data state during the programming operation, a plurality of programming pulses are applied to the at least one edge word line, the magnitude of the plurality of programming pulses gradually increasing the first programming step voltage in each of the plurality of cycles; and For the memory cell associated with the at least one edge word line and programmed to the seventh data state, the sixth data state, the fifth data state, and the fourth data state during the programming operation, a plurality of programming pulses are applied to the at least one edge word line, the magnitude of the plurality of programming pulses in each of the plurality of cycles gradually increasing to a second programming step voltage less than the first programming step voltage.

8. A controller for communicating with a memory device, the memory device including memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the string being organized row-wise, the controller being configured to: Identify the at least one edge word line; and The memory device is instructed to program memory cells of the string located in a specific row of the row and associated with the at least one edge word line from an erased state to have a changed threshold voltage distribution for one or more of the plurality of data states during the programming operation, compared with memory cells of the string not located in the specific row of the row and not associated with the at least one edge word line, the specific row of the row including a semicircular row including memory holes partially cut by shallow hole etching.

9. The controller of claim 8, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked alternately on top of each other in a stack, the strings extend vertically through the stack, the memory cells are connected in series between at least one drain-side select gate transistor located on the drain side of each of the strings and connected to one of the plurality of bit lines and at least one source-side select gate transistor located on the source side of each of the strings and connected to the source line, the at least one edge word line is vertically disposed above the plurality of other data word lines and adjacent to the at least one drain-side select gate transistor, the possible threshold voltage of each memory cell spans a threshold window, each memory cell is configured to store a plurality of bits, the plurality of data states including the erase state at a first end of the threshold window and a plurality of programming data states each corresponding to a threshold voltage higher than the threshold voltage associated with the erase state, the plurality of programming data states including a highest data state at a second end of the threshold window opposite to the first end and associated with a threshold voltage higher than the threshold voltage associated with the erase state and at least one of the plurality of programming data states.

10. The controller of claim 9, wherein the rows comprise full-circle rows and semi-circle rows, the full-circle rows and the semi-circle rows comprising memory holes forming the string, the memory holes being partially etched by the shallow holes extending vertically into the stack, and wherein the controller is further configured to: The memory device is instructed to apply each of a plurality of programming pulses, in which the magnitude value gradually increases in each of a plurality of cycles, to the plurality of other data word lines during the programming operation, until the memory cell programmed to the highest data state and associated with the full circle row reaches the first highest verification voltage level of the highest data state; During the programming operation, the memory device is instructed to apply each of the plurality of programming pulses, in which the magnitude value gradually increases in each of the plurality of cycles, to the at least one edge word line, until the memory cell programmed to be associated with the highest data state of the semicircular row and the at least one edge word line reaches a second highest verification voltage level of the highest data state, the second highest verification voltage level being higher than the first highest verification voltage level; and The memory device is instructed to disable bit line voltages applied to the bit lines of the string coupled to the full-circle row when programming the memory cell associated with the at least one edge word line to prevent programming of the memory cell associated with the full-circle row in the string, and to select bit line voltages applied to the bit lines of the string coupled to the half-circle row in the string when programming the memory cell associated with the at least one edge word line to facilitate programming of the memory cell associated with the half-circle row in the string.

11. The controller of claim 9, wherein the rows comprise full-circle rows and the semi-circle rows, the particular row in the rows being both the semi-circle row and the full-circle row, and the controller is further configured to: The memory device is instructed to apply each of a plurality of programming pulses, in increments of magnitude in each of a plurality of cycles, to the plurality of other data word lines during the programming operation, until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches the low highest verification voltage level of the highest data state; and The memory device is instructed to apply each of the plurality of programming pulses, whose magnitudes gradually increase in each of the plurality of cycles, to the at least one edge word line during the programming operation, until the memory cell programmed to be associated with the highest data state of the at least one edge word line reaches the high maximum verification voltage level of the highest data state, the high maximum verification voltage level being greater in magnitude than the low maximum verification voltage level.

12. The controller of claim 9, wherein the rows include full-circle rows and semi-circle rows, the specific row in the rows is both the semi-circle row and the full-circle row, the plurality of bits includes three bits, the total number of states of the plurality of data states is eight, the plurality of programmed data states include a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state in ascending order of the threshold voltage, the highest data state being the seventh data state, and the controller is further configured to: For a memory cell associated with the plurality of other data word lines and programmed during the programming operation to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, the memory device is instructed to apply each of a plurality of programming pulses with progressively increasing magnitudes in each of a plurality of cycles to the plurality of other data word lines during the programming operation, until the memory cell programmed to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state reaches one of the following voltage levels: a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, a low fourth voltage level of the fourth data state, a low fifth voltage level of the fifth data state, a low sixth voltage level of the sixth data state, and a low seventh voltage level of the seventh data state. For a memory cell associated with the at least one edge word line and programmed to one of the first data state, the second data state, the third data state, and the fourth data state during the programming operation, the memory device is instructed to apply each of the plurality of programming pulses, whose magnitudes gradually increase in each of the plurality of cycles, to the plurality of other data word lines during the programming operation, until the memory cell programmed to one of the first data state, the second data state, the third data state, and the fourth data state reaches one of the low first voltage level of the first data state, the low second voltage level of the second data state, the low third voltage level of the third data state, and the low fourth voltage level of the fourth data state, respectively. and For a memory cell associated with the at least one edge word line and programmed to one of the fifth, sixth, and seventh data states during the programming operation, the memory device is instructed to apply each of the plurality of programming pulses, whose magnitudes gradually increase in each of the plurality of cycles, to the plurality of other data word lines during the programming operation, until the memory cell programmed to one of the fifth, sixth, and seventh data states reaches one of the high fifth voltage level of the fifth data state, the high sixth voltage level of the sixth data state, and the high seventh voltage level of the seventh data state, respectively, wherein the high fifth voltage level is greater than the low fifth voltage level, the high sixth voltage level is greater than the low sixth voltage level, and the high seventh voltage level is greater than the low seventh voltage level.

13. The controller of claim 9, wherein the rows comprise full-circle rows and semi-circle rows, the full-circle rows and semi-circle rows comprising memory holes forming the string, the memory holes being partially cut by shallow holes etched vertically extending into the stack, the particular row of the rows being both the semi-circle row and the full-circle row, the plurality of bits comprising three bits, the total number of states of the plurality of data states being eight, the plurality of programmed data states comprising, in ascending order of magnitude of the threshold voltage, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the controller being further configured to: For a memory cell associated with the plurality of other data word lines and programmed to any of the plurality of programmed data states during the programming operation, the memory device is instructed to apply a plurality of programming pulses to the plurality of other data word lines, the magnitude of the plurality of programming pulses gradually increasing by a first programming step voltage in each of a plurality of cycles. For the memory cell associated with the at least one edge word line and programmed to the third data state, the second data state, and the first data state during the programming operation, the memory device is instructed to apply a plurality of programming pulses to the at least one edge word line, the magnitude of the plurality of programming pulses gradually increasing the first programming step voltage in each of the plurality of cycles; and For the memory cell associated with the at least one edge word line and programmed to the seventh data state, the sixth data state, the fifth data state, and the fourth data state during the programming operation, the memory device is instructed to apply the plurality of programming pulses to the at least one edge word line, the magnitude of the plurality of programming pulses in each of the plurality of cycles gradually increasing to a second programming step voltage less than the first programming step voltage.

14. A method of operating a memory device, the memory device comprising memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the string being organized row-wise, the method comprising the steps of: Identify at least one edge word line; as well as The memory cells of the string located in a specific row of the row and associated with the at least one edge word line are programmed from an erased state to have a changed threshold voltage distribution for one or more of the plurality of data states during the programming operation, compared with the memory cells of the string not located in a specific row of the row and not associated with the at least one edge word line, the specific row of the row including a semicircular row including memory holes partially cut by shallow hole etching.

15. The method of claim 14, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked alternately on top of each other in a stack, the strings extend vertically through the stack, the memory cell is connected in series between at least one drain-side selected gate transistor located on the drain side of each string and connected to one of the plurality of bit lines and at least one source-side selected gate transistor located on the source side of each string and connected to the source line, and the at least one edge word line is vertically disposed above the plurality of other data word lines and adjacent to the at least one drain-side selected gate transistor.

16. The method of claim 15, wherein for each memory cell in the memory cells, the possible threshold voltage spans a threshold window, each memory cell in the memory cells is configured to store a plurality of bits, the plurality of data states including the erase state at a first end of the threshold window and a plurality of programming data states each corresponding to a threshold voltage higher than the threshold voltage associated with the erase state, the plurality of programming data states including a highest data state at a second end of the threshold window opposite to the first end and associated with a threshold voltage higher than the threshold voltage associated with the erase state and at least one of the plurality of programming data states.

17. The method of claim 16, wherein the row comprises a full-circle row and the semi-circle row, the full-circle row and the semi-circle row comprising memory holes forming the string, the memory holes being partially cut by etching of the shallow holes extending vertically into the stack, and the method further comprising the step of: During the programming operation, each of a plurality of programming pulses, in which the magnitude value is gradually increased in each of a plurality of cycles, is applied to the plurality of other data word lines until the memory cell programmed to the highest data state and associated with the full circle row reaches the first highest verification voltage level of the highest data state; During the programming operation, each of the plurality of programming pulses, whose magnitudes are gradually increased in each of the plurality of cycles, is applied to the at least one edge word line until the memory cell programmed to be associated with the highest data state of the semicircular row and the at least one edge word line reaches a second highest verification voltage level of the highest data state, the second highest verification voltage level being higher than the first highest verification voltage level. as well as When programming a memory cell associated with at least one edge word line to prevent programming of a memory cell in the string associated with the full-circle row, bit line voltages are simultaneously disabled on the bit lines of the string coupled to the full-circle row among the plurality of bit lines; while when programming a memory cell associated with at least one edge word line to facilitate programming of a memory cell in the string associated with the semi-circle row among the plurality of bit lines, bit line voltages are selected to be applied to the bit lines of the string coupled to the semi-circle row among the plurality of bit lines.

18. The method of claim 16, wherein the rows comprise full-circle rows and the semi-circle rows, the particular row in the rows being both the semi-circle row and the full-circle row, and the method further comprises the following steps: During the programming operation, each of a plurality of programming pulses, in which the magnitude value is gradually increased in each of a plurality of cycles, is applied to the plurality of other data word lines until the memory cell programmed to the highest data state and associated with the plurality of other data word lines reaches the low highest verification voltage level of the highest data state; as well as During the programming operation, each of the plurality of programming pulses, whose magnitudes are gradually increased in each of the plurality of cycles, is applied to the at least one edge word line until the memory cell programmed to be associated with the highest data state of the at least one edge word line reaches the high maximum verification voltage level of the highest data state, which is greater in magnitude than the low maximum verification voltage level.

19. The method of claim 16, wherein the row comprises a full-circle row and the semi-circle row, the specific row in the row is both the semi-circle row and the full-circle row, the plurality of bits comprises three bits, the total number of states of the plurality of data states is eight, the plurality of programmed data states include a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state in ascending order of magnitude of the threshold voltage, the highest data state being the seventh data state, and the method further comprises the following steps: For a memory cell associated with the plurality of other data word lines and programmed during the programming operation to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, during the programming operation, each of a plurality of programming pulses in which the magnitude gradually increases in each of a plurality of cycles is applied to the plurality of other data word lines until the memory cell programmed to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state reaches one of the following voltage levels: a low first voltage level of the first data state, a low second voltage level of the second data state, a low third voltage level of the third data state, a low fourth voltage level of the fourth data state, a low fifth voltage level of the fifth data state, a low sixth voltage level of the sixth data state, and a low seventh voltage level of the seventh data state. For a memory cell associated with the at least one edge word line and programmed to one of the first data state, the second data state, the third data state, and the fourth data state during the programming operation, each of the plurality of programming pulses with progressively increasing magnitudes in each of the plurality of cycles is applied to the plurality of other data word lines during the programming operation until the memory cell programmed to one of the first data state, the second data state, the third data state, and the fourth data state reaches one of the low first voltage level of the first data state, the low second voltage level of the second data state, the low third voltage level of the third data state, and the low fourth voltage level of the fourth data state, respectively. as well as For a memory cell associated with the at least one edge word line and programmed to one of the fifth, sixth, and seventh data states during the programming operation, each of the plurality of programming pulses, whose magnitudes gradually increase in each of the plurality of cycles, is applied to the plurality of other data word lines during the programming operation until the memory cell programmed to one of the fifth, sixth, and seventh data states reaches one of the high fifth voltage level of the fifth data state, the high sixth voltage level of the sixth data state, and the high seventh voltage level of the seventh data state, respectively, wherein the high fifth voltage level is magnitude greater than the low fifth voltage level, the high sixth voltage level is magnitude greater than the low sixth voltage level, and the high seventh voltage level is magnitude greater than the low seventh voltage level.

20. The method of claim 16, wherein the row comprises a full-circle row and the semi-circle row, the specific row in the row is both the semi-circle row and the full-circle row, the plurality of bits comprises three bits, the total number of states of the plurality of data states is eight, the plurality of programmed data states include a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state in ascending order of the threshold voltage, the highest data state being the seventh data state, and the method further comprises the following steps: For a memory cell associated with the plurality of other data word lines and programmed to any of the plurality of programmed data states during the programming operation, a plurality of programming pulses are applied to the plurality of other data word lines, the magnitude of the plurality of programming pulses gradually increasing by a first programming step voltage in each of a plurality of cycles. For the memory cell associated with the at least one edge word line and programmed to the third data state, the second data state, and the first data state during the programming operation, a plurality of programming pulses are applied to the at least one edge word line, the magnitude of the plurality of programming pulses gradually increasing the first programming step voltage in each of the plurality of cycles; as well as For the memory cell associated with the at least one edge word line and programmed to the seventh data state, the sixth data state, the fifth data state, and the fourth data state during the programming operation, a plurality of programming pulses are applied to the at least one edge word line, the magnitude of the plurality of programming pulses in each of the plurality of cycles gradually increasing to a second programming step voltage less than the first programming step voltage.

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