Memory and voltage control method

Abstract

The present application provides a memory and a voltage control method, including a voltage generating circuit, wherein a first output terminal of the voltage generating circuit outputs a row control voltage, and a second output terminal of the voltage generating circuit outputs a column control voltage, wherein the row control voltage and the column control voltage are independent of each other. The row control voltage serves as a power supply voltage for a row control signal decoded by a row decoder, and the column control voltage serves as a power supply voltage for a column control signal decoded by a row decoder. When the memory is tested, the performance of a stage related to the row control signal and the performance of a stage related to the column control signal can be separated by adjusting the row control voltage and the column control voltage, that is, when adjusting the row control voltage, the performance of the stage related to the row control signal is changed, and when adjusting the column control voltage, the performance of the stage related to the column control signal is changed, so that problems can be effectively located through the performance of each stage, so that problems of the memory can be discovered in a timely manner by effectively testing the storage.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory and a voltage control method. Background Art

[0002] With the widespread use of various memories, such as dynamic random access memory (DRAM), in practical applications, in order to ensure the reliability of the product, the memory needs to be tested.

[0003] Therefore, how to effectively test the memory and discover the problems of the memory in time becomes an issue that needs to be considered. Summary of the invention

[0004] The present application provides a memory and a voltage control method, which can effectively test the memory and find problems with the memory in a timely manner.

[0005] In a first aspect, the present application provides a memory, comprising:

[0006] A voltage generating circuit, wherein a first output terminal thereof outputs a row control voltage, and a second output terminal thereof outputs a column control voltage, wherein the row control voltage and the column control voltage are independent of each other;

[0007] The row control voltage is used as a power supply voltage for the row control signal decoded by the row decoder, and the column control voltage is used as a power supply voltage for the column control signal decoded by the row decoder.

[0008] In some embodiments, the row control voltage includes a first row control voltage and a second row control voltage;

[0009] When the sense amplifier in the memory is in the deviation elimination stage, the first row control voltage is used as the power supply voltage of the row control signal decoded by the row decoder;

[0010] When the sense amplifier is in the sensing and amplifying stage, the second row control voltage is used as a power supply voltage of the row control signal decoded by the row decoder.

[0011] In some embodiments, the voltage generating circuit includes: a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit;

[0012] The first voltage generating circuit is used to generate the first row control voltage, the second voltage generating circuit is used to generate the second row control voltage, and the third voltage generating circuit is used to generate the column control voltage.

[0013] In some embodiments, the memory includes a voltage switching circuit, a first input terminal of which receives the first row control voltage, a second input terminal of which receives the second row control voltage, and a control terminal of which receives a first control signal and a second control signal;

[0014] The voltage conversion circuit is used to output the first row control voltage when the first control signal is valid, and to output the second row control voltage when the second control signal is valid.

[0015] In some embodiments, the voltage switching circuit includes: a first transistor and a second transistor;

[0016] The first end of the first transistor serves as the first input end of the voltage switching circuit, the control end of the first transistor receives the first control signal, the first end of the second transistor serves as the second input end of the voltage switching circuit, the control end of the second transistor receives the second control signal, the second end of the second transistor and the second end of the first transistor are connected to each other as the output end of the voltage switching circuit, and output the first row control voltage or the second row control voltage.

[0017] In some embodiments, when the sense amplifier is in the deviation elimination stage, the voltage switching circuit outputs the first row control voltage according to the first control signal;

[0018] When the sense amplifier is in the charge sharing stage from the preset time to the sensing amplification stage, the voltage switching circuit outputs the second row control voltage according to the second control signal.

[0019] In some embodiments, the memory further comprises: a voltage switching control circuit;

[0020] An input terminal thereof receives a third control signal, and is used to generate the first control signal when the sense amplifier is in the deviation elimination stage, and to generate the second control signal when the sense amplifier is in the charge sharing stage from a preset time to the sensing amplification stage;

[0021] The level of the third control signal is opposite to the level of the deviation elimination enable signal.

[0022] In some embodiments, the voltage switching control circuit includes: a first control circuit, a second control circuit, and a third control circuit;

[0023] The input end of the first control circuit serves as the input end of the voltage switching control circuit, and the output end of the first control circuit is connected to the first input end of the second control circuit and the first input end of the second control circuit;

[0024] The second input end of the second control circuit is connected to the output end of the third control circuit, and the second control circuit is used to generate the first control signal;

[0025] The second input end of the third control circuit is connected to the output end of the second control circuit, and the second control circuit is used to generate the second control signal.

[0026] In some embodiments, the second control circuit includes: a first NOT gate, a first NAND gate, and a second NOT gate;

[0027] The input end of the first NOT gate serves as the second input end of the second control circuit, and the output end of the first NOT gate is connected to the second input end of the first NAND gate;

[0028] The first input end of the first NAND gate serves as the first input end of the second control circuit, and the output end of the first NAND gate is connected to the input end of the second NAND gate;

[0029] The output end of the second NOT gate serves as the output end of the second control circuit.

[0030] In some embodiments, the third control circuit includes:

[0031] A first NOR gate, a third NOR gate, and a fourth NOR gate;

[0032] The first input end of the first NOR gate serves as the first input end of the third control circuit, the second input end of the first NOR gate serves as the second input end of the third control circuit, and the output end of the first NOR gate is connected to the input end of the third NOR gate;

[0033] The output end of the third NOT gate is connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate serves as the output end of the third control circuit.

[0034] In some embodiments, the source of the control transistor of the sense amplifier is connected to the sensing module of the sense amplifier, the drain of the control transistor is connected to the second power supply terminal, the second power supply terminal provides a ground voltage, and the gate of the control transistor receives a second enable signal. When the sense amplifier is in the deviation elimination stage, the first row control voltage is used as the power supply voltage of the second enable signal;

[0035] When the sense amplifier is in the sensing amplification stage, the second row control voltage serves as a power supply voltage of the second enable signal.

[0036] In some embodiments, the first row control voltage, the second row control voltage, and the column control voltage have different voltage amplitudes and different adjustment ranges of the voltage amplitudes.

[0037] In a second aspect, the present application provides a voltage control method, the method comprising:

[0038] The row decoder receives the row control voltage and the column control voltage, and outputs a row control signal whose power supply voltage is the row control voltage and a column control signal whose power supply voltage is the column control voltage;

[0039] The row control voltage and the column control voltage are independent of each other.

[0040] In some embodiments, the row decoder receives a row control voltage and a column control voltage, and outputs a row control signal whose power supply voltage is the row control voltage, specifically comprising:

[0041] The row decoder receives a first row control voltage, a second row control voltage, and a column control voltage;

[0042] When the sense amplifier in the memory is in the deviation elimination stage, the row decoder outputs a row control signal whose power supply voltage is a first row control voltage under the control of the first control signal;

[0043] When the sense amplifier is in the sensing amplification stage, the row decoder outputs a row control signal whose power supply voltage is a second row control voltage under the control of a second control signal.

[0044] In some embodiments, when the sense amplifier in the memory is in the deviation elimination stage, the row decoder outputs a row control signal whose power supply voltage is a first row control voltage under the control of the first control signal, specifically including:

[0045] The first control signal is effective in the deviation elimination phase, and the row decoder outputs a row control signal whose power supply voltage is a first row control voltage in the deviation elimination phase under the control of the first control signal;

[0046] When the sense amplifier is in the sensing amplification stage, the row decoder outputs a row control signal whose power supply voltage is a second row control voltage under the control of the second control signal, specifically comprising:

[0047] The second control signal is effective from a preset time in the charge sharing phase to the sensing and amplifying phase, and the row decoder outputs a row control signal whose power supply voltage is a second row control voltage in the sensing and amplifying phase under the control of the second control signal.

[0048] The memory and voltage control method provided by the present application include a voltage generating circuit, wherein the first output terminal of the voltage generating circuit outputs a row control voltage, and the second output terminal of the voltage generating circuit outputs a column control voltage, and the row control voltage and the column control voltage are independent of each other. The row control voltage serves as the power supply voltage of the row control signal decoded by the row decoder, and the column control voltage serves as the power supply voltage of the column control signal decoded by the row decoder. When the memory is tested, the performance of the stage related to the row control signal and the performance of the stage related to the column control signal can be separated by adjusting the row control voltage and the column control voltage, that is, when adjusting the row control voltage, the performance of the stage related to the row control signal is changed, and when adjusting the column control voltage, the performance of the stage related to the column control signal is changed, so that the problem can be effectively located through the performance of each stage, so as to effectively test the storage and find the problem of the memory in time.

[0049] Furthermore, when the sensitive amplifier is in the deviation elimination stage and the sensing amplification stage, different control voltages can be used as the power supply voltage of the row control signal, and the performance of the deviation elimination stage is changed by adjusting the first row control voltage, and the performance of the sensing amplification stage is changed by adjusting the second row control voltage, so that the problem can be further effectively located through the performance of the deviation elimination stage and the performance of the sensing amplification stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 is a circuit diagram of a sensitive amplifier;

[0052] Figure 2 It is a structural schematic diagram of an array read-write module;

[0053] Figure 3 A circuit diagram of a voltage switching circuit provided in an embodiment of the present application;

[0054] Figure 4 A circuit diagram of a voltage switching control circuit provided in an embodiment of the present application;

[0055] Figure 5 A timing diagram of a control signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims above.

[0058] The embodiment of the present application provides a memory, including a voltage generating circuit, wherein a first output terminal of the voltage generating circuit outputs a row control voltage, and a second output terminal of the voltage generating circuit outputs a column control voltage, wherein the row control voltage and the column control voltage are independent of each other. The row control voltage is used as a power supply voltage for the row control voltage decoded by a row decoder, and the column control voltage is used as a power supply voltage for the column control signal decoded by the row decoder.

[0059] The row control signal may include control signals related to activation (Active) and pre-charge (Pre-charge), and the column control signal may include control signals related to reading (Read) and writing (Write).

[0060] Figure 1 This is a circuit diagram of a sensitive amplifier. Figure 1 As shown, the sense amplifier includes a first N-type transistor M0, a second N-type transistor M1, a first P-type transistor M2, and a second P-type transistor M3. The source of the first P-type transistor M2 is connected to the source of the second P-type transistor M3, the drain of the first P-type transistor M2 is connected to the read complementary bit line SaBLb, and the gate of the first P-type transistor M2 is connected to the drain of the second P-type transistor M3. The drain of the second P-type transistor M3 is connected to the read bit line SaBLa, and the gate of the second P-type transistor M3 is connected to the drain of the first P-type transistor M2. The source of the first N-type transistor M0 is connected to the source of the second N-type transistor M1, the drain of the first N-type transistor M0 is connected to the read complementary bit line SaBLb, and the gate of the first N-type transistor M0 is connected to the bit line BLa. The drain of the second N-type transistor M1 is connected to the read bit line SaBLa, and the gate of the second N-type transistor M1 is connected to the complementary bit line BLb.

[0061] refer to Figure 1As shown, the sense amplifier further includes: a third N-type transistor M4, a fourth N-type transistor M5, a fifth N-type transistor M6, a sixth N-type transistor M7, a seventh N-type transistor M8, an eighth N-type transistor M9, a ninth N-type transistor M10 and a tenth N-type transistor M11.

[0062] The gate of the third N-type transistor M4 and the gate of the fourth N-type transistor M5 receive the isolation control signal ISO, the source of the third N-type transistor M4 is connected to the bit line BLa, the drain of the third N-type transistor M4 is connected to the drain of the second P-type transistor M3, the source of the fourth N-type transistor M5 is connected to the complementary bit line BLb, and the drain of the fourth N-type transistor M5 is connected to the drain of the first P-type transistor M2.

[0063] The gate of the fifth N-type transistor M6 and the gate of the sixth N-type transistor M7 receive the deviation elimination enable signal NcEn, the source of the fifth N-type transistor M6 is connected to the bit line BLa, the drain of the fifth N-type transistor M6 is connected to the read complementary bit line SaBLb, the source of the sixth N-type transistor M6 is connected to the complementary bit line BLb, and the drain of the sixth N-type transistor M7 is connected to the read bit line SaBLa.

[0064] The gate of the seventh N-type transistor M8 and the gate of the eighth N-type transistor M9 receive the pre-charging signal Eq, the source of the seventh N-type transistor M8 is connected to the pre-charging power supply terminal Vad2, the voltage of the pre-charging power supply terminal Vad2 is the pre-charging voltage, for example, VDD / 2, the drain of the seventh N-type transistor M8 is connected to the read bit line SaBLa, the source of the eighth N-type transistor M9 is connected to the pre-charging power supply terminal Vad2, and the drain of the eighth N-type transistor M9 is connected to the read complementary bit line SaBLb.

[0065] The source of the ninth N-type transistor M10 is connected to the first power supply terminal Vblh, which provides the power supply voltage VDD, the drain of the ninth N-type transistor M10 is connected to the source of the first P-type transistor M2 and the source of the second P-type transistor M3, and the gate of the ninth N-type transistor M10 receives the first enable signal SapEn. The drain of the tenth N-type transistor M11 is connected to the second power supply terminal, which provides the ground voltage, the source of the tenth N-type transistor M11 is connected to the source of the first N-type transistor M0 and the source of the second N-type transistor M1, and the gate of the tenth N-type transistor M11 receives the second enable signal SanEn.

[0066] The working phases of the sense amplifier may include a pre-charge phase, an offset cancellation (OC) phase, a charge sharing (CS) phase, and a sense amplifier (Sense) phase.

[0067] In the precharging stage, the seventh N-type transistor M8 and the eighth N-type transistor M9 are turned on under the control of the precharging signal Eq, and the read bit line SaBLa and the read complementary bit line SaBLb are precharged to the precharging voltage. At the same time, the fifth N-type transistor M6 and the sixth N-type transistor M7 are turned on under the control of the deviation elimination enable signal NcEn, and the read complementary bit line SaBLb is connected to the bit line BLa, and the read bit line SaBLa is connected to the complementary bit line BLb, so that the read bit line SaBLa, the read complementary bit line SaBLb, the bit line BLa and the complementary bit line BLb are all precharged to the precharging voltage.

[0068] In the deviation elimination stage, the ninth N-type transistor M10 is turned on under the control of the first enable signal SapEn, and the voltage of the source of the first P-type transistor and the source of the second P-type transistor is the power supply voltage provided by the first power supply terminal. The tenth N-type transistor M11 is turned on under the control of the second enable signal SanEn, and the voltage of the source of the first N-type transistor M0 and the source of the second N-type transistor M1 is the ground voltage provided by the second power supply terminal. The voltage of the gate of the first N-type transistor M0 is the voltage on the bit line BLa, the voltage of the source of the first N-type transistor M0 is the ground voltage, and the first N-type transistor M0 is turned on, thereby pulling down the voltage on the read complementary bit line SaBLb. Similarly, the voltage of the gate of the second N-type transistor M1 is the voltage on the complementary bit line BLb, the voltage of the source of the second N-type transistor N2 is the ground voltage, and the second N-type transistor M1 is turned on, thereby pulling down the voltage on the read bit line SaBLa. Since the threshold voltage of the first N-type transistor M0 is different from the threshold voltage of the second N-type transistor M1, the opening degrees of the first N-type transistor M0 and the second N-type transistor M1 are different, so that the voltage of the read complementary bit line SaBLb and the voltage of the read bit line SaBLa are pulled down differently. The fifth N-type transistor M6 and the sixth N-type transistor M7 remain turned on under the control of the deviation elimination enable signal NcEn, so that the gate of the first N-type transistor N1 and the read complementary bit line SaBLb are connected, and the gate of the second N-type transistor N2 and the read bit line SaBLa are connected, so that the voltage of the read complementary bit line SaBLb is compensated to the bit line BLa, and the voltage of the read bit line SaBLa is compensated to the complementary bit line BLb, and the mismatch compensation of the first N-type transistor M0 and the second N-type transistor M1 is completed.

[0069] In the charge sharing stage, the fifth N-type transistor M6 and the sixth N-type transistor M7 are turned off under the control of the deviation elimination enable signal NcEn, and the word line WL is turned on, so that the transistor T in the storage unit is turned on, and the charge stored in the storage capacitor C is shared with the charge stored in the bit line BLa, and there is a voltage difference between the bit line and the complementary bit line connected to the storage unit. At the same time, the third N-type transistor M4 and the fourth N-type transistor M5 are turned on under the control of the isolation control signal ISO, so that the bit line BLa is connected to the drain of the second P-type transistor M3, and the complementary bit line BLb is connected to the drain of the first P-type transistor M2, so that the information on the bit line BLa is transmitted to the readout bit line SaBLa inside the sense amplifier, and the information on the complementary bit line BLb is transmitted to the readout complementary bit line SaBLb inside the sense amplifier.

[0070] In the sensing and amplification stage, the ninth N-type transistor M10 is turned on under the control of the first enable signal SapEn, and the voltage of the source of the first P-type transistor M2 and the source of the second P-type transistor M3 is the power supply voltage provided by the first power supply terminal. The tenth N-type transistor M11 is turned on under the control of the second enable signal SanEn, and the voltage of the source of the first N-type transistor M0 and the source of the second N-type transistor M1 is the ground voltage provided by the second power supply terminal. The third N-type transistor M4 and the fourth N-type transistor M5 are turned on under the control of the isolation control signal ISO, the bit line BLa is connected to the drain of the second P-type transistor M3, and the complementary bit line BLb is connected to the drain of the first P-type transistor M2. If the voltage on the bit line BLa is at a high level and the voltage on the complementary bit line BLb is at a low level, the first P-type transistor M2 is turned on, so that the voltage on the read complementary bit line SaBLb is the power supply voltage, and the second N-type transistor M1 is turned on, so that the voltage on the read bit line SaBLa is the ground voltage, thereby amplifying the voltage difference between the bit line BLa and the complementary bit line BLb to correctly read the information of the storage unit.

[0071] Since the row control signal may include control signals related to activation and precharging, the row control signal may include at least one of the above-mentioned precharge signal Eq, offset cancellation enable signal NcEn, isolation control signal ISO, first enable signal SapEn and second enable signal SanEn.

[0072] Figure 2 Figure 1 is a schematic diagram of the structure of an array read-write module. Figure 2 As shown, the array read-write module includes a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6 and a seventh transistor N7.

[0073] The gate of the first transistor N1 and the gate of the second transistor N2 receive a write enable signal WrEn, the source of the first transistor N1 is connected to the global data line YIO, the drain of the first transistor N1 is connected to the local data line IO, the source of the second transistor N2 is connected to the complementary global data line YION, and the drain of the second transistor N2 is connected to the complementary local data line ION. The local data line IO is connected to the bit line BLa, and the complementary local data line ION is connected to the complementary bit line BLb.

[0074] The gate of the third transistor N3 and the gate of the fourth transistor N4 receive the read enable signal RdEn, the source of the third transistor N3 is connected to the global data line YIO, the drain of the third transistor N3 is connected to the drain of the fifth transistor N5, the source of the fourth transistor N4 is connected to the complementary global data line YION, and the drain of the fourth transistor N4 is connected to the drain of the sixth transistor N6. The gate of the fifth transistor N5 is connected to the local data line IO, the source of the fifth transistor N5 is connected to the source of the sixth transistor N6, and the gate of the sixth transistor N6 is connected to the complementary local data line ION.

[0075] The gate of the seventh transistor N7 also receives the read enable signal RdEn, the source of the seventh transistor N7 is connected to the source of the fifth transistor N5 and the source of the sixth transistor N6, the drain of the seventh transistor N7 is connected to the third power supply terminal, and the third power supply terminal provides a ground voltage.

[0076] The first transistor N1 , the second transistor N2 , the third transistor N3 , the fourth transistor N4 , the fifth transistor N5 , the sixth transistor N6 and the seventh transistor N7 may all be N-type transistors.

[0077] When performing a write operation, the write enable signal WrEn is valid, and the first transistor N1 is turned on to transmit the write data to the bit line BLa through the global data line YIO and the local data line IO, and then write the write data into the storage unit connected to the bit line BLa.

[0078] When performing a read operation, the read enable signal RdEn is valid, the third transistor N3, the fourth transistor N4 and the seventh transistor N7 are turned on, and the voltage of the source of the fifth transistor N5 and the source of the sixth transistor N6 is the ground voltage, and the ground voltage is at a low level. When the bit line BLa connected to the memory cell is at a high level, the fifth transistor N5 is turned on, so that the ground voltage is transmitted to the global data line YIO through the fifth transistor N5 and the third transistor N3, that is, when the bit line BLa is at a high level, the global data line YIO is at a low level.

[0079] Since the column control signal may include control signals related to reading and writing, the column control signal may include at least one of the above-mentioned write enable signal WrEn and read enable signal RdEn.

[0080] It should be noted that when the column control signal is transmitted from the memory channel, its voltage is the power supply voltage (VCC), for example, 1V. Due to the influence of the connection relationship and the working state, in the memory array area, the voltage of the column control signal needs to be higher than or equal to Vdleq (for example, 1.35-1.5V), and Vdleq can be the voltage used for pre-charge (EQ). Among them, Vdleq = VCC + Vth, and Vth is the threshold voltage of the transistor controlled by the column control signal.

[0081] In the embodiment of the present application, the voltage of the column control signal transmitted from the memory channel is converted and then transmitted to the storage array area. For example, the circuit for performing voltage conversion (level shift) is located in the row decoder (XDEC), and the voltage conversion circuit in the row decoder can convert the voltage of the column control signal transmitted from the memory channel into the voltage required by the column control signal in the storage array area. Here, the row decoder includes a row control signal and a column control signal.

[0082] The voltage generating circuit provided in the embodiment of the present application outputs a row control voltage and a column control voltage that are independent of each other, and uses the row control voltage as the power supply voltage of the row control signal decoded by the row decoder, and uses the column control voltage as the power supply voltage of the column control signal decoded by the row decoder. That is, the row control voltage is used as the voltage required by the row control signal in the storage array area, and the column control voltage is used as the voltage required by the column control signal in the storage array area. And because the row control signal and the column control signal each have a corresponding voltage, when the memory is tested, the performance of the stage related to the row control signal and the performance of the stage related to the column control signal can be separated by adjusting the row control voltage and the column control voltage, that is, when adjusting the row control voltage, the performance of the stage related to the row control signal is changed, and when adjusting the column control voltage, the performance of the stage related to the column control signal is changed, so that the problem can be effectively located through the performance of each stage, so as to effectively test the storage and find the problem of the memory in time. In addition, during the operation of the memory, the row control voltage is used as the power supply voltage of the row control signal, and the column control voltage is used as the control voltage of the column control signal, which can provide a more suitable voltage for the row control signal and the column control signal, thereby improving the work efficiency.

[0083] The row control voltage may include a first row control voltage and a second row control voltage. When the sensitive amplifier in the memory is in the deviation elimination stage, the first row control voltage is used as the power supply voltage of the row control signal from the row decoder. When the sensitive amplifier in the memory is in the sensing amplification stage, the second row control voltage is used as the power supply voltage of the row control signal from the row decoder. That is, different control voltages are used as the power supply voltage of the row control signal in the deviation elimination stage and the sensing amplification stage. When adjusting the first row control voltage, the performance of the deviation elimination stage can be changed. When adjusting the second row control voltage, the performance of the sensing amplification stage can be changed. Therefore, it is possible to analyze whether there is a problem with the transistor in the deviation elimination stage through the performance of the deviation elimination stage, and to analyze whether there is a problem with the transistor in the sensing amplification stage through the performance of the sensing amplification stage, so as to further effectively locate the problem. The first row control voltage, the second row control voltage and the column control voltage are independent of each other and can be adjusted independently. The voltage amplitudes of the first row control voltage, the second row control voltage and the column control voltage are different, the adjustment ranges of the voltage amplitudes are different, and the sensitivity coefficients to influencing factors such as temperature can also be different, so that more suitable voltages can be provided for the row control signal and the column control signal at different stages. The first row control voltage, the second row control voltage and the column control voltage can be adjusted according to the characteristics of a specific actual device. For example, the first row control voltage can be 1.2V to 1.5V, the second row control voltage can be 1.2V to 1.5V, and the column control voltage can be 1.2V to 1.5V.

[0084] For example, the gate of the control transistor in the sensitive amplifier receives the second enable signal, and when the sensitive amplifier is in the deviation elimination stage, the first row control voltage serves as the power supply voltage of the second enable signal, and when the sensitive amplifier is in the sensing amplification stage, the second row control voltage serves as the power supply voltage of the second enable signal. Among them, the source of the control transistor is connected to the sensing module of the sensitive amplifier, for example, the source of the first N-type transistor and the source of the second N-type transistor in the sensing module can be connected, and the drain of the control transistor is connected to the second power supply terminal, and the second power supply terminal provides a ground voltage. It should be noted that the control module in the sensitive amplifier includes an N-type control transistor and a P-type control transistor. Since the N-type control transistor has a greater impact on the circuit, the N-type transistor is called a control transistor, and the control transistor can be, for example, the tenth N-type transistor mentioned above. In the deviation elimination stage and the sensing amplification stage, the control transistor corresponding to the second enable signal needs to be turned on. In the deviation elimination stage, the first row control voltage is used as the power supply voltage of the second enable signal. In the sensing amplification stage, the second row control voltage is used as the power supply voltage of the second enable signal. When the first row control voltage is adjusted, the state of the control transistor corresponding to the second enable signal in the deviation elimination stage can be changed. When the second row control voltage is adjusted, the state of the control transistor corresponding to the second enable signal in the sensing amplification stage can be changed, so as to determine whether there is a problem with the control transistor. Of course, when the sensitive amplifier is in the deviation elimination stage, the first row control voltage can also be used as the power supply voltage of other signals in the row control signal except the second enable signal. When the sensitive amplifier is in the sensing amplification stage, the second row control voltage can also be used as the power supply voltage of other signals in the row control signal except the second enable signal.

[0085] In this embodiment, the voltage generating circuit may include a first voltage generating circuit, a second voltage generating circuit and a third voltage generating circuit. The first voltage generating circuit is used to generate a first row control voltage, the second voltage generating circuit is used to generate a second row control voltage, and the third voltage generating circuit is used to generate a third row control voltage, so that the row control signal and the column control signal can be controlled by different voltages, and the row control signals of different stages can be controlled by different voltages. It should be noted that the voltage generating circuit is located in the peripheral area, and the voltage generating circuit can be a charge pump (pump) or a voltage amplifier (AMP). For example, the first voltage generating circuit, the second voltage generating circuit and the third voltage generating circuit can be three independent charge pumps, and the three charge pumps generate the first row control voltage, the second row control voltage and the column control voltage respectively.

[0086] In some embodiments, the memory includes a voltage switching circuit, wherein a first input terminal of the voltage switching circuit receives a first row control voltage, a second input terminal of the voltage switching circuit receives a second row control voltage, and a control terminal of the voltage switching circuit receives a first control signal and a second control signal. When the first control signal is valid, the voltage switching circuit outputs the first row control voltage, and when the second control signal is valid, the voltage switching circuit outputs the second row control voltage, thereby being able to output independent first row control voltage and second row control voltage, so that the first row control voltage is used as a power supply voltage of the row control signal in the deviation elimination stage, and the second row control voltage is used as a power supply voltage of the row control signal in the sensing amplification stage.

[0087] In this embodiment, reference Figure 3 As shown, the voltage switching circuit includes a first transistor and a second transistor. The first end of the first transistor serves as the first input end of the voltage switching circuit to receive the first row control voltage, and the control end of the first transistor receives the first control signal. The first end of the second transistor serves as the second input end of the voltage switching circuit to receive the second row control voltage, and the control end of the second transistor receives the second control signal. The second end of the second transistor and the second end of the first transistor are connected to each other as the output end of the voltage switching circuit. When the first control signal is valid (for example, a high level), the first transistor is turned on and outputs the first row control voltage. When the second control signal is valid (for example, a high level), the second transistor is turned on and outputs the second row control voltage.

[0088] In this embodiment, when the sensitive amplifier is in the deviation elimination stage, the voltage switching circuit outputs the first row control voltage according to the first control signal, and when the sensitive amplifier is in the charge sharing stage from the preset time to the sensing amplification stage, the voltage switching circuit outputs the second row control voltage according to the second control signal. In this way, the first row control voltage and the second row control voltage will not be output during the preset time when the sensitive amplifier is in the charge sharing stage, thereby avoiding the generation of a DC path.

[0089] refer to Figure 5 As shown, the effective start time of the second control signal is delayed relative to the effective end time of the first control signal, that is, the effective start time of the second control signal is later than the effective end time of the first control signal. Within the preset time of the charge sharing stage, both the first control signal and the second control signal are invalid, so that the voltage switching circuit outputs the first row control voltage when the sensitive amplifier is in the deviation elimination stage, and outputs the second row control voltage when the sensitive amplifier is in the sensing amplification stage.

[0090] Continue to refer Figure 5As shown, at the beginning of the pre-charging stage, the second control signal changes from valid to invalid (high level changes to low level), and from the preset time of the pre-charging stage, the first control signal changes from invalid to valid (low level changes to high level), then the effective end time of the second control signal is earlier than the effective start time of the first control signal, and within the preset time of the pre-charging stage, both the first control signal and the second control signal are valid to avoid the generation of a DC path.

[0091] In some embodiments, the memory further includes a voltage switching control circuit, the input end of which receives a third control signal, for generating a first control signal when the sense amplifier is in the deviation elimination stage, and generating a second control signal from a preset time in the charge sharing stage to the sensing amplification stage, so that the effective time of the first control signal and the second control signal do not overlap, thereby avoiding the generation of a DC path. The level of the third control signal is opposite to the level of the deviation elimination enable signal NcEn. The voltage switching circuit can also generate the first control signal from a preset time in the pre-charging stage. The third control signal is an opposite signal to the deviation elimination enable signal, that is, the third control signal is an inverted signal of the deviation elimination enable signal.

[0092] In this embodiment, reference Figure 4 As shown, the voltage switching control circuit includes a first control circuit, a second control circuit and a third control circuit. The input end of the first control circuit serves as the input end of the voltage switching control circuit to receive the third control signal, and the output end of the first control circuit is connected to the first input end of the second control circuit and the first input end of the third control circuit. The second input end of the second control circuit is connected to the output end of the third control circuit, and the second control circuit is used to generate the first control signal. The second input end of the third control circuit is connected to the output end of the second control circuit, and the third control circuit is used to generate the second control signal. Specifically, the second control circuit generates the first control signal in the deviation elimination stage, and the third control circuit generates the second control signal from the preset time of the charge sharing stage to the sensing amplification stage.

[0093] In specific applications, refer to Figure 4 As shown, the second control circuit may include a first NOT gate, a first NAND gate, and a second NOT gate. The input end of the first NOT gate serves as the second input end of the second control circuit, receives the second control signal, and is connected to the output end of the third control circuit. The first input end of the first NAND gate serves as the first input end of the second control circuit, is connected to the output end of the first control circuit, and the second input end of the first NAND gate is connected to the output end of the first NOT gate. The input end of the second NOT gate is connected to the output end of the first NAND gate, and the output end of the second NOT gate serves as the output end of the second control circuit. The second control signal is delayed by multiple NOT gates to ensure that the time of the two paths of the second control circuit and the third control circuit are basically consistent.

[0094] The third control circuit includes a first NOR gate, a third NOR gate and a fourth NOR gate. The first input end of the first NOR gate is used as the first input end of the third control circuit, connected to the output end of the first control circuit, the second input end of the first NOR gate is used as the second input end of the third control circuit, and receives the first control signal, the output end of the first NOR gate is connected to the input end of the third NOR gate, the output end of the third NOR gate is connected to the input end of the fourth NOR gate, and the output end of the fourth NOR gate is used as the output end of the third control circuit. The first control signal is delayed by multiple NOR gates to ensure that the time of the two paths of the second control circuit and the third control circuit are basically consistent.

[0095] The first control circuit may include a fifth NOT gate, an input end of the fifth NOT gate serving as an input end of the first control circuit, receiving the third control signal, and outputting a deviation elimination enable signal.

[0096] In other embodiments, the voltage switching control circuit may also directly receive the deviation elimination enable NcEn and generate a first control signal when the sensitive amplifier is in the deviation elimination stage, and generate a second control signal from a preset time when the sensitive amplifier is in the charge sharing stage to the sensing amplification stage. At this time, the voltage switching control circuit does not have the first control circuit.

[0097] In this embodiment, the voltage switching circuit includes a second control circuit and a third control circuit, wherein the first input end of the second control circuit receives a deviation elimination enable signal, and the second input end of the second control circuit is connected to the output end of the third control circuit. The first input end of the third control circuit receives a deviation elimination enable signal, and the second input end of the third control circuit is connected to the output end of the second control circuit.

[0098] The present application provides a voltage control method, which includes:

[0099] S101 . A row decoder receives a row control voltage and a column control voltage, and outputs a row control signal whose power supply voltage is the row control voltage and a column control signal whose power supply voltage is the column control voltage.

[0100] The voltage generating circuit in the memory outputs a row control voltage and a column control voltage, and the row control voltage and the column control voltage are independent of each other. The row decoder receives the row control voltage and the column control voltage, and outputs a row control signal whose power supply voltage is the row control voltage and a column control signal whose power supply voltage is the column control voltage. The row control signal whose power supply voltage is the row control voltage, that is, the voltage of the row control signal in the storage array area is the row control voltage, and the column control signal whose power supply voltage is the column control voltage, that is, the voltage of the column control signal in the storage array area is the column control voltage. When the memory is tested, the performance of the stage related to the row control signal and the performance of the stage related to the column control signal can be separated by adjusting the row control voltage and the column control voltage, so that the problem can be effectively located through the performance of each stage, so as to effectively test the storage and find the problem of the memory in time. In addition, in the working process of the memory, the row control voltage is used as the power supply voltage of the row control signal, and the column control voltage is used as the control voltage of the column control signal, which can provide more suitable voltages for the row control signal and the column control signal, thereby improving the working efficiency.

[0101] In some embodiments, the row decoder receives a first row control voltage, a second row control voltage, and a column control voltage. When the sense amplifier in the memory is in the deviation elimination stage, the row decoder outputs a row control signal whose power supply voltage is the first row control voltage under the control of the first control signal. When the sense amplifier is in the sensing amplification stage, the row decoder outputs a row control signal whose power supply voltage is the second row control voltage under the control of the second control signal. The performance of the deviation elimination stage can be changed by adjusting the first row control voltage, and the performance of the sensing amplification stage can be changed by adjusting the second row control voltage, so as to further effectively locate the problem.

[0102] In this embodiment, the first control signal is effective in the deviation elimination stage, the second control signal is effective from the preset time in the charge sharing stage to the sensing and amplification stage, and the effective start time of the second control signal is later than the effective end time of the first control signal, that is, the effective time of the second control signal is delayed relative to the effective time of the first control signal to avoid the generation of a DC path. Then, the row decoder can output a row control signal whose power supply voltage is the first row control voltage in the deviation elimination stage under the control of the first control signal, and output a row control signal whose power supply voltage is the second row control voltage in the sensing and amplification stage under the control of the second control signal.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory, It is characterized in that include: A voltage generating circuit, wherein a first output terminal thereof outputs a row control voltage, and a second output terminal thereof outputs a column control voltage, wherein the row control voltage and the column control voltage are independent of each other; The row control voltage is used as a power supply voltage for the row control signal decoded by the row decoder, and the column control voltage is used as a power supply voltage for the column control signal decoded by the row decoder; Wherein, the row control voltage includes a first row control voltage and a second row control voltage; When the sense amplifier in the memory is in the deviation elimination stage, the first row control voltage is used as the power supply voltage of the row control signal decoded by the row decoder; When the sense amplifier is in the sensing and amplifying stage, the second row control voltage is used as a power supply voltage of the row control signal decoded by the row decoder.

2. The memory according to claim 1, It is characterized in that The voltage generating circuit comprises: a first voltage generating circuit, a second voltage generating circuit and a third voltage generating circuit; The first voltage generating circuit is used to generate the first row control voltage, the second voltage generating circuit is used to generate the second row control voltage, and the third voltage generating circuit is used to generate the column control voltage.

3. The memory according to claim 1, It is characterized in that The memory includes a voltage switching circuit, a first input terminal of which receives the first row control voltage, a second input terminal of which receives the second row control voltage, and a control terminal of which receives a first control signal and a second control signal; The voltage switching circuit is used to output the first row control voltage when the first control signal is valid, and to output the second row control voltage when the second control signal is valid.

4. The memory according to claim 3, It is characterized in that The voltage switching circuit includes: a first transistor and a second transistor; The first end of the first transistor serves as the first input end of the voltage switching circuit, the control end of the first transistor receives the first control signal, the first end of the second transistor serves as the second input end of the voltage switching circuit, the control end of the second transistor receives the second control signal, the second end of the second transistor and the second end of the first transistor are connected to each other as the output end of the voltage switching circuit, and output the first row control voltage or the second row control voltage.

5. The memory according to claim 4, It is characterized in that When the sense amplifier is in the deviation elimination stage, the voltage switching circuit outputs the first row control voltage according to the first control signal; When the sense amplifier is in the charge sharing stage from the preset time to the sensing amplification stage, the voltage switching circuit outputs the second row control voltage according to the second control signal.

6. The memory according to claim 5, It is characterized in that The memory further comprises: a voltage switching control circuit; Its input end receives a third control signal, and its output end is connected to the control end of the first transistor and the control end of the second transistor, and is used to generate the first control signal when the sense amplifier is in the deviation elimination stage, and to generate the second control signal when the sense amplifier is in the charge sharing stage from the preset time to the sensing amplification stage; The level of the third control signal is opposite to the level of the deviation elimination enable signal.

7. The memory according to claim 6, It is characterized in that The voltage switching control circuit comprises: a first control circuit, a second control circuit and a third control circuit; The input end of the first control circuit serves as the input end of the voltage switching control circuit, and the output end of the first control circuit is connected to the first input end of the second control circuit and the first input end of the second control circuit; The second input end of the second control circuit is connected to the output end of the third control circuit, and the second control circuit is used to generate the first control signal; The second input end of the third control circuit is connected to the output end of the second control circuit, and the third control circuit is used to generate the second control signal.

8. The memory according to claim 7, It is characterized in that The second control circuit includes: a first NOT gate, a first NAND gate, and a second NOT gate; The input end of the first NOT gate serves as the second input end of the second control circuit, and the output end of the first NOT gate is connected to the second input end of the first NAND gate; The first input end of the first NAND gate serves as the first input end of the second control circuit, and the output end of the first NAND gate is connected to the input end of the second NAND gate; The output end of the second NOT gate serves as the output end of the second control circuit.

9. The memory according to claim 7, It is characterized in that The third control circuit comprises: A first NOR gate, a third NOR gate, and a fourth NOR gate; The first input end of the first NOR gate serves as the first input end of the third control circuit, the second input end of the first NOR gate serves as the second input end of the third control circuit, and the output end of the first NOR gate is connected to the input end of the third NOR gate; The output end of the third NOT gate is connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate serves as the output end of the third control circuit.

10. The memory according to any one of claims 2 to 9, It is characterized in that The source of the control transistor of the sense amplifier is connected to the sensing module of the sense amplifier, the drain of the control transistor is connected to a second power supply terminal, the second power supply terminal provides a ground voltage, and the gate of the control transistor receives a second enable signal; When the sense amplifier is in the deviation elimination stage, the first row control voltage is used as the power supply voltage of the second enable signal; When the sense amplifier is in the sensing amplification stage, the second row control voltage serves as a power supply voltage of the second enable signal.

11. The memory according to any one of claims 2 to 9, It is characterized in that The first row control voltage, the second row control voltage and the column control voltage have different voltage amplitudes and different adjustment ranges of the voltage amplitudes.

12. A voltage control method, It is characterized in that The method comprises: The row decoder receives the row control voltage and the column control voltage, and outputs a row control signal whose power supply voltage is the row control voltage and a column control signal whose power supply voltage is the column control voltage; The row control voltage and the column control voltage are independent of each other; The row decoder receives a row control voltage and a column control voltage, and outputs a row control signal whose power supply voltage is the row control voltage, specifically including: The row decoder receives a first row control voltage, a second row control voltage, and a column control voltage; When the sense amplifier in the memory is in the deviation elimination stage, the row decoder outputs a row control signal whose power supply voltage is a first row control voltage under the control of the first control signal; When the sense amplifier is in the sensing amplification stage, the row decoder outputs a row control signal whose power supply voltage is a second row control voltage under the control of a second control signal.

13. The control method according to claim 12, It is characterized in that When the sense amplifier in the memory is in the deviation elimination stage, the row decoder outputs a row control signal whose power supply voltage is a first row control voltage under the control of the first control signal, specifically comprising: The first control signal is effective in the deviation elimination phase, and the row decoder outputs a row control signal whose power supply voltage is a first row control voltage in the deviation elimination phase under the control of the first control signal; When the sense amplifier is in the sensing amplification stage, the row decoder outputs a row control signal whose power supply voltage is a second row control voltage under the control of the second control signal, specifically comprising: The second control signal is effective from a preset time in the charge sharing phase to the sensing and amplifying phase, and the row decoder outputs a row control signal whose power supply voltage is a second row control voltage in the sensing and amplifying phase under the control of the second control signal.

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