Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a substrate including an active region and an isolation region; forming a gate structure, a sidewall structure, and a first dielectric layer on the substrate, the sidewall structure being located on the sidewalls of the gate structure and both being within the first dielectric layer, the sidewall structure including a sacrificial layer; forming a first conductive layer on the active region; forming a second conductive layer on the first conductive layer and forming a gate conductive layer on a part of the gate structure, with an initial first opening between the second conductive layer and the gate conductive layer; removing the sacrificial layer to form a first opening, the first opening being between the second conductive layer and the gate conductive layer, and between the first conductive layer and the gate structure; removing the gate structure and the sidewall structure on a part of the isolation region to form a groove within the first dielectric layer; forming a second dielectric layer on the substrate, the second dielectric layer closing the top of the first opening to form a first sealed cavity, and the second dielectric layer closing the groove to form an isolation structure. The performance of the formed semiconductor structure is optimized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the evolution of semiconductor technology process nodes, the continuous reduction of device size and the increase of device density have brought many problems. One of them is that leakage is likely to occur between metal gates (MG), affecting the performance of the device structure.

[0003] Therefore, the leakage problem between metal gates needs to be continuously solved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure to solve the leakage problem between metal gates.

[0005] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including adjacent active regions and isolation regions; forming a gate structure, a sidewall structure, and a first dielectric layer on the substrate, the gate structure extending from the active region to the isolation region, the sidewall structure being located on the sidewalls of the gate structure, the sidewall structure and the gate structure being located within the first dielectric layer, the sidewall structure including a sacrificial layer; forming a first conductive layer on the active region, the first conductive layer being located within the first dielectric layer on both sides of the gate structure, the sidewall structure being located between the gate structure and the first conductive layer; forming a second conductive layer on the first conductive layer, and forming a gate conductive layer on a part of the gate structure, an initial first opening being formed between the second conductive layer and the gate conductive layer, the initial first opening exposing the top surface of the sidewall structure on the active region and the isolation region; removing the sacrificial layer exposed by the initial first opening to form a first opening, the first opening being located between the second conductive layer and the gate conductive layer and between the first conductive layer and the gate structure; after removing the sacrificial layer, removing the gate structure and the sidewall structure on a part of the isolation region to form a groove within the first dielectric layer, the groove penetrating the gate structure in a direction perpendicular to the extending direction of the gate structure; forming a second dielectric layer on the substrate, the second dielectric layer closing the top of the first opening, forming a first sealed cavity between the first conductive layer and the gate structure and between the second conductive layer and the gate conductive layer, and the second dielectric layer closing the groove to form an isolation structure.

[0006] Optionally, the sidewall structure further includes: a first sidewall layer located on the sidewall surface of the gate structure and a part of the substrate surface, the sacrificial layer being located on the surface of the first sidewall layer; and a second sidewall layer located on the surface of the sacrificial layer.

[0007] Optionally, the material of the sacrificial layer is different from that of the first sidewall layer; the material of the sacrificial layer is different from that of the second sidewall layer; the materials of the first sidewall layer and the second sidewall layer are the same.

[0008] Optionally, the material of the sacrificial layer includes silicon oxide, and the materials of the first sidewall layer and the second sidewall layer include silicon nitride.

[0009] Optionally, the thickness range of the first sidewall layer is less than or equal to 3 nm; the thickness range of the second sidewall layer is less than or equal to 3 nm; the thickness range of the sacrificial layer is 2 nm to 5 nm.

[0010] Optionally, before forming the first conductive layer on the substrate, it further includes: forming a stop layer on the first dielectric layer, and the stop layer exposes the top surface of the gate structure and the top surface of the sidewall structure.

[0011] Optionally, before forming the second conductive layer on the first conductive layer and forming the gate conductive layer on a part of the gate structure, it further includes: forming a third dielectric layer on the stop layer, and the second conductive layer and the gate conductive layer are located within the third dielectric layer.

[0012] Optionally, the material of the third dielectric layer is the same as that of the sacrificial layer; when removing the sacrificial layer, it further includes: removing the third dielectric layer.

[0013] Optionally, the process of removing the third dielectric layer and the sacrificial layer includes a wet etching process.

[0014] Optionally, the method of removing the gate structure and the sidewall structure on a part of the isolation region includes: forming a mask structure on the substrate, and the mask structure exposes the gate structure on a part of the isolation region; using the mask structure as a mask, removing the sidewall structure by a first etching process; after removing the sidewall structure, removing the gate structure by a second etching process; after removing the gate structure and the sidewall structure on a part of the isolation region, removing the mask structure.

[0015] Optionally, the first etching process includes a dry etching process, and the parameters of the dry etching process include: the etching gas includes CHF3, CH2F2 or CH3F gas; the second etching process includes a dry etching process, and the parameters of the dry etching process include: the etching gas includes HBr, Cl2, SF6 or CF4.

[0016] Optionally, the process of forming the second dielectric layer includes a chemical vapor deposition process.

[0017] Optionally, the aspect ratio of the first opening is: 3:1 to 8:1.

[0018] Optionally, the aspect ratio of the groove ranges from 1:1 to 6:1.

[0019] Optionally, the isolation structure further encloses the groove to form a second sealed cavity.

[0020] Optionally, it further includes: source-drain doping regions formed in the active regions on both sides of the gate structure, and the first conductive layer is located on the source-drain doping regions.

[0021] Optionally, the substrate includes a base, a fin structure located on the base, and an isolation layer located on the base. The top plane of the isolation layer is lower than the top surface of the fin structure. The gate structure straddles the fin structure, and the source-drain doping regions are located in the fin structures on both sides of the gate structure; the isolation region is located between adjacent fin structures.

[0022] Optionally, the method for forming the gate structure, sidewall structure, and first dielectric layer includes: forming a dummy gate structure on the substrate; forming a sidewall structure on the sidewalls of the dummy gate structure; forming source-drain doping regions in the substrate on both sides of the sidewall structure; after forming the source-drain doping regions, forming a first dielectric layer on the substrate, and the source-drain doping regions, dummy gate structure, and sidewall structure are located within the first dielectric layer; removing the dummy gate structure to form a gate opening within the first dielectric layer; and forming a gate structure within the gate opening.

[0023] Optionally, the gate structure includes: a gate dielectric layer located on the sidewall surface and bottom surface of the gate opening; and a gate layer located on the gate dielectric layer.

[0024] Optionally, the gate structure further includes: a work function structure located between the gate dielectric layer and the gate layer.

[0025] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, including: a base, the base including adjacent active regions and isolation regions; a fin structure located on the active region of the base and an isolation layer located on the base, the top plane of the isolation layer being lower than the top surface of the fin structure, and the isolation region being located between adjacent fin structures; a gate structure located on the isolation layer, the gate structure straddling the fin structure; a sidewall structure located on the sidewalls of the gate structure; source-drain doping regions located in the fin structures on both sides of the gate structure, the source-drain doping regions being located at one end of the sidewall structure away from the gate structure; a first dielectric layer located on the isolation layer, the gate structure and the sidewall structure being located within the first dielectric layer, the first dielectric layer exposing the top surface of the gate structure, and the first dielectric layer having a groove that penetrates the gate structure in a direction perpendicular to the extending direction of the gate structure; a first conductive layer located on the source-drain doping regions, the first conductive layer being located within the first dielectric layer on both sides of the gate structure, and the sidewall structure being located between the gate structure and the first conductive layer;

[0026] A second conductive layer located on the first conductive layer, a gate conductive layer located on a partial gate structure, with a first opening between the second conductive layer and the gate conductive layer, and the first opening also located between the first conductive layer and the gate structure; a second dielectric layer located on the first dielectric layer, the second dielectric layer enclosing the top of the first opening to form a first sealed cavity, the first sealed cavity being located between the first conductive layer and the gate structure, as well as between the second conductive layer and the gate conductive layer, and the second dielectric layer enclosing the groove to form an isolation structure.

[0027] Optionally, the sidewall structure includes: a first sidewall layer located on the sidewall surface of the gate structure and a partial substrate surface, and a second sidewall layer located on the sidewall of the first dielectric layer, and the first opening is located between the first sidewall layer and the second sidewall layer.

[0028] Optionally, the materials of the first sidewall layer and the second sidewall layer include silicon nitride.

[0029] Optionally, the thickness range of the first sidewall layer is less than or equal to 3 nm; the thickness range of the second sidewall layer is less than or equal to 3 nm.

[0030] Optionally, it further includes: a stop layer located on the first dielectric layer, the stop layer exposing the top surface of the gate structure and the top surface of the sidewall structure; a third dielectric layer located on the stop layer, and the second conductive layer and the gate conductive layer are located within the third dielectric layer.

[0031] Optionally, the isolation structure encloses the groove to form a second sealed cavity.

[0032] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0033] In the technical solution of the present invention, by first removing the sacrificial layer, then removing the gate structure and the sidewall structure on a partial isolation region to form a groove in the first dielectric layer. Since the sacrificial layer is removed first, when removing the gate structure and the sidewall structure on the partial isolation region, the reaction by-products generated by the process of removing the gate structure and the sidewall structure on the partial isolation region are reduced, and only the gate structure and the sidewall structure on the partial isolation region need to be removed without removing the sacrificial layer anymore. Thus, the process of removing the gate structure and the sidewall structure on the partial isolation region can be simplified, and the gate structure and the sidewall structure are easily removed completely; at the same time, subsequently, a second dielectric layer is formed on the substrate, and the process of the second dielectric layer simultaneously enclosing the top of the first opening and the groove to form a first sealed cavity and an isolation structure is a single process, thereby simplifying the process flow and improving production efficiency.

[0034] Further, the isolation structure also closes the groove to form a second sealed cavity. Thus, while isolating the gate structure, the isolation structure has a relatively small parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 and Figure 2 are schematic diagrams of a semiconductor structure in an embodiment;

[0036] Figures 3 to 17 are schematic diagrams of the formation process of the semiconductor structure in an embodiment of the present invention;

[0037] Figure 18 are schematic diagrams of the formation process of the semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] As described in the background art, the leakage problem between metal gates needs to be continuously solved, and it will be analyzed and described in combination with specific embodiments.

[0039] Figure 1 and Figure 2 are schematic diagrams of a semiconductor structure in an embodiment.

[0040] Please refer to Figure 1 and Figure 2 , Figure 1 is Figure 2 a top view of the semiconductor structure with the sidewall structure omitted, Figure 2 is Figure 1Schematic cross-sectional structure diagram along the direction of section line AA1. The semiconductor structure includes: a substrate 100, the substrate 100 includes an active region I and an isolation region II located between the active regions I; a fin structure 101 located on the substrate 100; a gate structure 102 located on the substrate 100, the gate structure 102 straddles the fin structure 101; a spacer structure located on the sidewalls of the gate structure 102, the spacer structure includes a first spacer layer 107 and a second spacer layer 108 located on the sidewalls of the gate structure 102, and there is a first opening (not labeled) between the first spacer layer 107 and the second spacer layer 108; a first dielectric layer 111 located on the substrate 100, the spacer structure and the gate structure 102 are located within the first dielectric layer 111; a first conductive layer 106 within the first dielectric layer 111 on both sides of the gate structure 102, the spacer structure is located between the gate structure 102 and the first conductive layer 106; a second conductive layer 105 located on the first conductive layer 106, a gate conductive layer 104 located on the gate structure 102 in the active region I, and there is a second opening (not shown) between the second conductive layer 105 and the gate conductive layer 104; a second dielectric layer 112 located on the substrate 100, the second dielectric layer 112 closes the top of the second opening, and a first sealed cavity 110 is formed between the first spacer layer 107 and the second spacer layer 108, and between the second conductive layer 105 and the gate conductive layer 104; an isolation structure 120 located on the isolation region II, the isolation structure 120 penetrates the gate structure 102 along a direction perpendicular to the extension direction of the gate structure 102.

[0041] During the formation process of the semiconductor structure, a sacrificial layer needs to be formed between the first spacer layer 107 and the second spacer layer 108 for the spacer structure first, and then removed together when forming the second opening between the second conductive layer 105 and the gate conductive layer 104 to form the spacer structure. The material of the sacrificial layer is usually different from that of the first spacer layer 107 and the second spacer layer 108 so that the sacrificial layer can be removed completely.

[0042] The isolation structure 106 is formed after the formation of the second conductive layer 105 and the gate conductive layer 104 and before the formation of the second opening between the second conductive layer 105 and the gate conductive layer 104. When forming the isolation structure 120, it is necessary to first remove the gate structure 102, the first sidewall layer 107, the second sidewall layer 108, and the sacrificial layer on the isolation region II, form grooves in the second dielectric layer 112 and the first dielectric layer 111, and then form the isolation structure 120 in the grooves. Since the materials of the gate structure 102, the first sidewall layer 107, the second sidewall layer 108, and the sacrificial layer are different, the removal process is complex, multiple processes need to be replaced for removal, and at the same time, more reaction by-products are easily generated, so that the gate structure 102 on the isolation region II cannot be completely removed, affecting the isolation effect.

[0043] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure. By first removing the sacrificial layer, then removing the gate structure and the sidewall structure on a part of the isolation region, and forming a groove in the first dielectric layer, since the sacrificial layer is removed first, when removing the gate structure and the sidewall structure on a part of the isolation region, the reaction by-products generated by the process of removing the gate structure and the sidewall structure on a part of the isolation region are reduced, and only the gate structure and the sidewall structure on a part of the isolation region need to be removed without removing the sacrificial layer anymore. Therefore, the process of removing the gate structure and the sidewall structure on a part of the isolation region can be simplified, and the gate structure and the sidewall structure are easily removed completely; at the same time, subsequently, a second dielectric layer is formed on the substrate, and the second dielectric layer simultaneously seals the top of the first opening and the groove, and the process of forming the first sealed cavity and the isolation structure is a single process, so that the process flow can be simplified and the production efficiency can be improved.

[0044] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is made with reference to the accompanying drawings.

[0045] Figures 3 to 17 It is a schematic diagram of the process of forming a semiconductor structure in an embodiment of the present invention.

[0046] Please refer to Figure 3 and Figure 4 , Figure 3 For Figure 4 is a top view, Figure 4 For Figure 3 is a schematic cross-sectional structure diagram along the AA1 section line direction, a substrate is provided, and the substrate includes adjacent active region I and isolation region II.

[0047] In this embodiment, the substrate includes a base 200, a fin structure 201 located on the base 200, and an isolation layer 202 located on the base 200. The top plane of the isolation layer 202 is lower than the top surface of the fin structure 201.

[0048] In this embodiment, the isolation region II is located between adjacent fin structures 201.

[0049] In this embodiment, the material of the base 200 is silicon; the material of the fin structure 201 includes silicon.

[0050] In other embodiments, the material of the base includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP; the material of the fin structure includes silicon germanium.

[0051] In other embodiments, the substrate is a planar substrate.

[0052] Next, a gate structure, a sidewall structure, and a first dielectric layer are formed on the substrate. The gate structure extends from the active region I to the isolation region II. The sidewall structure is located on the sidewalls of the gate structure. The sidewall structure and the gate structure are located within the first dielectric layer. The sidewall structure includes a sacrificial layer. For the formation process of the gate structure, the sidewall structure, and the first dielectric layer, please refer to Figures 5 to 8 .

[0053] Please refer to Figure 5 and Figure 6 , Figure 5 is Figure 6 a top view of Figure 6 is Figure 5 a schematic cross-sectional structure diagram along the section line AA1 direction. A dummy gate structure 203 is formed on the substrate; a sidewall structure is formed on the sidewalls of the dummy gate structure 203.

[0054] In this embodiment, the dummy gate structure 203 straddles the fin structure 201.

[0055] In this embodiment, the sidewall structure includes: a first sidewall layer 205 located on the sidewall surface of the dummy gate structure 203 and a part of the substrate surface; a sacrificial layer 204 located on the sidewall surface of the first sidewall layer 205; and a second sidewall layer 206 located on the sidewall surface of the sacrificial layer 204.

[0056] The material of the sacrificial layer 204 is different from that of the first sidewall layer 205; the material of the sacrificial layer 204 is different from that of the second sidewall layer 206; the materials of the first sidewall layer 205 and the second sidewall layer 206 are the same.

[0057] The material of the sacrificial layer 204 is different from those of the first sidewall layer 205 and the second sidewall layer 206. Thus, when the sacrificial layer 204 is removed subsequently, the removal process causes less damage to the first sidewall layer 205 and the second sidewall layer 206, enabling a cavity to be formed between the first sidewall layer 205 and the second sidewall layer 206.

[0058] In this embodiment, the material of the sacrificial layer 204 includes silicon oxide, and the materials of the first sidewall layer 205 and the second sidewall layer 206 include silicon nitride.

[0059] In this embodiment, the thickness range of the first sidewall layer 205 is less than or equal to 3 nm; the thickness range of the second sidewall layer 206 is less than or equal to 3 nm; the thickness range of the sacrificial layer 204 is 2 nm to 5 nm.

[0060] In other embodiments, the sidewall structure includes a sacrificial layer located on the sidewall surface of the pseudo-gate structure and a partial substrate surface.

[0061] Please continue to refer to Figure 5 and Figure 6 , and source / drain doping regions 207 are formed in the substrate on one side of the sidewall structure.

[0062] In this embodiment, the source / drain doping regions 207 are located in the fin structures 201 on both sides of the pseudo-gate structure 203.

[0063] The source / drain doping regions 207 have doping ions, and the type of the doping ions is N-type or P-type; the N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0064] Please refer to Figure 7 and Figure 8 , Figure 7 is Figure 8 a top view of Figure 8 is Figure 7 a schematic cross-sectional structure diagram along the section line AA1 direction. A first dielectric layer 208 is formed on the substrate, and the source / drain doping regions 207, the pseudo-gate structure 203, and the sidewall structure are located in the first dielectric layer 208; a stop layer 211 is formed on the first dielectric layer 208, and the stop layer 211 exposes the top surface of the pseudo-gate structure 203 and the top surface of the sidewall structure.

[0065] The stop layer 211 serves as an etch stop layer when forming a second conductive layer in the second dielectric layer subsequently. The material of the first dielectric layer 208 is different from that of the stop layer 211.

[0066] The material of the first dielectric layer 208 includes a dielectric material, and the dielectric material includes one or a combination of more than one of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. The material of the stop layer 211 includes a dielectric material, and the dielectric material includes one or a combination of more than one of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.

[0067] In this embodiment, the material of the first dielectric layer 208 includes silicon oxide; the material of the stop layer 211 includes silicon nitride.

[0068] Please continue to refer to Figure 7 and Figure 8 , remove the dummy gate structure 203, form a gate opening (not shown) in the first dielectric layer 208; form a gate structure 209 in the gate opening.

[0069] The gate structure 209 includes: a gate dielectric layer (not shown) located on the sidewall surface and the bottom surface of the gate opening; a gate layer (not shown) located on the gate dielectric layer.

[0070] In this embodiment, the gate structure 209 further includes: a work function structure located between the gate dielectric layer and the gate layer.

[0071] The material of the gate dielectric layer includes a high-k material, the dielectric constant of the high-k material is greater than 3.9, and the high-k material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function structure includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0072] Please refer to Figure 9 and Figure 10 , Figure 9 is Figure 10 a top view of Figure 10 is Figure 9 a schematic cross-sectional structure diagram along the AA1 section line direction. A first conductive layer 210 is formed on the active region I. The first conductive layer 210 is located in the first dielectric layer 208 on both sides of the gate structure 209. The stop layer 211 exposes the top surface of the first conductive layer 210. The spacer structure is located between the gate structure 209 and the first conductive layer 210.

[0073] In this embodiment, the first conductive layer 210 is located on the source-drain doped region 207.

[0074] The material of the first conductive layer 210 includes metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0075] Please continue to refer to Figure 9 and Figure 10 , and a third dielectric layer 212 is formed on the stop layer 211.

[0076] The material of the third dielectric layer 212 is the same as that of the sacrificial layer 204. Thus, the third dielectric layer 212 and the sacrificial layer 204 can be removed simultaneously later.

[0077] In this embodiment, the material of the third dielectric layer 212 includes silicon oxide.

[0078] Please continue to refer to Figure 9 and Figure 10 , a second conductive layer 213 is formed on the first conductive layer 210, and a gate conductive layer 214 is formed on a part of the gate structure 209. The second conductive layer 213 and the gate conductive layer 214 are located within the third dielectric layer 212.

[0079] The material of the second conductive layer 213 includes metal or metal nitride, and the material of the gate conductive layer 214 includes metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0080] Please refer to Figure 11 , Figure 12 and Figure 13 , Figure 11 is Figure 12 and Figure 13 's top view, Figure 12 is Figure 11 's cross-sectional structure schematic diagram along the section line AA1 direction, Figure 13 is Figure 11 's cross-sectional structure schematic diagram along the section line BB1 direction. The third dielectric layer 212 is removed, and an initial first opening (not shown) is formed between the second conductive layer 213 and the gate conductive layer 214. The initial first opening exposes the top surface of the sidewall structure on the active region and the isolation region; the sacrificial layer 204 exposed by the initial first opening is removed to form a first opening 215. The first opening 215 is located between the second conductive layer 213 and the gate conductive layer 214, and between the first conductive layer 210 and the gate structure 209.

[0081] In this embodiment, the first opening 215 is located between the second conductive layer 213 and the gate conductive layer 214, and between the first sidewall layer 205 and the second sidewall layer 206 on the active region I and the isolation region II.

[0082] In this embodiment, the process of removing the third dielectric layer 212 and the sacrificial layer 204 includes a wet etching process. The wet etching process can cleanly remove the sacrificial layer 204 and the third dielectric layer 212 while causing less damage to the second conductive layer 213, the gate conductive layer 214, the first sidewall layer 205, and the second sidewall layer 206.

[0083] In this embodiment, the aspect ratio of the first opening 215 is 3:1 to 8:1.

[0084] Please refer to Figure 14 and Figure 15 , Figure 14 is Figure 15 a top view of Figure 15 is Figure 14 a schematic cross-sectional structure diagram along the section line BB1. After removing the sacrificial layer 204, the gate structure 209 and the sidewall structure on a part of the isolation region II are removed, and a groove 216 is formed in the first dielectric layer 208. The groove 216 penetrates through the gate structure 209 in a direction perpendicular to the extending direction of the gate structure 209.

[0085] In this embodiment, the aspect ratio range of the groove 216 is 1:1 to 6:1.

[0086] The method of removing the gate structure 209 and the sidewall structure on a part of the isolation region II includes: forming a mask structure (not shown) on the substrate, and the mask structure exposes the gate structure 209 on a part of the isolation region II; using the mask structure as a mask, removing the sidewall structure by a first etching process; after removing the sidewall structure, removing the gate structure 209 by a second etching process; after removing the gate structure 209 and the sidewall structure on a part of the isolation region II, removing the mask structure.

[0087] In this embodiment, the first etching process includes a dry etching process, and the parameters of the dry etching process include: the etching gas includes CHF3, CH2F2, or CH3F gas; the second etching process includes a dry etching process, and the parameters of the dry etching process include: the etching gas includes HBr, Cl2, SF6, or CF4.

[0088] Since the sacrificial layer 204 is removed first, when removing the gate structure 209 and the sidewall structure on the partial isolation region II, the reaction by-products generated by the process of removing the gate structure 209 and the sidewall structure on the partial isolation region II are reduced, and only the gate structure 209 and the sidewall structure on the partial isolation region II need to be removed without removing the sacrificial layer 204 anymore. Thus, the process of removing the gate structure 209 and the sidewall structure on the partial isolation region II can be simplified, and the gate structure 209 and the sidewall structure are easily removed completely, resulting in a better isolation effect of the isolation structure formed in the groove 216 subsequently, and reducing the short-circuit situation of the gate structure 209 on the adjacent active region I.

[0089] Please refer to Figure 16 and Figure 17 , Figure 16 For a schematic diagram based on Figure 12 On the basis of Figure 17 For a schematic diagram based on Figure 15 On the basis of, a second dielectric layer 217 is formed on the substrate. The second dielectric layer 217 closes the top of the first opening 215, and a first sealed cavity 218 is formed between the first conductive layer 210 and the gate structure 209, and between the second conductive layer 213 and the gate conductive layer 214. The second dielectric layer 217 closes the groove 216 to form an isolation structure 219.

[0090] In this embodiment, the process of forming the second dielectric layer 217 includes a chemical vapor deposition process. The chemical vapor deposition process has a relatively fast deposition rate, so it is easy to close the top of the first opening 215.

[0091] In this embodiment, the first sealed cavity 218 is located between the first conductive layer 210 and the gate structure 209, and between the first sidewall layer 205 and the second sidewall layer 206.

[0092] The first sealed cavity 218 has a relatively small dielectric constant, so that the parasitic capacitance between the first conductive layer 210 and the gate structure 209, and between the second conductive layer 213 and the gate conductive layer 214 is reduced, thereby improving the reaction speed of the device.

[0093] Since the sacrificial layer 204 is removed first, then the gate structure 209 and the sidewall structure on the partial isolation region II are removed to form the groove 216, and then the second dielectric layer 217 is formed on the substrate. The process of the second dielectric layer 217 closing the top of the first opening 215 and the groove 216 simultaneously to form the first sealed cavity 218 and the isolation structure 219 is a single process, so that the process flow can be simplified and the production efficiency can be improved.

[0094] In another embodiment, the isolation structure also closes the groove to form a second sealed cavity.

[0095] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to Figure 16 and Figure 17 , including:

[0096] A substrate 200, the substrate 200 includes adjacent active region I and isolation region II;

[0097] A fin structure 201 located on the active region I of the substrate 200 and an isolation layer 202 located on the substrate 200. The top plane of the isolation layer 202 is lower than the top surface of the fin structure 201. The isolation region II is located between adjacent fin structures 201;

[0098] A gate structure 209 located on the isolation layer 202, the gate structure 209 straddles the fin structure 201;

[0099] A sidewall structure located on the sidewalls of the gate structure 209;

[0100] Source / drain doping regions 207 located in the fin structures 201 on both sides of the gate structure 209. The source / drain doping regions 207 are located at one end of the sidewall structure away from the gate structure 209;

[0101] A first dielectric layer 208 located on the isolation layer 202. The gate structure 209 and the sidewall structure are located in the first dielectric layer 208. The first dielectric layer 208 exposes the top surface of the gate structure 209. The first dielectric layer 208 has a groove 216, and the groove 216 penetrates the gate structure 209 in a direction perpendicular to the extension direction of the gate structure 209;

[0102] A first conductive layer 210 located on the source / drain doping regions 207. The first conductive layer 210 is located in the first dielectric layer 208 on both sides of the gate structure 209. The sidewall structure is located between the gate structure 209 and the first conductive layer 210;

[0103] A second conductive layer 213 located on the first conductive layer 210 and a gate conductive layer 214 located on a part of the gate structure 209. There is a first opening 215 between the second conductive layer 213 and the gate conductive layer 214. The first opening 215 is also located between the first conductive layer 210 and the gate structure 209;

[0104] A second dielectric layer 217 located on the first dielectric layer 208. The second dielectric layer 217 closes the top of the first opening 215 to form a first sealed cavity 218. The first sealed cavity 218 is located between the first conductive layer 210 and the gate structure 209, and between the second conductive layer 213 and the gate conductive layer 214. The second dielectric layer 217 closes the groove 216 to form an isolation structure 219.

[0105] In this embodiment, the sidewall structure includes: a first sidewall layer 205 located on the sidewall surface of the gate structure 209 and part of the substrate surface, and a second sidewall layer 206 located on the sidewall of the first dielectric layer 208. The first opening 215 is located between the first sidewall layer 205 and the second sidewall layer 206.

[0106] In this embodiment, the materials of the first sidewall layer 205 and the second sidewall layer 206 include silicon nitride.

[0107] In this embodiment, the thickness range of the first sidewall layer 205 is less than or equal to 3 nm; the thickness range of the second sidewall layer 206 is less than or equal to 3 nm.

[0108] In this embodiment, it further includes: a stop layer 211 located on the first dielectric layer 208, the stop layer 211 exposing the top surface of the gate structure 209 and the top surface of the sidewall structure; a third dielectric layer 212 located on the stop layer 211, the second conductive layer 213 and the gate conductive layer 214 being located within the third dielectric layer 212.

[0109] In other embodiments, the isolation structure closes the groove to form a second sealed cavity.

[0110] Figure 18 It is a schematic diagram of a semiconductor structure in another embodiment of the present invention.

[0111] Please refer to Figure 18 , Figure 18 For the structure schematic diagram based on Figure 15 , a second dielectric layer is formed on the substrate, the second dielectric layer closing the top of the first opening 215, a first sealed cavity being formed between the first conductive layer 210 and the gate structure 209 and between the second conductive layer 213 and the gate conductive layer 214, and the second dielectric layer closing the groove 216 to form an isolation structure 317.

[0112] In this embodiment, the isolation structure also closes the groove 216 to form a second sealed cavity 319.

[0113] Thus, while the isolation structure 317 isolates the gate structure 209, it has a relatively small parasitic capacitance.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including adjacent active regions and isolation regions; Forming a gate structure, a sidewall structure, and a first dielectric layer on the substrate, the gate structure extending from the active region to the isolation region, the sidewall structure being located on the sidewalls of the gate structure, the sidewall structure and the gate structure being within the first dielectric layer, and the sidewall structure including a sacrificial layer; Forming a first conductive layer on the active region, the first conductive layer being within the first dielectric layer on both sides of the gate structure, and the sidewall structure being located between the gate structure and the first conductive layer; Forming a second conductive layer on the first conductive layer and forming a gate conductive layer on a part of the gate structure, an initial first opening being formed between the second conductive layer and the gate conductive layer, and the initial first opening exposing the top surface of the sidewall structure on the active region and the isolation region; Removing the sacrificial layer exposed by the initial first opening to form a first opening, the first opening being located between the second conductive layer and the gate conductive layer and between the first conductive layer and the gate structure; After removing the sacrificial layer, removing the gate structure and the sidewall structure on a part of the isolation region, and forming a groove in the first dielectric layer, the groove penetrating the gate structure in a direction perpendicular to the extending direction of the gate structure; Forming a second dielectric layer on the substrate, the second dielectric layer closing the top of the first opening, forming a first sealed cavity between the first conductive layer and the gate structure and between the second conductive layer and the gate conductive layer, and the second dielectric layer closing the groove to form an isolation structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sidewall structure further includes: a first sidewall layer located on the sidewall surface of the gate structure and a part of the substrate surface, the sacrificial layer being located on the surface of the first sidewall layer; and a second sidewall layer located on the surface of the sacrificial layer.

3. The method for forming a semiconductor structure according to claim 2, wherein, The material of the sacrificial layer is different from the material of the first sidewall layer; the material of the sacrificial layer is different from the material of the second sidewall layer; the materials of the first sidewall layer and the second sidewall layer are the same.

4. The method for forming a semiconductor structure according to claim 3, wherein, The material of the sacrificial layer includes silicon oxide, and the materials of the first sidewall layer and the second sidewall layer include silicon nitride.

5. The method for forming a semiconductor structure according to claim 2, wherein, The thickness range of the first sidewall layer is less than or equal to 3 nm; the thickness range of the second sidewall layer is less than or equal to 3 nm; the thickness range of the sacrificial layer is 2 nm to 5 nm.

6. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the first conductive layer on the substrate, further including: forming a stop layer on the first dielectric layer, the stop layer exposing the top surface of the gate structure and the top surface of the sidewall structure.

7. The method for forming a semiconductor structure according to claim 6, wherein, Before forming the second conductive layer on the first conductive layer and forming the gate conductive layer on a part of the gate structure, further including: forming a third dielectric layer on the stop layer, the second conductive layer and the gate conductive layer being within the third dielectric layer.

8. The method for forming a semiconductor structure according to claim 7, wherein, The material of the third dielectric layer is the same as the material of the sacrificial layer; when removing the sacrificial layer, further including: removing the third dielectric layer.

9. The method for forming a semiconductor structure according to claim 8, wherein, The process of removing the third dielectric layer and the sacrificial layer includes a wet etching process.

10. The method for forming a semiconductor structure according to claim 1, wherein A method for removing a gate structure and a sidewall structure on a partial isolation region includes: forming a mask structure on a substrate, where the mask structure exposes the gate structure on the partial isolation region; using the mask structure as a mask, removing the sidewall structure by a first etching process; after removing the sidewall structure, removing the gate structure by a second etching process; after removing the gate structure and the sidewall structure on the partial isolation region, removing the mask structure.

11. The method for forming a semiconductor structure according to claim 10, wherein The first etching process includes a dry etching process, and the parameters of the dry etching process include: the etching gas includes CHF3, CH2F2 or CH3F gas; the second etching process includes a dry etching process, and the parameters of the dry etching process include: the etching gas includes HBr, Cl2, SF6 or CF4.

12. The method for forming a semiconductor structure according to claim 1, wherein, The process for forming the second dielectric layer includes a chemical vapor deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein, The aspect ratio of the first opening is: 3:1 to 8:

1.

14. The method for forming a semiconductor structure according to claim 1, wherein The aspect ratio range of the groove is: 1:1 to 6:

1.

15. The method for forming a semiconductor structure according to claim 14, wherein The isolation structure also closes the groove to form a second sealed cavity.

16. The method for forming a semiconductor structure according to claim 1, wherein, Further included is: Forming source-drain doping regions in the active regions on both sides of the gate structure, and the first conductive layer is located on the source-drain doping regions.

17. The method for forming a semiconductor structure according to claim 16, wherein, The substrate includes a base, a fin structure located on the base, and an isolation layer located on the base. The top plane of the isolation layer is lower than the top surface of the fin structure. The gate structure straddles the fin structure, and the source-drain doping regions are located in the fin structures on both sides of the gate structure; the isolation region is located between adjacent fin structures.

18. The method for forming a semiconductor structure as described in claim 16, wherein, The method for forming the gate structure, the sidewall structure and the first dielectric layer includes: forming a dummy gate structure on a substrate; forming a sidewall structure on the sidewalls of the dummy gate structure; forming source-drain doping regions in the substrate on both sides of the sidewall structure; after forming the source-drain doping regions, forming a first dielectric layer on the substrate, where the source-drain doping regions, the dummy gate structure and the sidewall structure are located in the first dielectric layer; removing the dummy gate structure to form a gate opening in the first dielectric layer; forming a gate structure in the gate opening.

19. The method for forming a semiconductor structure according to claim 18, wherein, The gate structure includes: a gate dielectric layer located on the sidewall surface and the bottom surface of the gate opening; a gate layer located on the gate dielectric layer.

20. The method for forming a semiconductor structure according to claim 19, wherein, The gate structure further includes: a work function structure located between the gate dielectric layer and the gate layer.

21. A semiconductor structure, characterized in that, Included is: A base, where the base includes adjacent active regions and isolation regions; A fin structure located on the active region of the base and an isolation layer located on the base. The top plane of the isolation layer is lower than the top surface of the fin structure, and the isolation region is located between adjacent fin structures; A gate structure located on the isolation layer, where the gate structure straddles the fin structure; A sidewall structure located on the sidewalls of the gate structure; Source-drain doping regions located in the fin structures on both sides of the gate structure, and the source-drain doping regions are located at the end of the sidewall structure away from the gate structure; A first dielectric layer located on the isolation layer, where the gate structure and the sidewall structure are located in the first dielectric layer. The first dielectric layer exposes the top surface of the gate structure, and the first dielectric layer has a groove, and the groove penetrates the gate structure in a direction perpendicular to the extension direction of the gate structure; A first conductive layer located on the source-drain doping region, the first conductive layer being within a first dielectric layer on both sides of the gate structure, and the sidewall structure being located between the gate structure and the first conductive layer; A second conductive layer located on the first conductive layer, and a gate conductive layer located on a part of the gate structure, there being a first opening between the second conductive layer and the gate conductive layer, and the first opening also being located between the first conductive layer and the gate structure; A second dielectric layer located on the first dielectric layer, the second dielectric layer enclosing the top of the first opening to form a first sealed cavity, the first sealed cavity being located between the first conductive layer and the gate structure, and between the second conductive layer and the gate conductive layer, and the second dielectric layer enclosing the groove to form an isolation structure.

22. The semiconductor structure according to claim 21, wherein, The sidewall structure includes: a first sidewall layer located on the sidewall surface of the gate structure and a part of the substrate surface, and a second sidewall layer located on the sidewall of the first dielectric layer, and the first opening being located between the first sidewall layer and the second sidewall layer.

23. The semiconductor structure according to claim 22, wherein, The materials of the first sidewall layer and the second sidewall layer include silicon nitride.

24. The semiconductor structure according to claim 22, wherein The thickness range of the first sidewall layer is less than or equal to 3 nm; the thickness range of the second sidewall layer is less than or equal to 3 nm.

25. The semiconductor structure as claimed in claim 21, wherein, Further included is: A stop layer located on the first dielectric layer, the stop layer exposing the top surface of the gate structure and the top surface of the sidewall structure; A third dielectric layer located on the stop layer, the second conductive layer and the gate conductive layer being within the third dielectric layer.

26. The semiconductor structure according to claim 21, wherein The isolation structure encloses the groove to form a second sealed cavity.

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