Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate; a plurality of protrusions protruding from the substrate; an isolation layer located on the protrusions and comprising a first region and second regions located on both sides of the first region along the extension direction of the protrusions; a filling layer located on the first region of the isolation layer; a channel structure layer located above the filling layer and spaced apart from the filling layer, the channel structure layer comprising one or more channel layers arranged in sequence and spaced apart, the channel layers being stacked in a direction perpendicular to the surface of the substrate; an insulating layer located on the substrate and surrounding the protrusions, the isolation layer and the filling layer, the insulating layer covering the side walls of the isolation layer and the filling layer and exposing the channel structure layer; and a gate structure located on the insulating layer and spanning the channel structure layer and surrounding the channel layers, the gate structure also being located on the top of the filling layer and spanning the filling layer. The embodiments of the present application can reduce the leakage current of the device and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, GAA transistors have stronger control over the channel and can better suppress short-channel effects.

[0004] However, the performance of fully enclosed gate transistors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the leakage current of the device and improves the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a plurality of protrusions protruding from the substrate; an isolation layer located on the protrusions along the extending direction of the protrusions, the isolation layer including a first region and second regions located on both sides of the first region; a filling layer located on the first region of the isolation layer; a channel structure layer located above the filling layer and suspended from the filling layer at a distance, the channel structure layer including one or more channel layers arranged sequentially at intervals, the channel layers being stacked in a direction perpendicular to the surface of the substrate; an insulating layer located on the substrate and surrounding the protrusions, the isolation layer, and the filling layer, the insulating layer covering the sidewalls of the isolation layer and the filling layer and exposing the channel structure layer; a gate structure located on the insulating layer and spanning and surrounding the channel structure layer, the gate structure also being located on top of the filling layer and spanning the filling layer; and source / drain doped layers located on the filling layers on both sides of the gate structure and contacting the ends of each channel layer in the channel structure layer along the extending direction.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of protrusions protruding from the substrate, wherein a sacrificial layer, an etch stop layer and a stacked structure are sequentially formed on the protrusions, the etch stop layer being made of a semiconductor material, and the stacked structure including one or more channel stacks stacked sequentially from bottom to top, each channel stack including a placeholder layer and a channel layer located on the placeholder layer; forming an insulating layer surrounding the protrusions, the sacrificial layer and the etch stop layer on the substrate; forming a dummy gate structure across the stacked structure on the insulating layer; forming a groove in the stacked structure on both sides of the dummy gate structure, the bottom of the groove exposing the etch stop layer; forming a protective sidewall on the sidewall of the groove, the protective sidewall covering a portion of the top surface of the etch stop layer; removing the etch stop layer exposed by the protective sidewall, exposing the top surface of the sacrificial layer; removing the sacrificial layer, forming a channel between the etch stop layer and the protrusions and below the grooves, the channel being formed by the insulating layer, the protrusions and the stacked structure. An etch stop layer is formed; an isolation layer is formed within the channel; the protective sidewalls on the sidewalls of the channel layer are removed, exposing the sidewalls of the channel layer and the etch stop layers on both sides of the dummy gate structure; source / drain doped layers are formed on the etch stop layers on both sides of the dummy gate structure, the source / drain doped layers contacting the ends of the channel layer along the extension direction; the etch stop layer is removed to form a trench, the trench being surrounded by the isolation layer, the insulating layer, the stacked structure, and the source / drain doped layers on both sides of the stacked structure. The structure and the source / drain doped layers are suspended above the isolation layer; a filling layer is formed in the trench; after forming the filling layer, the dummy gate structure is removed to form a gate opening, exposing the stacked structure; through the gate opening, the occupant layer is removed to form a through trench, which is surrounded by adjacent channel layers or by the channel layers and the filling layer; a gate structure is filled in the gate opening and the through trench, the gate structure surrounding the channel layer, and the gate structure is also located on top of the filling layer and spans the filling layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention includes an isolation layer and a filling layer sequentially disposed on the protrusion. A channel structure layer is suspended above the filling layer at intervals. The gate structure is located on top of the filling layer and spans the filling layer. The source / drain doped layers are located on the filling layers on both sides of the gate structure. Accordingly, the isolation layer and the filling layer achieve isolation between the source / drain doped layers and the protrusion, as well as isolation between the gate structure and the protrusion. This helps prevent the source / drain doped layers, the gate structure, and the protrusion below them from forming parasitic devices, thereby helping to eliminate leakage channels generated in the protrusion, reducing the leakage current of the device, and improving the performance of the semiconductor structure.

[0010] In the semiconductor structure formation method provided by this invention, the sacrificial layer is removed to form a channel; an isolation layer is formed within the channel; after forming the source / drain doped layer, the etch stop layer is removed to form a trench; and a filling layer is formed within the trench. Therefore, after forming the gate structure, the isolation layer and the filling layer achieve isolation between the source / drain doped layer and the protrusion, as well as isolation between the gate structure and the protrusion. This helps prevent the source / drain doped layer and the gate structure and the protrusion below them from forming parasitic devices, thereby eliminating leakage channels generated within the protrusion and reducing device leakage current. Furthermore, after forming the trench, a protective sidewall is formed on the sidewall of the trench, covering part of the top surface of the etch stop layer. After forming the channel, the sacrificial layer is removed to form a trench. The protective sidewalls on the sidewalls of the channel layer expose etch stop layers located on both sides of the dummy gate structure. The etch stop layers are made of semiconductor materials. The process of forming the source / drain doped layer typically includes epitaxial processes. In the step of forming the source / drain doped layer, in addition to using the channel layer as the growth basis for the epitaxial process, the etch stop layers can also be used as the growth basis to form the source / drain doped layer, increasing the process platform for the epitaxial process and thus improving the epitaxial quality of the source / drain doped layer. In summary, the embodiments of the present invention improve the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 7 to 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 9 to 31 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 6 This is a schematic diagram of the structural steps involved in forming a semiconductor structure. Specifically, Figures 1 to 6 A schematic diagram of the cross-sectional structure along the extension direction of the channel layer is shown.

[0015] refer to Figure 1 A substrate is provided, including a substrate (not shown) and a plurality of protrusions 1 protruding from the substrate 1, wherein a stacked structure 6 is formed on the protrusions 1, the stacked structure 6 including one or more channel stacks 2, the channel stacks 2 including a placeholder layer 12 and a channel layer 3 located on the placeholder layer 12.

[0016] Continue to refer to Figure 1 An insulating layer (not shown) is formed on the substrate surrounding the protrusion 1, the insulating layer exposing the stacked structure 6.

[0017] Continue to refer to Figure 1 A pseudo-gate structure 5 is formed on the insulating layer, spanning the stacked structure 6.

[0018] refer to Figure 2 A gate sidewall 4 is formed on the sidewalls on both sides of the pseudo-gate structure 5; a groove 8 is formed in the stacked structure 6 on both sides of the gate sidewall 4.

[0019] refer to Figure 3 Along the extension direction of the channel layer 3, a portion of the thickness of the occupant layer 12 exposed on the sidewall of the groove 8 is removed to form an inner groove (not shown); the inner sidewall 14 is filled into the inner groove (not shown).

[0020] refer to Figure 4 A source / drain doped layer 15 is formed in the groove 8, and the source / drain doped layer 15 is located on the protrusion 1.

[0021] Continue to refer to Figure 4 An interlayer dielectric layer 19 is formed on the insulating layers on both sides of the pseudo-gate structure 5, covering the source / drain doped layer 15.

[0022] refer to Figure 5 Remove the pseudo-gate structure 5 to form a gate opening 16, exposing the stacked structure and the insulating layer; remove the occupant layer 12 through the gate opening 16 to form a through slot 17, which is surrounded by adjacent channel layers or by the channel layer 3 and the protrusion 1.

[0023] refer to Figure 6A gate structure 18 is filled in the gate opening 16 and the through groove 17, and the gate structure 18 surrounds the channel layer 3.

[0024] The semiconductor structure is a fully enclosed gate transistor, wherein the source / drain doped layer 15 and the protrusion 1 are in contact with each other, and the gate structure 18 and the protrusion 1 are in contact with each other. The source / drain doped layer 15, the gate structure 18 and the protrusion 1 below them are prone to forming parasitic devices, which in turn can easily generate leakage channels in the protrusion 1, resulting in excessive leakage current in the semiconductor structure and poor device performance.

[0025] One method to reduce leakage current is to provide an isolation layer between the bump and the source / drain doped layer, and between the bump and the gate structure, thereby achieving isolation between the source / drain doped layer and the bump, and between the gate structure and the bump. However, in this method, during the formation of the source / drain doped layer, because the isolation layer is provided on the bump, the epitaxial growth base can only be used as the growth base for the epitaxial process at the end of the channel layer along the extension direction. This results in a small epitaxial base area for forming the source / drain doped layer, insufficient process platform for epitaxial processing, and consequently reduced formation quality of the source / drain doped layer. In particular, the small cross-sectional area of ​​the channel layer easily further reduces the formation quality of the source / drain doped layer, leading to poor performance of the semiconductor structure.

[0026] To address the aforementioned technical problem, this invention provides a semiconductor structure in which an isolation layer and a filling layer are sequentially disposed on the protrusion. A channel structure layer is suspended above the filling layer at intervals. The gate structure is located on top of the filling layer and spans the filling layer. The source / drain doped layers are located on the filling layers on both sides of the gate structure. Accordingly, the isolation layer and the filling layer achieve isolation between the source / drain doped layers and the protrusion, as well as isolation between the gate structure and the protrusion. This helps prevent the formation of parasitic devices in the source / drain doped layers, the gate structure, and the protrusion below them, thereby eliminating leakage channels generated in the protrusion, reducing device leakage current, and improving the performance of the semiconductor structure.

[0027] To address the aforementioned technical problem, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: removing the sacrificial layer to form a channel; forming an isolation layer within the channel; after forming the source / drain doped layer, removing the etch stop layer to form a trench; and forming a filling layer within the trench. Therefore, after forming the gate structure, the isolation layer and the filling layer achieve isolation between the source / drain doped layer and the protrusion, as well as isolation between the gate structure and the protrusion. This helps prevent the source / drain doped layer and the gate structure and the protrusion below them from forming parasitic devices, thereby eliminating leakage channels generated within the protrusion and reducing device leakage current. Furthermore, after forming the trench, a protective sidewall is formed on the sidewall of the trench, the protective sidewall covering part of the top surface of the etch stop layer. After forming the channel, the sacrificial layer is removed to form a trench. The protective sidewalls on the sidewalls of the channel layer expose etch stop layers located on both sides of the dummy gate structure. The etch stop layers are made of semiconductor materials. The process of forming the source / drain doped layer typically includes epitaxial processes. In the step of forming the source / drain doped layer, in addition to using the channel layer as the growth basis for the epitaxial process, the etch stop layers can also be used as the growth basis to form the source / drain doped layer, increasing the process platform during the epitaxial process and thus improving the epitaxial quality of the source / drain doped layer. In summary, the embodiments of the present invention improve the performance of the semiconductor structure.

[0028] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] refer to Figures 7 to 8 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention. Figure 7 It is a 3D image. Figure 8 for Figure 7 Cross-sectional view along the XX direction.

[0030] like Figure 7 and Figure 8As shown, the semiconductor structure includes: a substrate 800; a plurality of protrusions 810 protruding from the substrate 800; an isolation layer 820 located on the protrusions 810 and extending along the extension direction of the protrusions 810, the isolation layer 820 including a first region I and second regions II located on both sides of the first region I; a fill layer 900 located on the first region I of the isolation layer 820; a channel structure layer 850 located above the fill layer 900 and suspended from the fill layer 900, the channel structure layer 850 including one or more channel layers 860 arranged sequentially at intervals, the channel layers 860 being stacked in a direction perpendicular to the surface of the substrate 800; and an insulating layer. Layer 870, located on the substrate 800 and surrounding the protrusion 810, the isolation layer 820, and the fill layer 900, the insulating layer 870 covers the sidewalls of the isolation layer 820 and the fill layer 900 and exposes the channel structure layer 850; gate structure 830, located on the insulating layer 870, spanning the channel structure layer 850 and surrounding the channel layer 860, the gate structure 830 also located on top of the fill layer 900 and spanning the fill layer 900; source / drain doped layers 840, located on the fill layers 900 on both sides of the gate structure 830 and in contact with the ends of each channel layer 860 in the channel structure layer 850 along the extension direction.

[0031] The substrate 800 is used to provide a process platform for the formation of semiconductor structures.

[0032] In this embodiment, a gate-all-around (GAA) transistor is used as an example of semiconductor structure. In other embodiments, the semiconductor structure may also be other types of transistors such as forksheet transistors or complementary field-effect transistors (CFETs).

[0033] In this embodiment, the substrate 800 is a silicon substrate, that is, the material of the substrate 800 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0034] The protrusion 810 protrudes from the substrate 800 so that the insulating layer can be located on the substrate 800 and surround the protrusion 810. The protrusion 810 also serves to provide support for the channel structure layer and the gate structure 830.

[0035] In this embodiment, the protrusion 810 and the substrate 800 are an integral structure, and the material of the protrusion 810 is the same as that of the substrate 800, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0036] The isolation layer 820 is used to isolate the source / drain doped layer 840 and the protrusion 810, as well as the gate structure 830 and the protrusion 810. This helps to prevent the source / drain doped layer 840 and the gate structure 830 and the protrusion 810 below them from forming parasitic devices. This, in turn, helps to eliminate leakage channels generated in the protrusion 810, reduces the leakage current of the device, and improves the performance of the semiconductor structure.

[0037] Therefore, the material of the isolation layer 820 is an insulating material.

[0038] Specifically, the material of the isolation layer 820 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the material of the isolation layer 820 is silicon oxide.

[0039] In this embodiment, the isolation layer 820 includes a first region I and a second region II located on both sides of the first region I; the first region I is located below the gate structure 830 and the source / drain doped layer 840, and the second region II is located on both sides of the gate structure 830 and the source / drain doped layer 840.

[0040] Accordingly, in this embodiment, the isolation layer 820 includes: a first isolation layer 821 located on the first region I; and a second isolation layer 822 located on the second region II.

[0041] The first isolation layer 821 is used to isolate the gate structure 830 from the protrusion 810 and the source / drain doped layer 840 from the protrusion 810, and the second isolation layer 822 is used to further isolate the source / drain doped layer 840 from the protrusion 810.

[0042] In this embodiment, the first isolation layer 821 and the second isolation layer 822 are made of the same material, silicon oxide. In other embodiments, the materials of the first isolation layer and the second isolation layer may be different.

[0043] In this embodiment, the top surfaces of the first isolation layer 821 and the second isolation layer 822 are flush, thereby achieving isolation between the source / drain doped layer 840 and the protrusion 810, as well as isolation between the gate structure 830 and the protrusion 810, and exposing the channel layer 860, which is beneficial for forming the source / drain doped layer 840 on the end of the exposed channel layer 860 through epitaxial process.

[0044] In other embodiments, the top surface of the second isolation layer may be lower than the top surface of the first isolation layer.

[0045] In this embodiment, the isolation layer 820 is described as including a first isolation layer 821 and a second isolation layer 822. In other embodiments, based on actual process requirements, the isolation layer can also be a monolithic structure, and the isolation layer can also achieve the function of isolating the gate structure from the bumps, and the source / drain doped layers from the bumps.

[0046] In this embodiment, the filling layer 900 is located on the first region I of the isolation layer 820, so that the filling layer 900 and the first isolation layer 821 together make the channel structure layer 850 and the protrusion 810 suspended at a distance.

[0047] The gate structure 830 is located on top of the filling layer 900 and spans the filling layer 900. The source / drain doped layer 840 is located on the filling layer 900 on both sides of the gate structure 830. Accordingly, the filling layer 900 and the isolation layer 820 achieve isolation between the gate structure 830 and the protrusion 810, as well as between the source / drain doped layer 840 and the protrusion 810.

[0048] Therefore, the material of the filling layer 900 is an insulating material.

[0049] Specifically, the material of the filling layer 900 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the material of the filling layer 900 is silicon oxide. It should be noted that the channel layer 860 extends laterally, and the lateral width of the filling layer 900 located between the source / drain doped layer 840 and the isolation layer 820 should not be too small or too large. If the lateral width of the filling layer 900 located between the source / drain doped layer 840 and the isolation layer 820 is too small, the space of the source / drain doped layer 840 is correspondingly reduced, thereby decreasing the quality of the source / drain doped layer 840. If the lateral width of the filling layer 900 located between the source / drain doped layer 840 and the isolation layer 820 is too large, the space of the source / drain doped layer 840 formed on the filling layer 900 is too large, thereby reducing the formation space of the interlayer dielectric layer 910 and correspondingly reducing the isolation effect of adjacent devices. Therefore, in this embodiment, the lateral width of the filling layer 900 located between the source / drain doped layer 840 and the isolation layer 820 is 5 nm to 10 nm.

[0050] The channel structure layer 850 is used to provide a conductive channel for the field-effect transistor. Specifically, the channel layer 860 is used to provide the conductive channel.

[0051] As an example, the channel structure layer 850 extends along the lateral direction. The stacking direction of the channel layer 860 is perpendicular to the surface of the substrate 800.

[0052] In this embodiment, the channel layer 860 is made of Si, which is beneficial for improving the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor, and the channel layer is made of SiGe. In other embodiments, the channel layer material can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0053] As an example, in the channel structure layer 850, the number of channel layers 860 is three. In other embodiments, the number of channel layers may also be other.

[0054] The insulating layer 870 serves to isolate adjacent protrusions 810 and also to isolate the substrate 800 from the gate structure 830.

[0055] The insulating layer 870 is made of one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the insulating layer 870 is made of silicon oxide.

[0056] When the device is in operation, the gate structure 830 is used to control the opening and closing of the conductive channel.

[0057] In this embodiment, the gate structure 830 is a metal gate structure, which includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through slot and the gate opening.

[0058] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0059] As an example, the gate dielectric layer includes a high-k gate dielectric layer, the material of which is a high-k dielectric material. The material of the high-k gate dielectric layer may also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer; alternatively, the gate dielectric layer may consist only of the gate oxide layer.

[0060] The work function layer is used to adjust the work function of the gate structure, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0061] The gate electrode layer is used as an external electrode for electrical connection between the gate structure 830 and external circuitry. The material of the gate electrode layer is a conductive material, including one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0062] In this embodiment, a metal gate structure 830 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0063] The gate structure 830 includes: a first portion 831 located between the fill layer 900 and the channel layer 860 adjacent to the fill layer 900; and a second portion 832 spanning the channel structure layer 850.

[0064] In this embodiment, the semiconductor structure further includes: an inner sidewall 880 located on the sidewall of the first portion 831 and exposing the end of each channel layer 860 in the channel structure layer 850; and a gate sidewall 890 located on the sidewall of the second portion 832 and exposing the end of each channel layer 860 in the channel structure layer 850.

[0065] On the one hand, the inner wall 880 is used to isolate the source / drain doped layer 840 from the gate structure 830. On the other hand, it can increase the distance between the gate structure 830 and the source / drain doped layer 840, which is beneficial to reduce the parasitic capacitance between the gate structure 830 and the source / drain doped layer 840.

[0066] In this embodiment, the material of the inner sidewall 880 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride; as an example, the material of the inner sidewall 880 is silicon nitride.

[0067] The gate sidewall 890 is used to define the formation location of the source / drain doped layer 840, and the gate sidewall 890 is also used to protect the sidewall of the gate structure 830.

[0068] In this embodiment, the gate sidewall 890 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide or silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 890 is a single-layer or multi-layer structure. As an example, the gate sidewall 890 is a single-layer structure, and the material of the gate sidewall 890 is silicon nitride.

[0069] The source / drain doped layer 840 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped layer 840 is used to provide a source of charge carriers.

[0070] In this embodiment, the source / drain doped layer 840 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped layer 840 includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source / drain doped layer 840 includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe.

[0071] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 910, which is located on the isolation layer 820 and covers the sidewall of the gate sidewall 890 and the source / drain doped layer 840.

[0072] The interlayer dielectric layer 910 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 910 is silicon oxide. The material of the interlayer dielectric layer 910 can also be other insulating materials.

[0073] In this embodiment, the interlayer dielectric layer 910 also covers the isolation layer 820 (i.e., the second isolation layer 822) of the second region II.

[0074] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 9 to 30 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0075] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0076] refer to Figure 9 The substrate is provided, including a substrate 100 and a plurality of protrusions 10 protruding from the substrate 100. A sacrificial layer 20, an etch stop layer 40 and a stacked structure 30 are sequentially formed on the protrusions 10. The etch stop layer 40 is made of a semiconductor material. The stacked structure 30 includes one or more channel stacks 31 stacked sequentially from bottom to top. Each channel stack 31 includes a placeholder layer 32 and a channel layer 33 located on the placeholder layer 32.

[0077] The substrate serves as a process platform for subsequent fabrication processes. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0078] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0079] The protrusion 10 protrudes from the substrate 100 so that a subsequent insulating layer can be located on the substrate 100 and surround the protrusion 10. The protrusion 10 also serves to provide support for the channel stack 31. In this embodiment, the protrusion 10 and the substrate 100 are an integral structure, and the material of the protrusion 10 is the same as that of the substrate 100, which is silicon.

[0080] In other embodiments, the material of the protrusion may be different from the material of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0081] The sacrificial layer 20 is used to reserve space for the subsequent formation of the isolation layer.

[0082] The material of the sacrificial layer 20 needs to have a high selectivity ratio with the material of the protrusion 10 in order to improve the integrity of the protrusion 10 in the subsequent step of removing the sacrificial layer 20 to form a channel.

[0083] In this embodiment, the material of the sacrificial layer 20 is a semiconductor material, so that the sacrificial layer 20 can be formed by an epitaxial process, and a semiconductor material can be epitaxially grown on the sacrificial layer 20, thereby forming the etch stop layer 40 on the sacrificial layer 20.

[0084] In this embodiment, the material of the sacrificial layer 20 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the material of the sacrificial layer 20 is SiGe.

[0085] In this embodiment, the step of forming the sacrificial layer 20 includes: forming the sacrificial material layer (not shown) on the protrusion 10. As an example, an epitaxial process is used to form the sacrificial material layer on the protrusion 10.

[0086] The etch stop layer 40 is used to provide a process basis for the subsequent formation of the source / drain doped layer. The process of forming the source / drain doped layer usually includes epitaxial process. In the step of forming the source / drain doped layer, in addition to using the channel layer 33 as the growth basis for the epitaxial process, the etch stop layer 40 can also be used as the growth basis to perform the epitaxial process to form the source / drain doped layer, which increases the process platform when performing the epitaxial process, thereby improving the epitaxial quality of the source / drain doped layer.

[0087] Furthermore, in the subsequent step of forming grooves in the stacked structure 30, the top surface of the etch stop layer 40 serves as the etch stop position to avoid over-etching, thereby protecting the sacrificial layer 20 located below the etch stop layer 40; and in the subsequent step of removing the sacrificial layer, the bottom surface of the etch stop layer 40 can be used as the etch stop position, which helps to reduce the probability of accidental etching of the stacked structure 30.

[0088] In this embodiment, the etch stop layer 40 is made of a semiconductor material to provide a process basis for the subsequent formation of source / drain doped layers. Specifically, the etch stop layer 40 can serve as an epitaxial growth basis for the subsequent formation of source / drain doped layers. Furthermore, the material of the etch stop layer 40 has a high selectivity ratio with the material of the placeholder layer 32, so that in the subsequent step of forming the trench, the etch stop layer 40 can effectively protect the sacrificial layer 20; and in the subsequent step of removing the sacrificial layer 20, the etch stop layer 40 has a high selectivity ratio with the material of the sacrificial layer 20, so that the etch stop layer 40 can effectively protect the bottom of the stacked structure 30.

[0089] As an example, when the material of the sacrificial layer 20 is SiGe, the material of the etch stop layer 40 can be Si. Si and SiGe have high etch selectivity, and the sacrificial layer 20 is made of the same commonly used material as the placeholder layer 32, and the etch stop layer 40 is made of the same commonly used material as the channel layer 33. This allows the sacrificial layer 20 and the etch stop layer 40 to be formed using the same process as forming the channel stack 31, which improves process integration and avoids introducing additional material types.

[0090] The channel stack 31 provides a process basis for the subsequent formation of the channel layer 33 with suspended space separation.

[0091] Specifically, the channel layer 33 is used to provide a conductive channel for the field-effect transistor, and the placeholder layer 32 is used to support the channel layer 33, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the channel layer 33. The placeholder layer 32 is also used to occupy space for the subsequent formation of the gate structure.

[0092] In this embodiment, an NMOS transistor is formed, with the channel layer 33 made of Si and the placeholder layer 32 made of SiGe. During the subsequent removal of the placeholder layer 32, the etching selectivity for SiGe and Si is relatively high. By setting the material of the placeholder layer 32 to SiGe and the material of the channel layer 33 to Si, the impact of the placeholder layer 32 removal process on the channel layer 33 can be effectively reduced, thereby improving the quality of the channel layer 33 and ultimately contributing to improved device performance.

[0093] In other embodiments, when forming a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor, wherein the channel layer is made of SiGe and the placeholder layer is made of Si. In other embodiments, the channel layer material can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0094] As an example, the step of providing a substrate may include: providing a semiconductor layer; sequentially forming a sacrificial material layer, an etch stop material layer, and one or more channel stacks on the semiconductor layer; sequentially patterning the channel stack, the etch stop material layer, the sacrificial material layer, and a portion of the semiconductor layer, wherein the remaining channel stack serves as the channel stack, the remaining etch stop material layer serves as the etch stop layer, the remaining sacrificial material layer serves as the sacrificial layer, and the remaining semiconductor layer includes a substrate and bumps.

[0095] In this process, an epitaxial process is used to sequentially form a sacrificial material layer, an etch stop material layer, and one or more trench films.

[0096] refer to Figure 10 An insulating layer 50 is formed on the substrate 100 surrounding the protrusion 10, the sacrificial layer 20, and the etch stop layer 40.

[0097] The insulating layer 50 serves to isolate adjacent protrusions 10 and also to isolate the substrate 100 from the gate structure.

[0098] In this embodiment, a pseudo-gate structure spanning the stacked structure 30 is subsequently formed on the insulating layer 50, and grooves are formed in the stacked structure 30 on both sides of the pseudo-gate structure, exposing the channel layer 33. The insulating layer 50 exposes the stacked structure 30 so that subsequent epitaxial growth can be performed not only using the etch stop layer 40 as the basis for forming source / drain doped layers, but also using the channel layer 33 as the basis for epitaxial growth to form source / drain doped layers.

[0099] In this embodiment, the insulating layer 50 also covers the sidewalls of the sacrificial layer 20 and the etch stop layer 40, so that in the subsequent step of forming grooves in the stacked structure 30 on both sides of the pseudo gate structure, the insulating layer 50 can protect the sacrificial layer 20 and the etch stop layer 40 and prevent accidental etching of the sacrificial layer 20 and the etch stop layer 40.

[0100] The insulating layer 50 is made of one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the insulating layer 50 is made of silicon oxide.

[0101] refer to Figure 11 A pseudo-gate structure 60 is formed on the insulating layer 50, spanning the stacked structure 30.

[0102] The pseudo-gate structure 60 is used to pre-occupy space for the subsequent formation of the gate structure.

[0103] The pseudo-gate structure 60 can be a stacked structure or a single-layer structure. In this embodiment, the pseudo-gate structure 60 is a stacked structure, including a pseudo-gate oxide layer (not shown) and a pseudo-gate layer (not shown) located on the pseudo-gate oxide layer.

[0104] Specifically, the pseudo-gate structure 60 is a polycrystalline silicon gate structure or an amorphous silicon gate structure, and the material of the pseudo-gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the pseudo-gate layer can be polycrystalline silicon or amorphous silicon.

[0105] refer to Figure 12 A gate sidewall 70 is formed on the sidewall of the pseudo-gate structure 60.

[0106] The gate sidewall 70 is used together with the dummy gate structure 60 as an etching mask for the subsequent etching process to form a groove, so as to define the formation position of the source and drain doped layers. The gate sidewall 70 is also used to protect the dummy gate structure 60 and the sidewalls of the subsequent gate structure.

[0107] In this embodiment, the gate sidewall 70 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide or silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 70 is a single-layer or multi-layer structure. As an example, the gate sidewall 70 is a single-layer structure, and the material of the gate sidewall 70 is silicon nitride.

[0108] refer to Figure 13 A groove 80 is formed in the stacked structure 30 on both sides of the pseudo gate structure 60, and the bottom of the groove 80 exposes the etching stop layer 40.

[0109] The groove 80 is used to provide space for the formation of source and drain doped layers.

[0110] The sidewalls of the groove 80 expose the stacked structure 30, which facilitates the formation of source / drain doped layers on the sidewalls of the exposed channel layer 33 of the groove 80 through subsequent epitaxial processes; and also facilitates the removal of the portion of the occupant layer 12 exposed on the sidewalls of the groove 80 along the extension direction of the channel layer 33 to form an inner trench.

[0111] Furthermore, in this embodiment, the bottom of the groove 80 exposes the etch stop layer 40, so that during the subsequent formation of a protective sidewall on the sidewall of the groove 80, the protective sidewall can cover part of the top surface of the etch stop layer 40. The portion of the etch stop layer 40 covered by the protective sidewall can be retained in subsequent processes, so that in the subsequent step of forming the source / drain doped layer, in addition to using the channel layer 20 as the growth basis for the epitaxial process, the etch stop layer 40 can also be used as the growth basis for the epitaxial process to form the source / drain doped layer. This increases the process platform during the epitaxial process, thereby improving the epitaxial quality of the source / drain doped layer.

[0112] In this embodiment, the bottom of the groove 80 exposes the etch stop layer 40, so that the top surface of the etch stop layer 40 can be used as the etch stop position, and the stacked structures 30 on both sides of the pseudo gate structure 60 can be etched using an etching process. Accordingly, the etch stop layer 40 defines the position of the bottom of the groove 80, so that the sacrificial layer 20 located below the groove 80 can be retained, so that the sacrificial layer 20 can be removed later and an isolation layer can be formed at the position of the sacrificial layer 20.

[0113] Specifically, in this embodiment, an anisotropic etching process (e.g., anisotropic dry etching process) is used to etch the stacked structure 30 on both sides of the pseudo gate structure 60 and the gate sidewall 70, which is beneficial to improve the cross-sectional morphology quality of the groove 80, thereby facilitating precise control of the sidewall morphology of the groove 80.

[0114] refer to Figure 14 The method for forming the semiconductor structure further includes: after forming the groove 80 in the stacked structure 30 on both sides of the pseudo-gate structure 60, removing a portion of the thickness of the occupant layer 32 exposed on the sidewall of the groove 80 along the extension direction of the channel layer 33 to form an inner trench 81.

[0115] The inner groove 81 provides space for the subsequent formation of the inner sidewall.

[0116] In this embodiment, a vapor etching process is used to etch the occupant layer 32, which is a portion of the sidewall thickness of the groove 80, along the extension direction of the channel layer 33. Vapor etching is an isotropic etching process that can etch the occupant layer 32 along the direction of the protrusion 10. Furthermore, vapor etching easily achieves a large etching selectivity, which helps reduce the difficulty of etching the occupant layer 32 and reduces the probability of damage to other film structures (e.g., the channel layer 33).

[0117] In this embodiment, the material of the occupant layer 32 is SiGe, and the material of the channel layer 33 is Si. The occupant layer 32 on the sidewall of the groove 80 is etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damage to the channel layer 33.

[0118] In other embodiments, when the channel layer is SiGe and the placeholder layer is made of Si, a dry etching process can be used to etch the placeholder layer on the sidewall of the trench along the extension direction of the channel layer. The etchant used in the dry etching process can include a mixture of plasmas of CF4, O2, and N2. The difference between the etching rate of Si and the etching rate of SiGe in the plasma mixture is relatively large, which can effectively reduce the probability of damage to the channel layer 33.

[0119] refer to Figure 15 A protective sidewall 90 is formed on the sidewall of the groove 80, and the protective sidewall 90 covers part of the top surface of the etching stop layer 40.

[0120] The protective sidewall 90 occupies space for the subsequent formation of the source / drain doped layer. The protective sidewall 90 covers part of the top surface of the etch stop layer 40, protecting the etch stop layer 40 located directly below the bottom of the protective sidewall 90. This ensures that the etch stop layer 40 below the protective sidewall 90 can be retained during the subsequent removal of the protective sidewall 90, thereby providing a process basis for the subsequent formation of the source / drain doped layer, increasing the process platform for epitaxial processes, and ultimately improving the epitaxial quality of the source / drain doped layer.

[0121] Furthermore, the protective sidewall 90 serves to protect the stacked structure 30 during the subsequent removal of the sacrificial layer 20 and the etching stop layer 40, thereby reducing the probability of damage to the stacked structure 30.

[0122] Furthermore, during the subsequent removal of the sacrificial layer 20, the etch stop layer 40 and the sacrificial layer 20 exposed by the protective sidewall 90 can be removed first, exposing the sidewall of the sacrificial layer 20 located below the stacked structure 30, so that the sacrificial layer 20 below the stacked structure 30 can be removed subsequently through the exposed sidewall of the sacrificial layer 20.

[0123] The material of the protective sidewall 90 needs to have a high selectivity ratio with the sacrificial layer 20 so as to effectively protect the laminated structure 30 in the subsequent step of removing the sacrificial layer 20 to form a channel.

[0124] In this embodiment, the material of the protective sidewall 90 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride; as an example, the material of the protective sidewall 90 is silicon nitride.

[0125] It should be noted that the thickness of the protective sidewall 90 should not be too small or too large. If the thickness of the protective sidewall 90 is too small, the area of ​​the subsequently exposed etch stop layer 40 will be too small, resulting in a small growth base for the subsequent formation of the source / drain doped layer, reducing the process platform during epitaxial processing, and thus lowering the epitaxial quality of the source / drain doped layer. If the thickness of the protective sidewall 90 is too large, the area of ​​the subsequently exposed etch stop layer 40 will be too large, resulting in a large growth base for the formation of the source / drain doped layer, thus reducing the formation space of the subsequent interlayer dielectric layer, and correspondingly reducing the isolation effect between adjacent devices. Therefore, in this embodiment, the thickness of the protective sidewall 90 is 5 nm to 10 nm.

[0126] In this embodiment, during the step of forming the protective sidewall 90, the protective sidewall 90 is also filled in the inner groove 81. Thus, in the subsequent step of removing the protective sidewall 90 located on the sidewall of the channel layer 33, the remaining protective sidewall 90 filled in the inner groove 81 is retained as the inner sidewall 91. This allows the process steps of forming the protective sidewall 90 and removing the sacrificial layer 20 to be integrated with the process of forming the inner sidewall 91, improving process integration and process compatibility, and also simplifying the process flow.

[0127] In this embodiment, the protective sidewall 90 is formed on the sidewall of the gate sidewall 70.

[0128] Specifically, in this embodiment, the step of forming the protective sidewall 90 includes: forming a protective material layer (not shown) on the sidewall of the gate sidewall 70, the top of the dummy gate structure 60, the top of the insulating layer 50, and the top of the etch stop layer 40; retaining a portion of the protective material layer located on both sides of the dummy gate structure 60, removing the protective material layer located on the top of the dummy gate structure 60, the insulating layer 50, and the etch stop layer 40, and the remaining protective material layer located on the sidewall of the gate sidewall 70 as the protective sidewall 90.

[0129] As an example, a protective material layer is formed using atomic layer deposition (ALD). ALD allows for precise control of the thickness of the protective material layer at the atomic level, resulting in a high-quality protective material layer and improving its step coverage.

[0130] As an example, the protective material layer located on top of the dummy gate structure 60, the insulating layer 50, and the etch stop layer 40 is removed using an anisotropic etching process, leaving the remaining protective material layer on the sidewall of the gate sidewall 70 as the protective sidewall 90. Employing anisotropic etching processes (e.g., anisotropic dry etching) to etch the protective material layer on the sidewalls of the dummy gate structure 60 facilitates precise control over the sidewall morphology of the protective sidewall 90.

[0131] refer to Figure 16 Remove the etch stop layer 40 exposed by the protective sidewall 90 to expose the top surface of the sacrificial layer 20 so that the etch stop layer 40 can be removed subsequently.

[0132] Specifically, using the protective sidewall 90 as a mask, an anisotropic etching process is employed to remove the etching stop layer 40 located at the bottom of the groove 80 in a direction perpendicular to the surface of the substrate 100, thereby exposing the top surface of the sacrificial layer 20.

[0133] As an example, an anisotropic dry etching process is used to remove the etching stop layer 40 located at the bottom of the groove 80, exposing the top surface of the sacrificial layer 20. The dry etching process offers high process controllability, allowing for precise control of the removal thickness.

[0134] In other embodiments, other types of anisotropic etching processes (e.g., anisotropic wet etching processes) may be used to remove the etching stop layer 40 located at the bottom of the groove.

[0135] Continue to refer to Figure 16 and Figure 17 Remove the sacrificial layer 20 and form a channel 110 between the etch stop layer 40 and the protrusion 10 and below the groove 80. The channel 110 is surrounded by the insulating layer 50, the protrusion 10 and the etch stop layer 40.

[0136] The channel 110 is located between the etch stop layer 40 and the protrusion 10, and below the groove 80. Thus, the isolation layer subsequently formed in the channel 110 can be located between the etch stop layer 40 and the protrusion 10, and below the groove 80. This allows the isolation layer to achieve isolation between the source / drain doped layer and the protrusion 10, and between the gate structure and the protrusion 10, after the source / drain doped layer is formed on the etch stop layer 40 and the occupant layer 32 is replaced with a gate structure.

[0137] The steps for removing the sacrificial layer 40 and forming the channel 110 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0138] like Figure 16 As shown, the sacrificial layer 20 located at the bottom of the groove 80 is removed.

[0139] Specifically, in this embodiment, an anisotropic etching process is used to remove the sacrificial layer 20 located at the bottom of the groove 80.

[0140] Specifically, using the protective sidewall 90 as a mask, an anisotropic etching process is employed to remove the sacrificial layer 20 located at the bottom of the groove 80 along a direction perpendicular to the surface of the substrate 100. This helps prevent etching of the etch stop layer 40 located below the stacked structure 30, allowing the etch stop layer 40 to be retained. In subsequent steps of removing the sacrificial layer 20 below the stacked structure 30, the etch stop layer 40 can define the etch stop position, thereby protecting the stacked structure 30 and reducing the probability of damage to the stacked structure 30.

[0141] As an example, an anisotropic dry etching process is used to remove the sacrificial layer 20 located at the bottom of the groove 80. The dry etching process has high process controllability and can precisely control the removal thickness.

[0142] In other embodiments, other types of anisotropic etching processes may be used to remove the sacrificial layer located at the bottom of the groove, such as anisotropic wet etching processes.

[0143] like Figure 17 As shown, the sacrificial layer 20 located below the stacked structure 30 is removed.

[0144] In this embodiment, an isotropic etching process is used to remove the sacrificial layer 20 located below the stacked structure 30. Specifically, in this embodiment, an isotropic dry etching process is used to remove the sacrificial layer 20 located below the stacked structure 30. Using an isotropic dry etching process is beneficial for subsequent removal of reactive impurities and helps to ensure the cleanliness of the channel 110.

[0145] In this embodiment, during the removal of the sacrificial layer 20 located below the stacked structure 30, the etch stop layer 40 located above the sacrificial layer 20 can define the etch stop position, thereby protecting the bottom of the stacked structure 30.

[0146] refer to Figures 18 to 20 An isolation layer 120 is formed within the channel 110.

[0147] The isolation layer 120 is used to isolate the source / drain doped layers and the bump 10, as well as the gate structure and the bump 10. This helps prevent parasitic devices from forming in the source / drain doped layers, the gate structure, and the bump 10 below them. This, in turn, helps eliminate leakage paths generated within the bump 10, reducing leakage current and improving the performance of the semiconductor structure. Furthermore, the isolation layer 120 provides the process basis for subsequent channel formation.

[0148] Therefore, the material of the insulating layer 120 is an electrically insulating material. Specifically, the material of the insulating layer 120 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride; as an example, the material of the insulating layer 120 is silicon oxide.

[0149] The steps for forming the isolation layer 120 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0150] like Figure 18 As shown, a first isolation layer 121 is filled in the channel 110 between the etching stop layer 40 and the protrusion 10.

[0151] The first isolation layer 121 is used to isolate the gate structure from the protrusion 10 and the source / drain doped layer from the protrusion 10.

[0152] In this embodiment, the step of forming the first isolation layer 121 includes: forming a first isolation material layer (not shown) in the channel 110 between the etch stop layer 40 and the protrusion 10; removing the first isolation material layer located at the bottom of the groove 80, and the remaining first isolation material layer filling the lower part of the stacked structure 30 as the first isolation layer 121.

[0153] Specifically, a first isolation material layer (not shown) is deposited in the channel 110 between the etch stop layer 40 and the protrusion 10 by chemical vapor deposition (CVD); the first isolation material layer located at the bottom of the groove 80 is removed by an isotropic etching process.

[0154] In this embodiment, during the step of forming the first isolation layer 121, the protective sidewall 90 can protect the channel layer on the sidewall of the groove 80, thereby reducing the probability of damage to the channel layer.

[0155] like Figures 20 to 21 As shown, a second isolation layer 122 is formed in the channel 110 on both sides of the gate structure. The second isolation layer 122 and the first isolation layer 121 are in contact to form the isolation layer 120.

[0156] The second isolation layer 122 is used to further isolate the source / drain doped layer from the protrusion 10.

[0157] Specifically, in this embodiment, the step of forming the second isolation layer 122 includes: as follows Figure 20 As shown, a second isolation material layer 123 is formed on the exposed protrusion 10 and the insulating layer 50. The second isolation material layer 123 covers the sidewall of the gate sidewall 70 and the sidewall of the etch stop layer 40, and fills the channel 110; as Figure 21 As shown, after removing a portion of the thickness of the second insulating material layer 123 located on the protrusion 10 and the second insulating material layer located on the insulating layer 50, the remaining second insulating material layer 123 filling the channel 110 is used as the second insulating layer 122.

[0158] The formation of the second isolation material layer 123 includes: depositing an isolation film (not shown) on the exposed protrusion 10 and the insulating layer 50; planarizing the isolation film with the hard mask layer (not shown) located on top of the dummy gate structure 60 as the stop position, and retaining the isolation film located above the protrusion 10 and the insulating layer 50 and below the hard mask layer on top of the dummy gate structure 60 as the second isolation material layer 123.

[0159] In this embodiment, an isolation film is deposited on the exposed protrusion 10 and the insulating layer 50 by chemical vapor deposition; the planarization process is performed by chemical mechanical polishing (CMP).

[0160] In this embodiment, an anisotropic etching process is used to remove a portion of the second insulating material layer 123 located on the insulating layer 50 and on the protrusion 10.

[0161] As an example, an anisotropic dry etching process is used to etch the second isolation material layer 123. The anisotropic dry etching process is beneficial for precise control of the removal thickness of the second isolation material layer 123.

[0162] In this embodiment, the top surface of the second isolation layer 122 is flush with the etching stop layer 40.

[0163] It should be noted that the reference Figure 19 Remove the protective sidewall 90 located on the sidewall of the channel layer 33 to expose the sidewall of the channel layer 33 and the etch stop layer 40 located on both sides of the pseudo gate structure 60.

[0164] The protective sidewall 90 on the channel layer 33 located on the sidewall of the groove is removed to expose the channel layer 33. This allows the channel layer 33 to be used as the growth base for the epitaxial process in the subsequent step of forming the source / drain doped layer. In addition to using the channel layer 33 as the growth base for the epitaxial process, the etch stop layer 40 can also be used as the growth base for the epitaxial process to form the source / drain doped layer. This increases the process platform for the epitaxial process and thus improves the epitaxial quality of the source / drain doped layer.

[0165] Specifically, in this embodiment, after the first isolation layer 121 is formed and before the second isolation layer 122 is formed, the protective sidewall 90 located on the sidewall of the channel layer 33 is removed.

[0166] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: in the step of removing the protective sidewall 90 located on the sidewall of the channel layer, the remaining protective sidewall 90 filled in the inner trench 81 is retained as the inner sidewall 91.

[0167] In the step of forming the protective sidewall 90, the protective sidewall 90 is also filled in the inner groove 81. Thus, in the step of removing the protective sidewall 90 located on the channel layer 33 on the sidewall of the groove 80 after removing the sacrificial layer 20, the protective sidewall 90 filled in the inner groove 81 can be used as the inner sidewall 91. This allows the process steps of forming the protective sidewall 90 and removing the sacrificial layer 20 to be integrated with the process of forming the inner sidewall 91, improving process integration and process compatibility, and also simplifying the process flow.

[0168] The inner wall 91 is used to isolate the source / drain doped layer from the gate structure, which can increase the distance between the gate structure and the source / drain doped layer, and help reduce the parasitic capacitance between the gate structure and the source / drain doped layer.

[0169] Accordingly, in this embodiment, the material of the inner sidewall 91 is the same as the material of the protective sidewall 90.

[0170] Specifically, an isotropic etching process is used to etch the protective sidewall 90 located outside the trench layer 33, exposing the trench layer 33. The isotropic etching process can be an isotropic dry etching process.

[0171] refer to Figure 22 Source / drain doped layers 130 are formed on the etch stop layers 40 on both sides of the pseudo gate structure 60, and the source / drain doped layers 130 are in contact with the end of the channel layer 33 along the extension direction.

[0172] The source / drain doped layer 130 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped layer 130 is used to provide a source of charge carriers.

[0173] In addition to using the channel layer as the growth basis for the epitaxial process, the source / drain doped layer 130 also uses the etch stop layer 40 as the growth basis, thus increasing the process platform for epitaxial processing and improving the epitaxial quality of the source / drain doped layer 130. Furthermore, the source / drain doped layer 130 is suspended on the protrusion 10, thereby achieving isolation between it and the protrusion 10.

[0174] In this embodiment, the source / drain doped layer 130 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped layer 130 includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source / drain doped layer 130 includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe.

[0175] In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer. The stress layer doped with ions is used as the source / drain doping layer 130.

[0176] refer to Figures 23 to 24 The etching stop layer 40 is removed to form a trench 180. The trench 180 is surrounded by the isolation layer 120, the insulating layer 50, the stacked structure 30, and the source / drain doped layers 130 located on both sides of the stacked structure 30. The stacked structure 30 and the source / drain doped layers 130 are suspended above the isolation layer 120.

[0177] The groove 180 is used to provide space for the subsequent formation of the fill layer.

[0178] Specifically, the trench 180 is located below the stacked structure 30 and the source / drain doped layer 130, so that the filling layer subsequently formed in the trench 180 can be located below the stacked structure 30 and the source / drain doped layer 130, so that after the placeholder layer 32 is replaced with the gate structure, the filling layer and the isolation layer 120 can achieve isolation between the source / drain doped layer 130 and the protrusion 10, and between the gate structure and the protrusion 10.

[0179] The following description, in conjunction with the accompanying drawings, details the steps of removing the etching stop layer 40 and forming the trench 180 in this embodiment.

[0180] like Figure 23As shown, the portion of the thickness of the insulating layer 50 and the isolation layer 120 exposed by removing the pseudo-gate structure 60 and the source / drain doped layer 130 exposes the sidewall of the etch stop layer 40.

[0181] Specifically, in this embodiment, an anisotropic etching process is used to remove the portion of the thickness of the insulating layer 50 and the isolation layer 120 exposed by the dummy gate structure 60 and the source / drain doped layer 130. This helps to prevent accidental etching of the insulating layer 50 located below the dummy gate structure 60, so that the insulating layer 50 located below the dummy gate structure 60 can provide sufficient support for the dummy gate structure 60.

[0182] As an example, an anisotropic dry etching process is used to remove the portion of the dummy gate structure 60 and the source / drain doped layer 130 exposed in the insulating layer 50 and the isolation layer 120. This anisotropic dry etching process allows for precise control over the thickness of the insulating layer 50 and the isolation layer 120 removed.

[0183] In other embodiments, other types of anisotropic etching processes may be employed to remove the etching stop layer and sacrificial layer located at the bottom of the groove, such as anisotropic wet etching processes.

[0184] like Figure 24 As shown, the etch stop layer 40 is removed through the exposed sidewalls of the etch stop layer 40 to form the trench 180.

[0185] The materials of the insulating layer 50 and the etching stop layer 40 have a high selectivity ratio, which helps to prevent accidental etching of the insulating layer 50 below the dummy gate structure 60 and protects the insulating layer 50 located below the dummy gate structure 60.

[0186] In this embodiment, an isotropic etching process is used to selectively etch the etch stop layer 40 below the source / drain doped layer 130. As an example, using an isotropic dry etching process to subsequently remove reactive impurities helps ensure the cleanliness of the trench 180.

[0187] refer to Figure 25 A filling layer 200 is formed within the groove 180.

[0188] The filling layer 200 is located between the stacked structure 30 and the isolation layer 120, and between the source / drain doped layer 130 and the isolation layer 120, so that after the placeholder layer 32 is replaced with the gate structure, the filling layer 200 and the first isolation layer 121 together achieve isolation between the source / drain doped layer 130 and the protrusion 10, and between the gate structure and the protrusion 10.

[0189] Specifically, the material of the filling layer 200 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the material of the filling layer 200 is silicon oxide.

[0190] In this embodiment, the step of forming the filling layer 200 includes: forming a filling material layer (not shown) in the trench 180, removing the filling material layer located on both sides of the source / drain doped layer 130, and the remaining filling material layer filling the stacked structure 30 and the source / drain doped layer 130 as the filling layer 200.

[0191] Specifically, in this embodiment, the filling material layer is formed by chemical vapor deposition (CVD) process.

[0192] In this embodiment, the source / drain doped layer 130 is used as a mask, and an anisotropic etching process is employed to remove the filling material layers located on both sides of the source / drain doped layer 130 in a direction perpendicular to the surface of the substrate 100.

[0193] As an example, an anisotropic dry etching process is used to remove the filler material layers located on both sides of the source / drain doped layer 130. The dry etching process offers high process controllability, allowing for precise control of the removal thickness.

[0194] In this embodiment, during the step of forming the filling layer 200, the gate sidewall 70 can protect the channel layer 33 on the sidewall of the recess 80, thereby reducing the probability of damage to the channel layer 33.

[0195] Specifically, the material of the filling layer 200 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the material of the filling layer 200 is silicon oxide.

[0196] refer to Figure 26 and Figure 27 , Figure 26 It is a 3D image. Figure 27 for Figure 26 A cross-sectional view along the XX direction shows that the method of forming the semiconductor structure further includes: after forming the filling layer 200, forming an interlayer dielectric layer 170 on the isolation layer 120 and the insulating layer 50 on the side of the dummy gate structure 60, covering the source / drain doped layer 130.

[0197] Specifically, the interlayer dielectric layer 170 covers the sidewall of the gate sidewall 70 and the source / drain doped layer 130. The interlayer dielectric layer 170 is used to isolate adjacent devices and also to support the channel layer 33 during the subsequent removal of the dummy gate structure 60 and the occupant layer 32, so as to achieve the suspended space arrangement of the channel layer 33.

[0198] In this embodiment, the material of the interlayer dielectric layer 170 is silicon oxide. The material of the interlayer dielectric layer 170 can also be other insulating materials.

[0199] In this embodiment, the interlayer dielectric layer 170 also exposes the top of the dummy gate structure 60 to facilitate subsequent removal of the dummy gate structure 60.

[0200] In this embodiment, the interlayer dielectric layer 170 also covers the isolation layer 120 (i.e., the second isolation layer 122) of the second region II.

[0201] refer to Figure 28 and Figure 29 , Figure 28 It is a 3D image. Figure 29 for Figure 28 A cross-sectional view along the XX direction shows the removal of the pseudo-gate structure 60, forming a gate opening 140, which exposes the stacked structure 30.

[0202] The gate opening 140 provides space for forming the gate structure. The gate opening 140 exposes the stacked structure 30 to facilitate the subsequent removal of the occupant layer 32 in the channel stack 31 through the gate opening 140.

[0203] In this embodiment, the gate opening 140 spans the stacked structure 30 and is located in the interlayer dielectric layer 170.

[0204] Continue to refer to Figure 28 and Figure 29 The occupant layer 32 is removed through the gate opening 140 to form a through groove 160. The through groove 160 is surrounded by adjacent channel layers 33, or by the channel layers 33 and the isolation layer 120.

[0205] The through-slot 160 and the gate opening 140 together provide space for forming the gate structure. The through-slot 160 is connected to the gate opening 140.

[0206] The occupant layer 32 is removed after the source / drain doped layer 130 is formed. Therefore, after the occupant layer 32 is removed, the two ends of the channel layer 33 are connected to the source / drain doped layer 130 along the direction of the protrusion 10. The channel layer 33 is suspended in the gate opening 140 so that the subsequent gate structure can surround the channel layer 33.

[0207] In this embodiment, a vapor etching process is used to remove the occupant layer 32. Specifically, the channel layer 33 is made of Si, and the occupant layer 32 is made of SiGe. Therefore, removing the occupant layer 32 exposed by the gate opening 140 using HCl vapor is beneficial because HCl vapor has a high etching selectivity between SiGe and Si, which helps to improve the removal efficiency of the occupant layer 32 and reduce the probability of damage to the channel layer 33.

[0208] refer to Figure 30 and Figure 31 , Figure 30 It is a 3D image. Figure 31 for Figure 30 A cross-sectional view along the XX direction. A gate structure 150 is filled within the gate opening 140 and the through-slot 160. The gate structure 150 surrounds the channel layer 33 and is also located on top of and across the fill layer 200.

[0209] When the device is in operation, the gate structure 150 is used to control the opening and closing of the conductive channel.

[0210] The gate structure 150 is also located on top of the filling layer 200 and spans the filling layer 200, thereby achieving isolation between the gate structure 150 and the protrusion 10 through the filling layer 200, thereby preventing the gate structure 150 and the protrusion 10 from forming a parasitic device, and correspondingly preventing leakage current channels generated in the protrusion 10, thus optimizing the performance of the semiconductor structure.

[0211] In this embodiment, the gate structure 150 is a metal gate structure, which includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through-slot 160 and the gate opening 140.

[0212] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0213] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0214] The work function layer is used to adjust the work function of the gate structure 150, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0215] The gate electrode layer is used as an external electrode for electrical connection between the gate structure 150 and external circuitry. The material of the gate electrode layer is a conductive material, including one or more of TiN, TaN, Ti, Ta, TiAl, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0216] In this embodiment, a metal gate structure 150 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0217] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; Multiple protrusions protrude from the substrate; An isolation layer is located on the protrusion and extends along the direction of the protrusion. The isolation layer includes a first region and a second region located on both sides of the first region. A filling layer is located on the first region of the isolation layer; A channel structure layer is located above the filler layer and suspended from the filler layer at a distance. The channel structure layer includes one or more channel layers arranged at intervals in sequence, and the channel layers are stacked in a direction perpendicular to the surface of the substrate. An insulating layer is located on the substrate and surrounds the protrusion, the isolation layer, and the filler layer, the insulating layer covering the sidewalls of the isolation layer and the filler layer and exposing the channel structure layer; A gate structure is located on the insulating layer and spans the channel structure layer and surrounds the channel layer; the gate structure is also located on top of the fill layer and spans the fill layer. The source and drain doped layers are located on the filling layers on both sides of the gate structure and are in contact with the end of each channel layer in the channel structure layer along the extension direction.

2. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes: a first portion located between the fill layer and a channel layer adjacent to the fill layer, or located between adjacent channel layers in the channel structure layer; and a second portion spanning the channel structure layer. The semiconductor structure further includes: an inner sidewall located on the sidewall of the first portion and exposing the end of each channel layer in the channel structure layer; and a gate sidewall located on the sidewall of the second portion and exposing the end of each channel layer in the channel structure layer.

3. The semiconductor structure as described in claim 2, characterized in that, The material of the inner wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride; The material of the gate sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the protrusion includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the insulating layer includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride; The filling layer is made of one or more of the following materials: silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. The material of the channel structure layer includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The insulating layer is made of one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride.

5. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

6. The semiconductor structure as described in claim 5, characterized in that, The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

7. The semiconductor structure as described in claim 1, characterized in that, The channel layer extends laterally, and the lateral width of the filling layer located between the source / drain doped layer and the isolation layer is 5 nm to 10 nm.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a plurality of protrusions protruding from the substrate, wherein a sacrificial layer, an etch stop layer and a stacked structure are sequentially formed on the protrusions, wherein the etch stop layer is made of a semiconductor material, and the stacked structure includes one or more channel stacks stacked sequentially from bottom to top, each channel stack including a placeholder layer and a channel layer located on the placeholder layer; An insulating layer is formed on the substrate surrounding the protrusion, the sacrificial layer, and the etch stop layer; A pseudo-gate structure is formed on the insulating layer that spans the stacked structure; Grooves are formed in the stacked structures on both sides of the pseudo-gate structure, and the bottom of the grooves exposes the etching stop layer; A protective sidewall is formed on the sidewall of the groove, and the protective sidewall covers a portion of the top surface of the etching stop layer; Remove the etch stop layer exposed by the protective sidewall to expose the top surface of the sacrificial layer; The sacrificial layer is removed, and a channel is formed between the etch stop layer and the protrusion, and below the groove, the channel being surrounded by the insulating layer, the protrusion, and the etch stop layer; An isolation layer is formed within the channel; Remove the protective sidewalls located on the sidewalls of the trench layer to expose the sidewalls of the trench layer and the etch stop layers located on both sides of the pseudo gate structure; Source and drain doped layers are formed on the etch stop layers on both sides of the pseudo gate structure, and the source and drain doped layers are in contact with the end of the channel layer along the extension direction; The etching stop layer is removed to form a trench, which is surrounded by the isolation layer, the insulating layer, the stacked structure, and the source / drain doped layers located on both sides of the stacked structure. The stacked structure and the source / drain doped layers are suspended above the isolation layer. A filling layer is formed within the trench; After the filling layer is formed, the dummy gate structure is removed to form a gate opening, exposing the stacked structure; The occupant layer is removed through the gate opening to form a through-slot, which is surrounded by adjacent channel layers or by the channel layers and the fill layer. A gate structure is filled within the gate opening and the through-slot, the gate structure surrounding the channel layer, and the gate structure also being located on top of and across the fill layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for forming the etching stop layer includes an epitaxial process.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the protective sidewall, the thickness of the protective sidewall is 5 nm to 10 nm.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the semiconductor structure further includes: after forming the source / drain doped layer and before removing the sacrificial layer, removing the portion of the thickness of the insulating layer and the isolation layer exposed by the dummy gate structure and the source / drain doped layer, thereby exposing the sidewalls of the etch stop layer.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching stop layer is removed using an isotropic etching process.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The material of the etch stop layer includes one or more of the following: single crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of removing the sacrificial layer includes: removing the sacrificial layer located at the bottom of the groove; and after removing the sacrificial layer located at the bottom of the groove, removing the sacrificial layer located below the stacked structure.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, An anisotropic etching process is used to remove the sacrificial layer located at the bottom of the groove; An isotropic etching process is used to remove the sacrificial layer located beneath the stacked structure.

16. The method for forming a semiconductor structure as claimed in claim 8, wherein the method for forming the semiconductor structure further comprises: After forming grooves in the stacked structures on both sides of the pseudo-gate structure and before forming the protective sidewalls, the occupant layer with a portion of its thickness exposed by the groove sidewalls is removed along the extension direction of the trench layer to form an inner trench. In the step of forming the protective sidewall, the protective sidewall is also filled in the inner trench; The method for forming the semiconductor structure further includes: in the step of removing the protective sidewall located on the sidewall of the channel layer, retaining the remaining protective sidewall filled in the inner trench as an inner sidewall.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the isolation layer includes: filling a first isolation layer in the channel between the etch stop layer and the protrusion; forming a second isolation layer in the channels on both sides of the gate structure, wherein the second isolation layer and the first isolation layer are in contact to form the isolation layer.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the filling layer includes: forming a filling material layer in the trench, removing the filling material layers located on both sides of the source / drain doped layers, and leaving the remaining filling material layer filling the stacked structure and below the source / drain doped layers as the filling layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The process for removing the filling material layer located on both sides of the source / drain doped layer includes an isotropic etching process.

Images