A method for manufacturing an LED flip chip

Abstract

The application relates to the field of semiconductor electronic technology, in particular to a manufacturing method of an LED flip chip. According to the manufacturing method, an N-GaN layer, a multi-quantum well layer and a P-GaN layer are sequentially grown on a substrate, a current blocking layer and an ITO layer are sequentially prepared, Mesa step surfaces and a cutting path are simultaneously photoetched, and then the Mesa step surfaces, the cutting path, a current expansion layer, a DBR reflection layer and a metal electrode pad layer are sequentially prepared. According to the manufacturing method, the Mesa step surfaces and the cutting path are simultaneously photoetched, so that exposure deviation is reduced, and the area of the GaN layer and the area of ITO on the GaN layer are maximally reserved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor electronic technology, in particular to a manufacturing method of LED flip chip. BACKGROUND

[0002] LED is the abbreviation of Light Emitting Diode, which is called light emitting diode in Chinese. The composition products can be seen everywhere in life. With the update iteration of technology, the demand and research and development of LED chips gradually increase. In the case of multilayer film lamination, the light emitting film layer and the conducting film layer are affected by the photoetching deviation, and a relatively wide window needs to be reserved.

[0003] The Chinese invention patent with publication number CN106025010A discloses a flip LED chip based on conductive DBR structure and a manufacturing method thereof. A buffer layer, an N-GaN layer, an active layer and a P-GaN layer are sequentially grown on a substrate. The active layer and the P-GaN layer are etched to form a Mesa step and partially expose the N-GaN layer. A DBR conductive reflection layer and a metal reflection layer are sequentially formed on the P-GaN layer step by evaporation and etching. An N metal conductive layer and a current expansion strip are arranged on the exposed part of the N-GaN layer. An insulating layer is formed above the metal reflection layer and above the N metal conductive layer and the exposed part of the N-GaN layer. A plurality of through holes are etched on the insulating layer. A P common gold layer and an N common gold layer are arranged on the insulating layer, respectively. The P common gold layer is connected with the metal reflection layer through the through hole, and the N common gold layer is connected with the N metal conductive layer through the through hole. The insulating layer isolates the N metal conductive layer from the P common gold layer and isolates the DBR conductive reflection layer from the N common gold layer. The preparation method improves the light emitting reliability of the light emitting diode product and reduces the process difficulty and manufacturing cost.

[0004] However, the preparation method needs to perform multiple photoetching, is affected by the exposure machine alignment accuracy, and sets a photoetching deviation window of about 4 μm for each photoetching. That is, the film layer pattern in the subsequent process and the Mesa pattern or the alignment pattern need to be offset by no more than ± 2 μm, otherwise it is easy to cause electric leakage or other electrical problems, so the more the number of photoetching, the greater the manufacturing difficulty. Moreover, the multiple film layers all need to reserve the photoetching deviation window, which causes great waste of light emitting area. SUMMARY

[0005] In order to overcome the defects of the above-mentioned prior art, the technical problem to be solved by the present application is to provide a manufacturing method of LED flip chip. The LED flip chip prepared by the method has less photoetching times and large light emitting area.

[0006] In order to solve the above technical problems, the technical scheme adopted by the present application is as follows: a manufacturing method of LED flip chip, comprising the following steps:

[0007] S1: sequentially growing an N-GaN layer, a multi-quantum well layer and a P-GaN layer on a substrate;

[0008] S2: preparing a current blocking layer above the P-GaN layer;

[0009] S3: evaporating an ITO layer above the current blocking layer;

[0010] S4: obtaining a Mesa lithography pattern and a cutting path pattern after lithography;

[0011] S5: etching using an ITO etching solution first, then etching to obtain a Mesa step surface, and synchronously etching the upper layer of the cutting path pattern;

[0012] S6: covering and protecting the exposed N-GaN layer using a positive photoresist, and obtaining a cutting path after etching;

[0013] S7: forming a current spreading layer on the exposed portions of the N-GaN layer and the P-GaN layer by evaporation;

[0014] S8: forming a DBR reflection layer above the P-GaN layer by evaporation and etching;

[0015] S9: evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole to connect and conduct with the current spreading layer.

[0016] The LED flip chip manufacturing method has the advantages that the current blocking layer and the ITO layer are prepared first, then the Mesa step surface and the cutting path are synchronously lithographed, the manufacturing steps are exchanged, a prerequisite for synchronous lithography is provided, the number of lithography is reduced, the exposure deviation is reduced, the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon are maximized, the light emitting efficiency is increased, and the brightness is improved. Reducing the number of lithography can also reduce the multi-path processing flow, shorten the processing time, and save labor and equipment costs. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 Fig. 2 shows a product structure schematic diagram of S2 of the LED flip chip manufacturing method of the embodiment of the present application;

[0018] Figure 2 Fig. 3 shows a product structure schematic diagram of S3 of the LED flip chip manufacturing method of the embodiment of the present application;

[0019] Figure 3 Fig. 5 shows a product structure schematic diagram of S5 of the LED flip chip manufacturing method of the embodiment of the present application;

[0020] Figure 4The figure shows a product structure schematic diagram of S6 of the LED flip chip manufacturing method of the embodiment of the present application;

[0021] Figure 5 The figure shows a product structure schematic diagram of S7 of the LED flip chip manufacturing method of the embodiment of the present application;

[0022] Figure 6 The figure shows a product structure schematic diagram of S8 of the LED flip chip manufacturing method of the embodiment of the present application;

[0023] Figure 7 The figure shows a product structure schematic diagram of S9 of the LED flip chip manufacturing method of the embodiment of the present application;

[0024] Label explanation: 1, substrate; 2, N-GaN layer; 3, multi-quantum well layer; 4, P-GaN layer; 5, current blocking layer; 6, ITO layer; 7, current spreading layer; 8, DBR reflection layer; 9, metal electrode pad layer; 10, cutting path; EMBODIMENT

[0025] To make the technical content, the purposes and effects of the present application clear, the following will be described in conjunction with the embodiments and the accompanying drawings.

[0026] The most key idea of the present application is to synchronize the Mesa step surface and the cutting path with the photoetching operation, so as to reduce the exposure deviation and maximize the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon.

[0027] Please refer to Figures 1 to 7 The figure shows a LED flip chip manufacturing method of the present application, which comprises the following steps:

[0028] S1: growing N-GaN layer, multi-quantum well layer and P-GaN layer on the substrate in sequence;

[0029] S2: preparing a current blocking layer above the P-GaN layer;

[0030] S3: evaporating an ITO layer above the current blocking layer;

[0031] S4: getting Mesa photoetching pattern and cutting path pattern after photoetching;

[0032] S5: etching first using ITO etching liquid, then etching to get Mesa step surface and synchronously etching the upper layer of the cutting path pattern;

[0033] S6: covering the exposed N-GaN layer with positive photoresist, and getting the cutting path after etching;

[0034] S7: Forming a current spreading layer by evaporation on the exposed part of the N-GaN layer and the P-GaN layer;

[0035] S8: Forming a DBR reflection layer by evaporation and etching on the P-GaN layer;

[0036] S9: Evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole connected to the current spreading layer.

[0037] From the above description, the beneficial effects of the present application are that DBR is also known as distributed Bragg reflector. The existing manufacturing method of LED flip chip first prepares a Meas step surface, a cutting channel, a current blocking layer and an ITO layer. The manufacturing steps of the present application are exchanged, the current blocking layer and the ITO layer are prepared first, and then the Mesa step surface and the cutting channel are simultaneously photolithography, which reduces the number of photolithography, reduces the exposure deviation, thereby reducing the etched P-GaN and ITO, maximizing the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon, increasing the light emitting efficiency and improving the brightness. Reducing the number of photolithography can also reduce the multi-channel processing flow, shorten the processing time, save labor and equipment costs.

[0038] The cutting channel includes a Masa cutting channel and an ISO cutting channel. The present application simultaneously photolithography and etches the two cutting channels, reduces the number of photolithography, and increases the light emitting efficiency.

[0039] Further, the specific steps of S2 are:

[0040] S21: Depositing silicon dioxide on the surface of the P-GaN layer;

[0041] S22: Photolithography of the silicon dioxide;

[0042] S23: Corrosion with BOE etching solution (high-purity ammonium fluoride etching solution), degumming, to obtain a current blocking layer.

[0043] Further, the deposition thickness of the silicon dioxide in S2 is

[0044] As can be seen from the above description, 2100-3000 can meet the demand for current blocking, and excessive thickness prolongs the deposition time, causing waste of production capacity.

[0045] Further, the specific steps of S4 are: coating a positive photoresist, and then preparing a Mesa photolithography pattern and a cutting channel pattern after exposure and development.

[0046] Further, in S4, the coating thickness of the positive photoresist is 90-110 μm, and the exposure dose of the exposure is 140-160 mj. Preferably, the coating thickness of the positive photoresist is 100 μm, and the exposure dose of the exposure is 150 mj.

[0047] Further, in S4 and S5, overlay is obtained.

[0048] Further, the width of the scribe lane pattern is 3.5-4.5 μm. Preferably, the width of the scribe lane pattern is 4 μm.

[0049] As can be seen from the above description, the smaller the scribe lane pattern, the higher the yield of the chip; but when the scribe lane pattern is too small, the cutting tool is difficult to accurately position.

[0050] Further, the side etching amount of the ITO etching solution is 5-7 μm.

[0051] As can be seen from the above description, the core particle spacing of ITO obtained by the prior art is 34 μm, but under the photolithography process of the present application, the spacing can be reduced to 18-22 μm, i.e. the single-side ITO is enlarged by 7 μm, increasing the luminous area of the chip.

[0052] Further, in S5, the ITO etching solution is used for etching, and the etching time is 60-70 s + 30-40 s (two times of etching, one time of etching is 60-70 s, and one time of etching is 30-40 s).

[0053] As can be seen from the above description, in the prior art, the etching time of the ITO etching solution is 50-60 s + 20-30 s, and the etching time is prolonged to adapt to the increased thickness of the coating photoresist.

[0054] Further, in S5, the etching depth of the Mesa step surface is

[0055] Further, in S6, chlorine gas is used for etching, the etching time is 900 s, the gas flow is 155 cfm, and the etching depth is

[0056] As can be seen from the above description, in the original ISO etching, the etching time is 1800 s, and the etching time is shortened to adapt to the synchronous etching of the ISO scribe lane and the Mesa scribe lane.

[0057] Further, in S6, the width of the scribe lane is 14-18 μm.

[0058] As can be seen from the above description, the smaller the scribe lane, the higher the yield of the chip; the minimum width of the scribe lane is determined by the cutting tool.

[0059] Further, the current spreading layer is composed of a metal electrode composed of an N-GaN layer and a P-GaN layer.

[0060] Further, the DBR reflection layer is composed of SiO2 and Ti3O5 arranged alternately.

[0061] Further, the DBR reflection layer is composed of SiO2 and Ti3O5 arranged alternately in ABAB mode for 47 layers.

[0062] Please refer to Figures 1 to 7 The embodiment one of the present application is a manufacturing method of LED flip chip, comprising the following steps:

[0063] S1: growing N-GaN layer 2, multi-quantum well layer 3 and P-GaN layer 4 on substrate 1 in sequence;

[0064] S2: preparing current blocking layer 5 above P-GaN layer:

[0065] S21: depositing silicon dioxide on the surface of P-GaN layer;

[0066] S22: performing photoetching on the silicon dioxide;

[0067] S23: etching by using BOE etching liquid, and removing glue to obtain current blocking layer 5 and first etching;

[0068] S3: evaporating ITO layer 6 above the current blocking layer;

[0069] S4: coating 100 μm positive photoresist, drying at 110 ℃ for 90 s, and then preparing Mesa etching pattern, cutting path pattern and second etching pattern by sequentially going through exposure of 150 mj exposure amount, development at 135 ℃ for 120 s; the width of cutting path pattern is 4 μm;

[0070] S5: etching by using ITO etching liquid, the side etching amount of ITO etching liquid is 5-7 μm, etching twice, the etching time of one time is 65 s, and the etching time of one time is 35 s; then etching to obtain Mesa step surface and second etching, and synchronously etching the upper layer of cutting path pattern; the etching depth of Mesa step surface is

[0071] S6: covering and protecting second etching and exposed N-GaN layer by using positive photoresist, and obtaining cutting path 10 after etching, the width of cutting path is 16 μm; etching by using chlorine gas, the etching time is 900 s, the gas flow is 155 cfm, and the etching depth is

[0072] ​S7: Forming a current spreading layer 7 by evaporation on the exposed parts of the N-GaN layer 2 and the P-GaN layer 4, the current spreading layer being composed of metal electrodes of the N-GaN layer 2 and the P-GaN layer 4;

[0073] S8: Forming a DBR reflection layer 8 by evaporation and etching on the P-GaN layer, the DBR reflection layer 8 being composed of 47 layers of SiO2 and Ti3O5 arranged alternately in the manner of ABAB;

[0074] S9: Evaporating P-type and N-type pads to obtain a metal electrode pad layer 9, and injecting DBR etching holes to connect and conduct with the current spreading layer 7.

[0075] The performance test of the LED flip chip of the embodiment one shows that the ITO interval is 20 μm, the ITO overall area is 86400 μm 2 .

[0076] Therefore, the ITO interval of the conventional LED flip chip is generally 34 μm, and the ITO overall area is about 77356 μm 2 .Compared with the conventional LED flip chip, the ITO overall area of the LED flip chip obtained by the application is enlarged by 9044 μm 2 (about 11.7%), and the brightness ratio is improved by about 3.44%.

[0077] The embodiment two of the application is a manufacturing method of an LED flip chip, comprising the following steps:

[0078] S1: Growing an N-GaN layer, a multi-quantum well layer and a P-GaN layer on a substrate in sequence;

[0079] S2: Preparing a current blocking layer on the P-GaN layer:

[0080] S21: Depositing silicon dioxide on the surface of the P-GaN layer;

[0081] S22: Performing photoetching on the silicon dioxide;

[0082] S23: Carrying out etching and glue removal by using a BOE etching liquid to obtain the current blocking layer and a first etching mask.

[0083] S3: Evaporating an ITO layer on the current blocking layer;

[0084] S4: Coating a positive photoresist of 90 μm, performing drying at 110 ℃ for 90 s, and then preparing Mesa photoetching patterns, cutting path patterns and a second etching mask in sequence after exposure at an exposure amount of 140 mj and development at 135 ℃ for 120 s; the width of the cutting path patterns is 3.5 μm;

[0085] S5: etching by using ITO etching liquid, the side etching amount of the ITO etching liquid is 5-7 μm, etching twice, the etching time of one time is 60 s, and the etching time of one time is 30 s; then etching to obtain a Mesa step surface and a second set of etching, and the upper layer of a cutting path pattern is etched synchronously; the etching depth of the Mesa step surface is

[0086]

[0087] S6: covering and protecting the second set of etching and the exposed N-GaN layer by using a positive photoresist, obtaining a cutting path after etching, the width of the cutting path is 14 μm; etching by using chlorine gas, the etching time is 900 s, the gas flow is 155 cfm, and the etching depth is

[0088] S7: forming a current spreading layer on the exposed parts of the N-GaN layer and the P-GaN layer by evaporation, the current spreading layer is composed of a metal electrode of the N-GaN layer and the P-GaN layer;

[0089] S8: forming a DBR reflection layer above the P-GaN layer by evaporation and etching, the BR reflection layer is composed of 47 layers of SiO2 and Ti3O5 arranged alternately in the ABAB mode;

[0090] S9: evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole to connect and conduct with the current spreading layer.

[0091] Embodiment three of the application is a manufacturing method of an LED flip chip, comprising the following steps:

[0092] S1: growing an N-GaN layer, a multi-quantum well layer and a P-GaN layer on a substrate in sequence;

[0093] S2: preparing a current blocking layer above the P-GaN layer:

[0094] S21: depositing silicon dioxide on the surface of the P-GaN layer;

[0095] S22: performing photoetching on the silicon dioxide;

[0096] S23: etching by using a BOE etching liquid, and removing glue to obtain a current blocking layer and a first set of etching.

[0097] S3: evaporating an ITO layer above the current blocking layer;

[0098] ​S4: coating 110 mu m of positive photoresist, drying at 110 DEG C for 90 s, and then sequentially performing exposure at 160 mj exposure amount, developing at 135 DEG C for 120 s to prepare Mesa photoetching pattern, cutting path pattern and the second set of etching pattern; the width of the cutting path pattern is 4.5 mu m;

[0099] S5: first, using ITO etching solution for corrosion, the side etching amount of ITO etching solution is 5-7 mu m, and the corrosion is carried out twice, one time is 70 s, and the other time is 40 s; then, etching to obtain Mesa step surface and the second set of etching, and synchronously etching the upper layer of the cutting path pattern; the etching depth of the Mesa step surface is

[0100]

[0101] S6: using positive photoresist to cover and protect the second set of etching and the exposed N-GaN layer, and then etching to obtain the cutting path, the width of the cutting path is 18 mu m; during etching, chlorine gas is used for etching, the etching time is 900 s, the gas flow is 155 cfm, and the etching depth is

[0102] S7: forming a current spreading layer on the exposed portions of the N-GaN layer and the P-GaN layer by evaporation, and the current spreading layer is composed of metal electrodes of the N-GaN layer and the P-GaN layer;

[0103] S8: forming a DBR reflection layer above the P-GaN layer by evaporation and etching, and the BR reflection layer is composed of 47 layers of SiO2 and Ti3O5 arranged alternately in the ABAB mode;

[0104] S9: evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole to connect and conduct with the current spreading layer.

[0105] In summary, the manufacturing method of the LED flip chip provided by the application first sequentially prepares a current blocking layer and an ITO layer, and then synchronously photoetches a Mesa step surface and a cutting path. The application provides a prerequisite for synchronous photoetching by changing the manufacturing steps and changing the thickness of the photoresist and other process parameters, synchronous photoetching reduces the number of photoetching, thereby reducing exposure deviation and reducing the etched P-GaN and ITO, so as to maximize the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon, increase the light-emitting efficiency, and improve the brightness. Reducing the number of photoetching can also reduce the multi-path processing flow, shorten the processing time, and save labor and equipment costs.

[0106] The above only describes the embodiments of the application, and does not limit the patent scope of the application, any equivalent transformation or direct or indirect application in the related technical field based on the content of the specification and drawings of the application is also included in the patent protection scope of the application.

Claims

1. A method of manufacturing an LED flip chip, characterized by, The method comprises the following steps: S1: sequentially growing an N-GaN layer, a multi-quantum well layer and a P-GaN layer on a substrate; S2: preparing a current blocking layer above the P-GaN layer; S3: evaporating an ITO layer above the current blocking layer; S4: obtaining a Mesa lithography pattern and a cutting path pattern after photoetching; S5: etching the Mesa step surface by using an ITO etching solution, and synchronously etching the upper layer of the cutting path pattern; S6: covering and protecting the exposed N-GaN layer by using a positive photoresist, and obtaining the cutting path after etching; S7: forming a current spreading layer by evaporation on the exposed parts of the N-GaN layer and the P-GaN layer; S8: forming a DBR reflection layer by evaporation and etching above the P-GaN layer; S9: evaporating P-type and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole to connect and conduct with the current spreading layer.

2. The method of claim 1, wherein The specific steps of S2 are: S21: depositing silicon dioxide on the surface of the P-GaN layer; S22: photoetching the silicon dioxide; S23: etching and removing the photoresist by using a BOE etching solution to obtain the current blocking layer.

3. The method of claim 1, wherein The specific steps of S4 are: coating a positive photoresist, and then preparing the Mesa lithography pattern and the cutting path pattern by sequentially performing exposure and development.

4. The method of claim 3, wherein In S4, the coating thickness of the positive photoresist is 90-110 μm, and the exposure amount of the exposure is 140-160 mj.

5. The method of claim 1, wherein the LED flip chip is manufactured by the steps of: The width of the cutting path pattern is 3.5-4.5 μm.

6. The method of claim 1, wherein The side etching amount of the ITO etching solution is 5-7 μm.

7. The method of claim 1, wherein the LED flip chip is manufactured by a method comprising: The width of the cutting path in S6 is 14-18 μm.

8. The method of claim 1, wherein the LED flip chip is manufactured by a method comprising: The current spreading layer is composed of a metal electrode of the N-GaN layer and the P-GaN layer.

9. The method of claim 1, wherein The DBR reflection layer is composed of SiO2 and Ti3O5 arranged alternately.

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