A high-speed latch comparator and its bias circuit

Abstract

The present invention belongs to the technical field of comparators, and specifically relates to a high-speed latch comparator and its bias circuit. The present invention adopts a structure of a preamplifier plus a latch, and introduces a coupling capacitor in the latch to increase the transconductance of the transistor and improve the speed of the latch. The introduction of the preamplifier isolates the input signal and the output signal, reduces the kickback noise, and can provide a certain gain and bandwidth. The present invention also designs a bias circuit for the comparator, through which the current of the preamplifier and latch of the comparator can be adjusted, thereby controlling the speed and power consumption of the comparator. The present invention can be used in analog-to-digital converters, especially pipelined analog-to-digital converters.

Description

Technical Field

[0001] The present invention belongs to the technical field of comparators, and in particular relates to a high-speed latch comparator and a bias circuit thereof. Background Art

[0002] Comparators are commonly used modules in analog integrated circuits and are widely found in analog-to-digital converters. They generate digital logic outputs by comparing differential input analog signals. The speed and accuracy of a comparator are directly related to its power consumption. Controlling the comparator's current can achieve control over the power consumption, speed, and accuracy of the comparator. As the core module of an analog-to-digital converter, especially a pipelined one, the comparator's speed and comparison accuracy directly impact the performance of the pipelined converter. A pipelined converter consists of multiple sub-stage analog-to-digital converters, and the performance requirements of the circuits within each sub-stage decrease as the number of stages increases. This characteristic of pipelined converters can be exploited to achieve a trade-off between comparator power consumption and speed by providing different bias currents to the different sub-stage analog-to-digital converters. Summary of the Invention

[0003] In view of this, the present invention proposes a high-speed latch comparator and its bias circuit. The comparator structure is as follows Figure 1 As shown in the figure, a preamplifier plus high-speed latch structure is used, in which the preamplifier isolates the input signal from the latch, reduces the kickback noise and provides a certain gain and bandwidth. The high-speed latch introduces a cross-coupling capacitor to increase the transconductance of the transistor in the amplification unit of the latch, thereby increasing the speed of the comparator. The structure of the bias circuit is shown in the figure. Figure 2 As shown, bias voltages VB1 and VB2 can be generated by adjusting the first current source I1 and the second current source I2. The bias voltages bias the preamplifier, thereby indirectly controlling the currents of the preamplifier and the latch.

[0004] The technical solution of the present invention is:

[0005] A high-speed latch comparator and a bias circuit thereof, comprising a preamplifier, a latch, and a bias circuit;

[0006] The preamplifier is arranged between the input signal and the latch, and is used to isolate the input signal from the latch and amplify the signal, thereby reducing the kickback noise and providing a certain gain and bandwidth;

[0007] The latch is used to receive and compare the amplified signal output by the preamplifier;

[0008] The bias circuit is used to provide a bias voltage to the preamplifier and simultaneously adjust the current of the preamplifier and the latch.

[0009] Furthermore, the preamplifier includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5;

[0010] The gate of the first NMOS transistor MN1 is connected to the input positive signal, the source is connected to the drain of the fifth NMOS transistor MN5, the drain of the first NMOS transistor MN1 is the negative signal output terminal of the preamplifier, and the drain of the first NMOS transistor MN1 is connected to the source of the third NMOS transistor MN3;

[0011] The gate of the second NMOS transistor MN2 is connected to the input negative signal, the source is connected to the drain of the fifth NMOS transistor MN5, the drain of the second NMOS transistor MN2 is the positive signal output terminal of the preamplifier, and the second NMOS transistor MN2 is connected to the source of the fourth NMOS transistor MN4;

[0012] The gate of the third NMOS transistor MN3 is connected to the second bias voltage VB2, and the drain is connected to the first power supply VDD1;

[0013] The gate of the fourth NMOS transistor MN4 is connected to the second bias voltage VB2, and the drain is connected to the first power supply VDD1;

[0014] The gate of the fifth NMOS transistor MN5 is connected to the first bias voltage VB1 , and the source is connected to the ground.

[0015] Furthermore, the latch includes a first PMOS transistor MP1, a second PMOS transistor MP2, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a first capacitor C1, and a second capacitor C2;

[0016] The gate of the first PMOS transistor MP1 is the positive signal output terminal of the latch, connected to the drains of the second PMOS transistor MP2, the tenth NMOS transistor MN10, and the seventh NMOS transistor MN7. The source of the first PMOS transistor MP1 is connected to the first power supply VDD1. The drain of the first PMOS transistor MP1 is the negative signal output terminal of the latch. The drain of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, the source of the tenth NMOS transistor MN10, and the drain of the sixth NMOS transistor MN6.

[0017] The gate of the second PMOS transistor MP2 is the negative signal output terminal of the latch, connected to the drains of the first PMOS transistor MP1 and the sixth NMOS transistor MN6, and the source of the tenth NMOS transistor MN10. The source of the second PMOS transistor MP2 is connected to the first power supply VDD1. The drain of the second PMOS transistor MP2 is the positive signal output terminal of the latch. The drain of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, the drain of the tenth NMOS transistor MN10, and the drain of the seventh NMOS transistor MN7.

[0018] The sixth NMOS transistor MN6 receives the positive output signal of the preamplifier through the eighth NMOS transistor MN8. The gate of the sixth NMOS transistor MN6 is connected to the source of the eighth NMOS transistor MN8 and the second connection terminal of the first capacitor C1. The source of the sixth NMOS transistor MN6 is connected to ground. The drain of the sixth NMOS transistor MN6 is the negative signal output terminal of the latch. The drain of the sixth NMOS transistor MN6 is connected to the drain of the first PMOS transistor MP1, the source of the tenth NMOS transistor MN10, and the first connection terminal of the second capacitor C2.

[0019] The gate of the seventh NMOS transistor MN7 is connected to the source of the ninth NMOS transistor MN9 and the second connection terminal of the second capacitor C2. The source of the seventh NMOS transistor MN7 is connected to ground. The drain of the seventh NMOS transistor MN7 is the positive signal output terminal of the latch. The drain of the seventh NMOS transistor MN7 is connected to the drain of the second PMOS transistor MP2, the drain of the tenth NMOS transistor MN10, and the first connection terminal of the first capacitor C1.

[0020] The gate of the eighth NMOS transistor MN8 is connected to the latch clock signal, the source is connected to the gate of the sixth NMOS transistor MN6 and the second connection end of the first capacitor C1, and the drain of the eighth NMOS transistor MN8 is connected to the positive output signal of the preamplifier;

[0021] The gate of the ninth NMOS transistor MN9 is connected to the latch clock signal, the source is connected to the gate of the seventh NMOS transistor MN7 and the second connection end of the second capacitor C2, and the drain of the ninth NMOS transistor MN9 is connected to the negative output signal of the preamplifier;

[0022] The gate of the tenth NMOS transistor MN10 is connected to the Latch clock signal, the source is the negative signal output terminal of the latch, and is connected to the drains of the first PMOS transistor MP1 and the sixth NMOS transistor MN6, and the first connection terminal of the second capacitor C2. The drain of the tenth NMOS transistor MN10 is the positive signal output terminal of the latch, and the drain of the tenth NMOS transistor MN10 is connected to the drains of the second PMOS transistor MP2 and the seventh NMOS transistor MN7, and the first connection terminal of the first capacitor C1.

[0023] Furthermore, the bias circuit includes a first current source I1, a second current source I2, a first amplifier AMP1, a second amplifier AMP2, a third PMOS transistor MP3, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16;

[0024] The first connection end of the first current source I1 is connected to the second power supply voltage VDD2, the second connection end outputs the first bias voltage VB1, and the second connection end is connected to the gates of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 and the drain of the thirteenth NMOS transistor MN13;

[0025] The first connection end of the second current source I2 is connected to the second power supply voltage VDD2, and the second connection end is connected to the source and gate of the third PMOS transistor MP3 and the negative input end of the second amplifier AMP2;

[0026] The positive input terminal of the first amplifier AMP1 is connected to the gate of the sixteenth NMOS transistor MN16, the negative input terminal is connected to the drain of the fourteenth NMOS transistor MN14 and the source of the fifteenth NMOS transistor MN15, the output terminal of the first amplifier AMP1 outputs the second bias voltage VB2, and the output terminal of the first amplifier AMP1 is connected to the gate of the fifteenth NMOS transistor MN15;

[0027] The positive input terminal of the second amplifier AMP2 is connected to the first power supply voltage VDD1, and the negative input terminal is connected to the second connection terminal of the second power supply I2 and the source and drain of the third PMOS transistor MP3;

[0028] The gate and source of the third PMOS transistor MP3 are connected to each other, and are connected to the negative input terminal of the second amplifier AMP2 and the second connection terminal of the second power supply I2;

[0029] The gate of the eleventh NMOS transistor MN11 is connected to the second connection terminal of the first current source I1 and the gate of the twelfth NMOS transistor MN12 , the source of the eleventh NMOS transistor MN11 is connected to the ground, and the drain of the eleventh NMOS transistor MN11 is connected to the source of the thirteenth NMOS transistor MN13 ;

[0030] The gate of the twelfth NMOS transistor MN12 is connected to the second connection terminal of the first current source I1 and the gate of the eleventh NMOS transistor MN11 , the source of the twelfth NMOS transistor MN12 is connected to the ground, and the drain of the twelfth NMOS transistor MN12 is connected to the source of the fourteenth NMOS transistor MN14 ;

[0031] The gate of the thirteenth NMOS transistor MN13 is the preamplifier input common mode voltage VCM terminal, the gate of the thirteenth NMOS transistor MN13 is connected to the gate of the fourteenth NMOS transistor MN14, the source of the thirteenth NMOS transistor MN13 is connected to the drain of the eleventh NMOS transistor MN11, and the drain of the thirteenth NMOS transistor MN13 is connected to the second connection terminal of the first current source I1 and the gates of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12;

[0032] The source of the fourteenth NMOS transistor MN14 is connected to the drain of the twelfth NMOS transistor MN12 , and the drain of the fourteenth NMOS transistor MN14 is connected to the source of the fifteenth NMOS transistor MN15 and the negative input terminal of the first amplifier AMP1 ;

[0033] The gate of the fifteenth NMOS transistor MN15 is connected to the output terminal of the first amplifier AMP1, and the source of the fifteenth NMOS transistor MN15 is connected to the drain of the fourteenth NMOS transistor MN14 and the negative input terminal of the first amplifier AMP1;

[0034] The gate of the sixteenth NMOS transistor MN16 is connected to the positive input terminal of the first amplifier AMP1 and the output terminal of the second amplifier AMP2 , the source of the sixteenth NMOS transistor MN16 is grounded, and the drain of the sixteenth NMOS transistor MN16 is connected to the drain of the third PMOS transistor MP3 .

[0035] Beneficial effects of the present invention: The present invention designs a high-speed latch comparator with a preamplifier and its bias circuit. The preamplifier can isolate the input signal from the latch, reduce kickback noise, and provide a certain gain and bandwidth. The introduction of cross-coupling capacitors in the latch can increase the latch speed. At the same time, the bias circuit of the invention can generate bias voltages VB1 and VB2 by adjusting the current. The bias voltages VB1 and VB2 provided to the preamplifier indirectly adjust the current of the preamplifier and latch, thereby achieving a compromise control between the power consumption and speed of the comparator. The present invention can be used in each sub-stage of a pipeline analog-to-digital converter. The bias circuit can bias multiple comparators simultaneously. Each sub-stage can contain a bias circuit and multiple comparators. By setting different bias currents in different sub-stages of the pipeline analog-to-digital converter, the speed and power consumption of the comparator can be adjusted, thereby achieving the purpose of controlling the power consumption and accuracy of each sub-stage in the pipeline analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic diagram of the circuit structure of a high-speed latch comparator with a preamplifier proposed by the present invention;

[0037] Figure 2 This is a schematic diagram of the circuit structure of the bias circuit of the high-speed latch comparator proposed by the present invention. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings.

[0039] The present invention proposes a high-speed latch comparator and its bias circuit, characterized by including: a preamplifier for isolating the input signal from the latch, reducing kickback noise, and providing a certain gain and bandwidth; a latch for comparing the input signal after being isolated and amplified by the preamplifier; and a bias circuit for providing a bias voltage to the preamplifier and capable of regulating the current of the preamplifier and the latch. Furthermore, the preamplifier includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5. The first NMOS transistor MN1 and the second NMOS transistor MN2 are a differential input pair for receiving and amplifying the input differential signal, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are load transistors, and the fifth NMOS transistor MN5 is a bias current source for providing bias current to the preamplifier. The gate of the first NMOS transistor MN1 is connected to the input positive signal, the source is connected to the drain of the fifth NMOS transistor MN5, the drain is the negative signal output terminal of the pre-amplifier, and is connected to the source of the third NMOS transistor MN3; the gate of the second NMOS transistor MN2 is connected to the input negative signal, the source is connected to the drain of the fifth NMOS transistor MN5, the drain is the positive signal output terminal of the pre-amplifier, and is connected to the source of the fourth NMOS transistor MN4; the gate of the third NMOS transistor MN3 is connected to the bias voltage VB2, the source is the negative signal output terminal of the pre-amplifier, connected to the drain of the first NMOS transistor MN1, and the drain is connected to the first power supply VDD1; the gate of the fourth NMOS transistor MN4 is connected to the bias voltage VB2, the source is the positive signal output terminal of the pre-amplifier, connected to the drain of the second NMOS transistor MN2, and the drain is connected to the first power supply VDD1; The gate is connected to the bias voltage VB1, the source is connected to the ground, and the drain is connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2. Further, the latch includes a first PMOS transistor MP1, a second PMOS transistor MP2, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a first capacitor C1, and a second capacitor C2. The gate of the first PMOS transistor MP1 is a positive signal output terminal of the latch, connected to the drains of the second PMOS transistor MP2, the tenth NMOS transistor MN10, and the seventh NMOS transistor MN7. The source is connected to the first power supply VDD1, and the drain is a negative signal output terminal of the latch, connected to the gate of the second PMOS transistor MP2, the source of the tenth NMOS transistor MN10, and the drain of the sixth NMOS transistor MN6.The gate of the second PMOS transistor MP2 is the latch output negative signal terminal, connected to the drains of the first PMOS transistor MP1 and the sixth NMOS transistor MN6, and the source of the tenth NMOS transistor MN10. The source is connected to the first power supply VDD1, and the drain is the latch output positive signal terminal, connected to the gate of the first PMOS transistor MP1, the drain of the tenth NMOS transistor MN10, and the drain of the seventh NMOS transistor MN7. The sixth NMOS transistor MN6 receives the output positive signal of the preamplifier through the eighth NMOS transistor MN8. The gate of the sixth NMOS transistor MN6 is connected to the source of the eighth NMOS transistor MN8 and the second connection terminal of the first capacitor C1. The source is connected to the ground, and the drain is the latch output negative signal terminal, connected to the gate of the first PMOS transistor MP1, the drain of the tenth NMOS transistor MN10, and the drain of the seventh NMOS transistor MN7. The drain of the seventh NMOS transistor MN7 is connected to the source of the ninth NMOS transistor MN9 and the second connection terminal of the second capacitor C2, the source is connected to the ground, and the drain is the latch output positive signal terminal, connected to the drain of the second PMOS transistor MP2, the drain of the tenth NMOS transistor MN10 and the first connection terminal of the first capacitor C1; the gate of the eighth NMOS transistor MN8 is connected to the latch clock signal, the source is connected to the gate of the sixth NMOS transistor MN6 and the second connection terminal of the first capacitor C1, and the drain is connected to the positive output signal of the preamplifier; the gate of the ninth NMOS transistor MN9 is connected to the latch clock signal, and the source is connected to the seventh NMOS transistor MN7 The gate of the tenth NMOS transistor MN10 is connected to the Latch clock signal, the source is the latch output negative signal terminal, connected to the drain of the first PMOS transistor MP1 and the sixth NMOS transistor MN6 and the first connection terminal of the second capacitor C2, the drain is the latch output positive signal, connected to the drain of the second PMOS transistor MP2 and the seventh NMOS transistor MN7 and the first connection terminal of the first capacitor C1; the first connection terminal of the first capacitor C1 is the latch output positive signal terminal, connected to the drain of the second PMOS transistor MP2, the seventh NMOS transistor MN7 and the tenth NMOS transistor MN10, and the second connection terminal is connected to the gate of the sixth NMOS transistor MN6 and the drain of the eighth NMOS transistor MN10. The source of the NMOS transistor MN8; the first connection end of the second capacitor C2 is the latch output negative signal terminal, connected to the first PMOS transistor MP1, the drain of the sixth NMOS transistor MN6, and the source of the tenth NMOS transistor MN10, and the second connection end is connected to the gate of the seventh NMOS transistor MN7 and the source of the ninth NMOS transistor MN9; further, the bias circuit includes a first current source I1, a second current source I2, a first amplifier AMP1, a second amplifier AMP2, a third PMOS transistor MP3, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16;The first connection terminal of the first current source I1 is connected to the second power supply voltage VDD2, and the second connection terminal is the output bias voltage VB1 terminal, which is connected to the gates of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12, and the drain of the thirteenth NMOS transistor MN13; the first connection terminal of the second current source I2 is connected to the second power supply voltage VDD2, and the second connection terminal is connected to the source and gate of the third PMOS transistor MP3 and the negative input terminal of the second amplifier AMP2; the positive input terminal of the first amplifier AMP1 is connected to the gate of the sixteenth NMOS transistor MN16, the negative input terminal is connected to the drain of the fourteenth NMOS transistor MN14 and the source of the fifteenth NMOS transistor MN15, and the output terminal The bias circuit outputs a bias voltage VB2, which is connected to the gate of the fifteenth NMOS transistor MN15; the positive input terminal of the second amplifier AMP2 is connected to the first power supply voltage VDD1, and the negative input terminal is connected to the second connection terminal of the second power supply I2 and the source and drain of the third PMOS transistor MP3; the gate and source of the third PMOS transistor MP3 are connected, and the gate and source are connected to the negative input terminal of the second amplifier AMP2 and the second connection terminal of the second power supply I2; the gate of the eleventh NMOS transistor MN11 is the output bias voltage VB1 terminal, connected to the second connection terminal of the first current source I1 and the gate of the twelfth NMOS transistor MN12, the source is connected to ground, and the drain is connected to the thirteenth NMOS transistor MN1 3; the gate of the twelfth NMOS transistor MN12 is the output bias voltage VB1 terminal, connected to the second connection terminal of the first current source I1 and the gate of the eleventh NMOS transistor MN11, the source is connected to the ground, and the drain is connected to the source of the fourteenth NMOS transistor MN14; the gate of the thirteenth NMOS transistor MN13 is the preamplifier input common mode voltage VCM terminal, connected to the gate of the fourteenth NMOS transistor MN14, the source is connected to the drain of the eleventh NMOS transistor MN11, and the drain is connected to the second connection terminal of the first current source I1 and the gates of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12; the gate of the fourteenth NMOS transistor MN14 ... The common-mode voltage VCM terminal is connected to the gate of the thirteenth NMOS transistor MN13, the source is connected to the drain of the twelfth NMOS transistor MN12, and the drain is connected to the source of the fifteenth NMOS transistor MN15 and the negative input terminal of the first amplifier AMP1; the gate of the fifteenth NMOS transistor MN15 is the output bias voltage VB2 terminal, connected to the output terminal of the first amplifier AMP1, and the source is connected to the drain of the fourteenth NMOS transistor MN14 and the negative input terminal of the first amplifier AMP1; the gate of the sixteenth NMOS transistor MN16 is connected to the positive input terminal of the first amplifier AMP1 and the output terminal of the second amplifier AMP2, the source is grounded, and the drain is connected to the drain of the third PMOS transistor MP3;

[0040] Figure 1This is a schematic diagram of the circuit structure of a proposed high-speed latch comparator with a preamplifier. The preamplifier amplifies the input signal and transmits it to the subsequent latch for comparison, while effectively reducing kickback noise, increasing drive, and resetting the latch. Its amplification factor is:

[0041]

[0042] Wherein gmN1 and gmN3 are the transconductances of the first NMOS transistor MN1 and the third NMOS transistor MN3 in the figure, and RL is the load resistance.

[0043] The bandwidth of the preamplifier is:

[0044]

[0045] Where CL is the load capacitance of the preamplifier.

[0046] The latch compares the output signal of the pre-amplifier through positive feedback, and its bandwidth is:

[0047]

[0048] Among them, gmN6 and gmP1 are the transconductance of the sixth NMOS transistor MN6 and the first PMOS transistor MP1 in the figure.

[0049] The first capacitor C1 and the second capacitor C2 play the role of level shifting, which can increase the V GS This increases the transconductance of the two PMOS tubes, that is, when there is a cross-coupling capacitor:

[0050] V gsN6 +V sgP1 =V DD +V c1

[0051] Its working principle is that when the latch clock is high, the switch tubes MN8, MN9, and MN10 are turned on, the latch enters the reset state, and the gates of the MN6 and MN7 tubes store the output differential signals amplified by the preamplifier. The differential outputs of the latch are pulled to the same potential. When the latch clock is low, the switch tubes MN8, MN9, and MN10 are turned off, and the latch is in the comparison state. The amplification unit composed of MP1 and MN6 and the amplification unit composed of MP2 and MN7 are connected end to end, which will produce a positive feedback effect, compare the input signals and generate digital logic level outputs.

[0052] Figure 2This is a schematic diagram of the circuit structure of the bias circuit of the high-speed latch comparator proposed in the present invention, wherein the sizes of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 match the fifth NMOS transistor MN5, the tail current transistor in the preamplifier; the sizes of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 match the first NMOS transistor MN1 and the second NMOS transistor MN2, the input differential pair transistors in the preamplifier; the size of the fifteenth NMOS transistor MN15 matches the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the load pair transistors in the preamplifier; the size of the sixteenth NMOS transistor MN16 matches the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 in the latch; and the size of the third PMOS transistor MP3 matches the first PMOS transistor MP1 and the second PMOS transistor MP2 in the latch;

[0053] The eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, and the fourteenth NMOS transistor MN14 form a traditional low-voltage cascode structure. The bias of the first current source I1 and the preamplifier's input common-mode voltage generates a bias voltage VB1, thereby biasing the gate of the fifth NMOS transistor MN5, the preamplifier's tail current transistor. The first amplifier AMP1 clamps the drain of the fourteenth NMOS transistor MN14 and the gate of the sixteenth NMOS transistor MN16, simulating the state of the preamplifier and latch being connected when the latch clock is high. The third PMOS transistor MP3 simulates the operating state of the first PMOS transistor MP1 and the second PMOS transistor MP2 being in a diode connection when the latch clock is high. The second amplifier AMP2 clamps point A and the first power supply voltage VDD1. While clamping point A to the first power supply voltage VDD1, the second power supply voltage VDD2 and the second current source I2 provide a current bias to the third PMOS transistor MP3, cleverly achieving dual voltage and power bias for the third PMOS transistor MP3. Simultaneously, the output of the first amplifier AMP1 generates a bias voltage VB2, which biases the gates of the third and fourth NMOS transistors MN3 and MN4, the preamplifier load transistors. The bias circuit simulates the operating state of each transistor in the comparator's reset state, allowing the current of the comparator preamplifier and latch to be indirectly adjusted by adjusting the first and second current sources I1 and I2, thereby controlling speed and power consumption.

[0054] Therefore, the high-speed latch comparator designed in the present invention has the characteristics of low kickback noise, high speed, and strong driving capability by introducing a preamplifier. At the same time, the introduction of cross-coupling capacitors increases the transconductance gm of the MOS tube by increasing the gate-source Vg of the latch MOS tube. At the same time, the designed bias circuit can flexibly adjust the speed and power consumption of the comparator by directly adjusting the input current source, and can be used for pipelined analog-to-digital converters.

Claims

1. A high-speed latch comparator and its bias circuit, characterized in that: The device comprises a preamplifier, a latch, and a bias circuit; the preamplifier is arranged between the input signal and the latch, and is used to isolate the input signal from the latch and amplify the signal; the latch is used to receive and compare the amplified signal output by the preamplifier; the bias circuit is used to provide a bias voltage to the preamplifier and simultaneously adjust the current of the preamplifier and the latch; The preamplifier comprises a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3), a fourth NMOS tube (MN4), and a fifth NMOS tube (MN5); The gate of the first NMOS transistor (MN1) is connected to the input positive signal, the source is connected to the drain of the fifth NMOS transistor (MN5), the drain of the first NMOS transistor (MN1) is the negative signal output end of the preamplifier, and the drain of the first NMOS transistor (MN1) is connected to the source of the third NMOS transistor (MN3); The gate of the second NMOS transistor (MN2) is connected to the input negative signal, the source is connected to the drain of the fifth NMOS transistor (MN5), the drain of the second NMOS transistor (MN2) is the positive signal output end of the preamplifier, and the source of the second NMOS transistor (MN2) is connected to the source of the fourth NMOS transistor (MN4); The gate of the third NMOS transistor (MN3) is connected to the second bias voltage VB2, and the drain is connected to the first power supply VDD1; The gate of the fourth NMOS transistor (MN4) is connected to the second bias voltage VB2, and the drain is connected to the first power supply VDD1; The gate of the fifth NMOS transistor (MN5) is connected to the first bias voltage VB1, and the source is connected to the ground.

2. A high-speed latch comparator and bias circuit thereof according to claim 1, characterized in that: The latch comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), a first capacitor (C1), and a second capacitor (C2); The gate of the first PMOS tube (MP1) is the positive signal output end of the latch, connected to the drains of the second PMOS tube (MP2), the tenth NMOS tube (MN10) and the seventh NMOS tube (MN7); the source of the first PMOS tube (MP1) is connected to the first power supply VDD1; the drain of the first PMOS tube (MP1) is the negative signal output end of the latch; the drain of the first PMOS tube (MP1) is connected to the gate of the second PMOS tube (MP2), the source of the tenth NMOS tube (MN10) and the drain of the sixth NMOS tube (MN6); The gate of the second PMOS tube (MP2) is the negative signal output terminal of the latch, connected to the drains of the first PMOS tube (MP1) and the sixth NMOS tube (MN6) and the source of the tenth NMOS tube (MN10); the source of the second PMOS tube (MP2) is connected to the first power supply VDD1; the drain of the second PMOS tube (MP2) is the positive signal output terminal of the latch; and the drain of the second PMOS tube (MP2) is connected to the gate of the first PMOS tube (MP1), the drain of the tenth NMOS tube (MN10) and the drain of the seventh NMOS tube (MN7); The sixth NMOS transistor (MN6) receives the positive output signal of the preamplifier through the eighth NMOS transistor (MN8); the gate of the sixth NMOS transistor (MN6) is connected to the source of the eighth NMOS transistor (MN8) and the second connection end of the first capacitor (C1); the source of the sixth NMOS transistor (MN6) is connected to the ground; the drain of the sixth NMOS transistor (MN6) is the negative signal output end of the latch; and the drain of the sixth NMOS transistor (MN6) is connected to the drain of the first PMOS transistor (MP1), the source of the tenth NMOS transistor (MN10) and the first connection end of the second capacitor (C2); The gate of the seventh NMOS transistor (MN7) is connected to the source of the ninth NMOS transistor (MN9) and the second connection terminal of the second capacitor (C2); the source of the seventh NMOS transistor (MN7) is connected to the ground; the drain of the seventh NMOS transistor (MN7) is the positive signal output terminal of the latch; and the drain of the seventh NMOS transistor (MN7) is connected to the drain of the second PMOS transistor (MP2), the drain of the tenth NMOS transistor (MN10) and the first connection terminal of the first capacitor (C1); The gate of the eighth NMOS transistor (MN8) is connected to the latch clock signal, the source is connected to the gate of the sixth NMOS transistor (MN6) and the second connection end of the first capacitor (C1), and the drain of the eighth NMOS transistor (MN8) is connected to the positive output signal of the preamplifier; The gate of the ninth NMOS transistor (MN9) is connected to the latch clock signal, the source is connected to the gate of the seventh NMOS transistor (MN7) and the second connection end of the second capacitor (C2), and the drain of the ninth NMOS transistor (MN9) is connected to the negative output signal of the preamplifier; The gate of the tenth NMOS transistor (MN10) is connected to the latch clock signal, the source is the latch negative signal output terminal, and is connected to the drains of the first PMOS transistor (MP1) and the sixth NMOS transistor (MN6) and the first connection terminal of the second capacitor (C2); the drain of the tenth NMOS transistor (MN10) is the latch positive signal output terminal, and the drain of the tenth NMOS transistor (MN10) is connected to the drains of the second PMOS transistor (MP2) and the seventh NMOS transistor (MN7) and the first connection terminal of the first capacitor (C1).

3. A high-speed latch comparator and bias circuit thereof according to claim 2, characterized in that: The bias circuit comprises a first current source (I1), a second current source (I2), a first amplifier (AMP1), a second amplifier (AMP2), a third PMOS transistor (MP3), an eleventh NMOS transistor (MN11), a twelfth NMOS transistor (MN12), a thirteenth NMOS transistor (MN13), a fourteenth NMOS transistor (MN14), a fifteenth NMOS transistor (MN15), and a sixteenth NMOS transistor (MN16); The first connection end of the first current source (I1) is connected to the second power supply voltage VDD2, the second connection end outputs the first bias voltage VB1, and the second connection end is connected to the gates of the eleventh NMOS transistor (MN11) and the twelfth NMOS transistor (MN12) and the drain of the thirteenth NMOS transistor (MN13); A first connection end of the second current source (I2) is connected to a second power supply voltage VDD2, and a second connection end is connected to a source and a gate of a third PMOS transistor (MP3) and a negative input end of a second amplifier (AMP2); The positive input terminal of the first amplifier (AMP1) is connected to the gate of the sixteenth NMOS transistor (MN16), the negative input terminal is connected to the drain of the fourteenth NMOS transistor (MN14) and the source of the fifteenth NMOS transistor (MN15), the output terminal of the first amplifier (AMP1) outputs the second bias voltage VB2, and the output terminal of the first amplifier (AMP1) is connected to the gate of the fifteenth NMOS transistor (MN15); The positive input terminal of the second amplifier (AMP2) is connected to the first power supply voltage VDD1, and the negative input terminal is connected to the second connection terminal of the second current source (I2) and the source and drain of the third PMOS transistor (MP3); The gate and source of the third PMOS transistor (MP3) are connected and connected to the negative input terminal of the second amplifier (AMP2) and the second connection terminal of the second current source (I2); The gate of the eleventh NMOS transistor (MN11) is connected to the second connection terminal of the first current source (I1) and the gate of the twelfth NMOS transistor (MN12), the source of the eleventh NMOS transistor (MN11) is connected to the ground, and the drain of the eleventh NMOS transistor (MN11) is connected to the source of the thirteenth NMOS transistor (MN13); The gate of the twelfth NMOS transistor (MN12) is connected to the second connection terminal of the first current source (I1) and the gate of the eleventh NMOS transistor (MN11), the source of the twelfth NMOS transistor (MN12) is connected to the ground, and the drain of the twelfth NMOS transistor (MN12) is connected to the source of the fourteenth NMOS transistor (MN14); The gate of the thirteenth NMOS transistor (MN13) is the preamplifier input common mode voltage VCM terminal, the gate of the thirteenth NMOS transistor (MN13) is connected to the gate of the fourteenth NMOS transistor (MN14), the source of the thirteenth NMOS transistor (MN13) is connected to the drain of the eleventh NMOS transistor (MN11), and the drain of the thirteenth NMOS transistor (MN13) is connected to the second connection terminal of the first current source (I1) and the gates of the eleventh NMOS transistor (MN11) and the twelfth NMOS transistor (MN12); The source of the fourteenth NMOS transistor (MN14) is connected to the drain of the twelfth NMOS transistor (MN12), and the drain of the fourteenth NMOS transistor (MN14) is connected to the source of the fifteenth NMOS transistor (MN15) and the negative input terminal of the first amplifier (AMP1); The gate of the fifteenth NMOS transistor (MN15) is connected to the output terminal of the first amplifier (AMP1), and the source of the fifteenth NMOS transistor (MN15) is connected to the drain of the fourteenth NMOS transistor (MN14) and the negative input terminal of the first amplifier (AMP1); The gate of the sixteenth NMOS transistor (MN16) is connected to the positive input terminal of the first amplifier (AMP1) and the output terminal of the second amplifier (AMP2), the source of the sixteenth NMOS transistor (MN16) is grounded, and the drain of the sixteenth NMOS transistor (MN16) is connected to the drain of the third PMOS transistor (MP3).

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