Level shifter and calibration method

Abstract

Disclosed are level shifters and calibration methods. In described examples, a level shifter (200) includes a signal generator (206) that produces a differential signal on a first output and a second output. A first capacitor (C21) is coupled between the first output and a first node (N21), and a second capacitor (C22) is coupled between the second output and a second node (N22). A third capacitor (C23) is coupled between the first node (N21) and a first voltage potential (VT). A capacitance of the third capacitor (C23) is variable. A fourth capacitor (C24) is coupled between the second node (N22) and the first voltage potential (VT). A capacitance of the fourth capacitor (C24) is variable.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201780014027.8, entitled “Level Shifter and Calibration Method”, filed on March 30, 2017. Background Technology

[0002] Voltage converters, or level shifters, are devices that resolve mixed voltage incompatibilities between different parts of a system operating in multiple voltage domains. They are common in many complex electronic systems, especially when connected to conventional devices. With the advent of wide-bandgap semiconductors, the switching speed of level shifters has continuously increased. However, conventional level shifters do not possess the required high common-mode transient immunity (CMTI) and propagation time fast enough to handle these high switching speeds. Summary of the Invention

[0003] In the described example, the level shifter includes a signal generator that produces differential signals at a first output and a second output. A first capacitor is coupled between the first output and a first node, and a second capacitor is coupled between the second output and the second node. A third capacitor is coupled between the first node and a first voltage potential. The capacitance of the third capacitor is variable. A fourth capacitor is coupled between the second node and the first voltage potential. The capacitance of the fourth capacitor is variable. Attached Figure Description

[0004] Figure 1 This is a schematic diagram of a part of a switching power supply.

[0005] Figure 2 yes Figure 1 A schematic diagram of an example of a power supply level shifter, which is tunable to increase common-mode transient immunity.

[0006] Figure 3 It is by Figure 2 An example of a pulse generator that generates a signal in response to an input voltage.

[0007] Figure 4 It is in response to Figure 2 The pulse generated by the pulse generator Figure 2 An example of the signal at the output of the amplifier.

[0008] Figure 5 yes Figure 2 A detailed schematic diagram of an example of a first differential amplifier.

[0009] Figure 6 This describes a calibration level shifter (e.g.) Figure 2 The flowchart of the method for using a level shifter. Detailed Implementation

[0010] This article describes a level shifter with high common-mode transient immunity (CMTI) and low propagation delay. The high CMTI enables the level shifter to operate at high switching frequencies in applications such as driving high-voltage field-effect transistors (FETs). In some examples, the level shifter drives the high-side signal transition of a wide-bandgap power FET driver in a high-voltage switching power supply. Such wide-bandgap FETs can include gallium nitride (GaN) power FETs and silicon carbide (SiC) power FETs. With the advent of such wide-bandgap semiconductors, the switching speed of switching power supplies continues to increase, placing higher demands on the gate drivers and level shifters within the switching power supply. Conventional switching power supplies reduce switching losses by implementing wide-bandgap drivers with slew rates higher than those that current level shifters can support without error.

[0011] Figure 1 This is a schematic diagram of a portion of a switching power supply 100. The power supply 100 includes a controller 104 coupled to a switching section 106, whereby the controller 104 drives FETs Q11 and Q12 in the switching section 106. FET Q11 is sometimes referred to as a high-side FET, and FET Q12 is sometimes referred to as a low-side FET. In some examples, FETs Q11 and Q12 are wide-bandgap GaN FETs with a drain / source breakdown voltage of approximately 600V. FETs Q11 and Q12 are examples of switches that can be implemented in the switching section 106. Other switching devices can be implemented in the power supply 100. The power supply 100 is capable of high-voltage swinging between a transmitter (not shown) and a receiver (not shown).

[0012] The drain of FET Q11 is coupled to a voltage source V11, which is a high-voltage source and, in some examples, has a voltage potential between 0V and 600V. The source of FET Q12 is coupled to a voltage potential... Figure 1 In the example, the voltage potential is grounded.

[0013] Controller 104 includes control circuitry 110, which can receive and output multiple signals and voltages to drive switching section 106. In the example controller 104, control circuitry 110 receives control signals at node N11. In some examples, the control signals include pulse width modulation (PWM) signals that control or set the timing of switching section 106. In other examples, control circuitry 110 may have additional inputs coupled to control circuitry 110. Control circuitry 110 has an output 112 coupled to an input of level shifter 120 and an output 124 coupled to an input of driver 126 driving FET Q12.

[0014] When controller 104 itself operates at a much lower voltage, level shifter 120 enables controller 104 to operate FET Q11 at a higher voltage. Level shifter 120 has an output 130 coupled to driver or amplifier 132, which controls the gate voltage of FET Q11. Similarly, driver 126 controls the gate voltage of FET Q12. Driver 126 operates at, for example, a voltage VDD of 5V relative to a voltage VSS that can be grounded. Level shifter 120 and driver 132 can operate at low voltages, but their ground reference VDD remains constant. HS It can be much higher than the VSS potential. Therefore, the ground reference V HS and power supply voltage V HB The voltage difference between them can be VDD or 5V.

[0015] When FET Q12 is turned off, FET Q11 is turned on, and the voltage V HS The voltage is quickly swayed to V11. The output of level shifter 120 is also synchronized with voltage V. HS This simultaneous slew rate results in very fast common-mode transients for the level shifter 120. High-speed switching power supplies require drivers with very good common-mode transient immunity (CMTI) to withstand high slew rates from wide-bandgap devices such as FET Q11 and FET Q12. Many switching power supplies further require low propagation time and propagation matching to support high switching frequencies. Additionally, many switching power supplies require level shifters with low quiescent current consumption. The level shifter described herein features high CMTI, operates at high switching frequencies, and draws low quiescent current.

[0016] Figure 2 This is a schematic diagram of an example of a level shifter 200, which is tunable to increase CMTI. The level shifter 200 is coupled to an input, which can be coupled to... Figure 1 Node N11. Input 202 is coupled to pulse generator 206, which converts the input signal at input 202 into multiple differential pulses output at nodes Q and Q'. The signal output at node Q is referred to as signal V21, and the signal output at node Q' is referred to as V22. In other examples, signal generation devices other than pulse generator 206 can be implemented to generate differential signals representing the input signal at node N11.

[0017] Nodes Q and Q' are coupled to multiple drivers 208. The last of the drivers 208 is a driver 210 or a driver 212 coupled to or powered by a variable voltage source 216. The variable voltage source 216 sets the amplitudes of signals V23 and V24 at the outputs of drivers 210 and 212. As described in more detail below, the variable voltage source 216 changes the amplitudes of signals V23 and V24 to calibrate the output amplitude of the level shifter 200. In some examples, multiple drivers 208 are implemented using a single driver coupled to node Q and a single driver coupled to node Q'.

[0018] Capacitor C21 is coupled between driver 210 and node N21, and capacitor C22 is coupled between driver 212 and node N22. Capacitors C21 and C22 will transfer the voltage potential V... HS It is isolated from low-voltage circuits (such as driver 208 and pulse generator 206). Capacitor C23 is coupled at node N21 and voltage terminal V. T Between. Capacitor C24 is coupled at node N22 and voltage terminal V. T Between. Voltage terminal V T Multiple different voltages can be used, as described herein. Capacitors C23 and C24 are variable or can be adjusted to improve the CMTI at nodes N21 and N22, as described in more detail below. In some examples, the capacitance values ​​of capacitors C23 and C24 are greater than the capacitance values ​​of capacitors C21 and C22. Capacitors C21 and C23 form a voltage divider at node N21, and capacitors C22 and C24 form a voltage divider at node N22. Signals V23 and V24 are typically high-frequency signals or contain high-frequency components, such as a step function, and can pass through capacitors C21 and C22 to become differential signals at nodes N21 and N22. Common-mode signals are generated at N21 and N22 in response to the CMTI on level shifter 200. During calibration, the ratios of C21 to C23 and C22 to C24 are closely matched to minimize the differential outputs generated at nodes N21 and N22 in response to CMTI. If the ratios are not closely matched, transient common-mode voltages may cause delays and / or errors in the processing of signals V23 and V24 as described herein.

[0019] Differential amplifier 220 has its differential input coupled to nodes N21 and N22. Differential amplifier 220 processes signals V21 and V22 as described herein. Another differential amplifier 222 also has its differential input coupled to nodes N21 and N22. Differential amplifier 222 measures the differential transient response at nodes N21 and N22 during transient testing and generates signal V.TEST Signal V TEST It is proportional to the differential transient response. Signal V TEST The signal is input to processor 224, which responds to signal V. TEST Adjust the capacitance values ​​of capacitors C23 and C24.

[0020] Resistor R21 converts voltage source V through switch SW21 CM Coupled to node N21, and resistor R22 converts voltage source V through switch SW21. CM Coupled to node N22. The state of switch SW21 is set by processor 224, and switch SW21 is used to charge nodes N21 and N22 to voltage V. CM The voltage V CM This is the common-mode voltage of differential amplifier 220. The charges on nodes N21 and N22 are analyzed by processor 224 to determine the appropriate capacitance values ​​for capacitors C23 and C24 to maximize CMTI, as described herein.

[0021] exist Figure 2 In the example, the output of differential amplifier 220 is coupled to the input of second differential amplifier 230. Figure 2 In the example, differential amplifier 220 has a very good high-frequency common-mode rejection ratio (CMRR). For example, a 2-volt swing over a 2-nanosecond period can produce a maximum 2-mV differential swing at the output of differential amplifier 220. The CMRR of differential amplifier 220 is a factor limiting the CMTI of level shifter 200. Differential amplifier 220 is sometimes referred to herein as the first stage. Common-mode voltage swings at nodes N21 and N22 have little effect on the gain of differential amplifier 220. Differential amplifier 230 has a modest gain, which can be less than that of differential amplifier 220. Furthermore, differential amplifier 230 has a low output impedance to drive large loads of components coupled to the output of differential amplifier 230, as described herein.

[0022] The differential output of differential amplifier 230 is coupled to a first RC network, which in turn is coupled to the input of comparator 234. The differential output of differential amplifier 230 is also coupled to a second RC network, which in turn is coupled to the input of comparator 236. The high output of differential amplifier 230 is coupled to capacitors C25 and C26, and the low output of differential amplifier 230 is coupled to capacitors C27 and C28. Capacitors C25 and C27 are coupled to the input of comparator 234, and capacitors C26 and C28 are coupled to the input of comparator 236. Resistors R23 and R24 couple the input of comparator 234 to voltage source V25, and resistors R25 and R26 couple the input of comparator 236 to voltage source V26. Voltage source V25 sets a threshold for triggering a voltage transition on the output of comparator 234, and voltage source V26 sets a threshold for triggering a voltage transition on the output of comparator 236. The outputs of comparators 234 and 236 are coupled to the input of latch 240. Figure 2 In this example, latch 240 includes two NAND gates. The output of latch 240 is coupled to the gate of transistor Q11. In some examples, an amplifier or driver (not shown) is coupled between latch 240 and the gate of transistor Q11.

[0023] Figure 3 It is the signal V21 generated by pulse generator 206 in response to the signal received at node N11. Figure 2 Example of signal V21. Signal V22 is a complement to signal V21. Figure 3 The signal V21 shown is an example of several differential signal types that can be generated by the pulse generator 206. Figure 3 In the example, pulse generator 206 generates positive or negative pulses on the rising and falling edges of the input signal at node N11. Pulse generator 206 further generates pulses to keep level shifter 200 active. The input signal has a rising edge 300, which causes pulse generator 206 to generate a pulse 302 with a predetermined pulse width t31. Figure 3 In the example, the predetermined pulse width t31 is 3 ns. Pulse 302 is represented by the letter M to indicate that it is the main pulse generated at the start of the input signal transition. A safety pulse, represented by the letter I, is transmitted after a predetermined time t32 from the main pulse. Figure 3 The example shows a safety pulse 306 transmitted after a predetermined time t32 following the autonomous pulse 302. Figure 3 In the example, the predetermined time t32 between the main pulse and the safety pulse is 20 ns. If the input signal does not change after the predetermined time t33, the pulse generator 206 generates a hold pulse represented by the letter K. Figure 3In the example, pulse generator 206 generates hold pulse 310 at time t33 since the generation of safety pulse 312.

[0024] The pulses in signals V23 and V24 are turned on by capacitors C21 and C22, respectively, and terminated by capacitors C23 and C24, whose capacitance values ​​can be sufficiently greater than those of capacitors C21 and C22. This difference in capacitance forms a capacitive voltage divider between the outputs of drivers 210 and 212 and nodes N21 and N22. In the example described herein, the voltage divider has a large ratio, such as 330 V / V. This ratio is chosen such that the total voltage swing of the input relative to the output is equal to at least half of the total mode range of the differential amplifier 220.

[0025] As described above, capacitors C23 and C24 are adjustable to adjust for common-mode to differential conversion, which would otherwise occur due to the mismatch ratio of the capacitance values ​​of C21 / C23 and C22 / C24 as described herein. Adjustment of capacitors C23 and C24 can be performed after assembling level shifter 200, for example, during testing. The input signal at node N11 is invalid during testing, therefore pulse generator 206 does not generate any pulses. Processor 224 closes switch SW21, which is connected to the common-mode voltage V. CM Capacitors C21, C22, C23, and C24 are charged. Then, processor 224 disconnects switch SW21, creating a high-impedance condition, which allows any differential error at nodes N21 and N22 to be preserved for readout by amplifier 222. Then, V... HS The voltage is scanned to a high voltage relative to the input of the level shifter. Any differential errors associated with capacitor mismatch are then maintained across capacitors C21, C22, C23, and C24 and read by processor 224 via differential amplifier 222. If the ratio of the capacitance values ​​of capacitors C21 to C23 is equal to the ratio of the capacitance values ​​of capacitors C22 to C24, then the voltage at node N21 will be equal to the voltage at node N22. Amplifier 222 measures the difference between the voltages at nodes N21 and N22 and outputs the difference to processor 224. In the example described herein, amplifier 222 has a gain of twenty, but other gain values ​​can be implemented as needed for a particular application. Processor 224 then determines the values ​​of capacitors C23 and C24. In some examples, processor 224 is separate from level shifter 220.

[0026] As mentioned above, the mismatch in the capacitance ratio of capacitors C21, C22, C23, and C24 causes common-mode differential switching, and adjusting capacitors C23 and C24 improves the common-mode differential switching performance. This is achieved by using a common voltage source V... CM Disconnecting resistors R21 and R22 converts the adjustment process to low-frequency adjustment, which sets DC voltages across capacitors C23 and C24. The DC voltages across capacitors C23 and C24 are the voltages at nodes N21 and N22, respectively. Common-mode is then swept, and any errors caused by mismatch are left across capacitors C23 and C24 and measured via amplifier 222. Sweeping common-mode involves shifting the high-voltage side of level shifter 200 from 0V, where it is when switch SW21 is open, to a higher voltage. The high voltage develops across C21 and C22. Due to the slow time constants associated with capacitors C23 and C24, the measurement can be completed over a long period. Amplifier 222 can be double-sampled to eliminate any offset errors within the amplifier itself. For example, the output of amplifier 222 can be sampled before SW21 is open and both inputs are still at the same voltage potential, and then sampled again after the errors at N21 and N22 have stabilized. The difference between the two readings gives an error independent of the offset of amplifier 222.

[0027] As described above, the output signal or voltage of amplifier 222 is received by processor 224. Processor 224 then analyzes the voltage output of amplifier 222 to determine which of capacitors C23 and / or C24 needs adjustment and by how much to make the aforementioned ratio equal. The common-mode differential conversion process can be repeated after the initial adjustment to ensure that capacitors C23 and C24 have been correctly adjusted.

[0028] Figure 4 It shows the response to by Figure 2 The pulse generated by pulse generator 206 is plotted as an example signal 400 at the output of amplifier 230. This plot shows the noise margin between the positive and negative comparison thresholds, where signal 400 is undetectable. Figure 4 As shown, the CMTI sensing signal is present in signal 400, but it is within the noise margin and does not cause error. Signal 400 exceeds the positive comparison threshold and enters the signal margin at time 402. The signal amplitude of signal 400 determines the extent to which signal 400 extends beyond the noise margin. If the signal amplitude is too low, signal 400 will not be detected above the noise margin.

[0029] Level shifter 200 provides the ability to set the threshold levels of comparators 234 and 236 to obtain the signal, for example... Figure 4The signal 400 has appropriate signal and noise margins. In the example described herein, the signal amplitude is set to twice the noise margin. The process involves regulating the outputs of drivers 210 and 212 to a lower voltage. Figure 2 In the example, by providing a lower or half voltage to drivers 210 and 212 via a variable voltage source 216, the output voltage of the drivers is set to half of their normal operating voltage. Voltages V25 and V26 are then adjusted until signal 400 just exceeds the noise margin. The outputs of comparators 234 and 236, or latch 240, can be monitored to determine if signal 400 has exceeded the noise margin. Then, processor 224 instructs variable voltage source 216 to output full voltage to drivers 210 and 212, and the outputs of drivers 210 and 212 return to their full voltage. Then signal amplitude 400... Figure 4 As shown.

[0030] Figure 5 yes Figure 2 A schematic diagram of an example of a differential amplifier 220. The first stage of amplifier 220 provides improved... Figure 2 The benefits of operating the level shifter 200. The terminals of capacitors C23 and C24 can be voltage VDD, ground, or the voltage between ground and DVD. Amplifier 220 has a very high common-mode rejection ratio (CMRR), which is achieved by utilizing the input, node N21, and node N22, and can be loaded with high capacitance without affecting the circuitry of amplifier 220.

[0031] Figure 6 This is a flowchart describing a method for calibrating a level shifter, for example... Figure 2 The method begins at step 600 by coupling a first node to a first voltage potential. The first node is coupled to a first capacitor, which is coupled to a signal generator. A second capacitor is coupled to a second voltage potential, and a first input is coupled to a first differential amplifier. Step 602 includes coupling a second node to the first voltage potential. The second node is coupled to a third capacitor, which is coupled to the signal generator. A fourth capacitor is coupled to the second voltage potential, and a second input is coupled to the first differential amplifier. Step 604 includes decoupling the first voltage from the first and second nodes. Step 606 includes scanning the voltage across the level shifter to generate a differential voltage between the first and second nodes. Step 608 includes measuring the voltage difference between the first and second nodes. Step 610 includes adjusting the capacitance value of at least one of the second and fourth capacitors in response to the measurement.

[0032] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An electronic system comprising: A level shifter, comprising: A first capacitor has a first terminal and a first capacitance; A second capacitor has a second terminal and a second capacitance; Terminal voltage source; A third capacitor, coupled between the first terminal and the terminal voltage source, and having a third capacitance that defines a first ratio of the third capacitance to the first capacitance; and A fourth capacitor is coupled between the second terminal and the terminal voltage source and has a fourth capacitance, the fourth capacitance defining a second ratio of the fourth capacitance to the second capacitance, the second ratio matching the first ratio.

2. The system according to claim 1, further comprising: Common-mode voltage source; A first switch is coupled between the first terminal and the common-mode voltage source; as well as A second switch is coupled between the second terminal and the common-mode voltage source.

3. The system according to claim 1, further comprising: A first differential amplifier having a first input coupled to the first terminal and a second input coupled to the second terminal, the first differential amplifier being configured to generate a test signal based on the voltage difference between the first terminal and the second terminal when the first terminal and the second terminal are decoupled from a common-mode voltage source.

4. The system according to claim 3, wherein: The third capacitor includes a first adjustable capacitor; The fourth capacitor includes a second adjustable capacitor; and Adjust at least one of the third capacitor or the fourth capacitor based on the test signal so that the second ratio matches the first ratio.

5. The system according to claim 4, further comprising: A processor, coupled to the first differential amplifier to receive the test signal, is configured to provide instructions to adjust at least one of the third capacitor or the fourth capacitor.

6. The system of claim 5, wherein the processor is configured to decouple the common-mode voltage source from the first terminal and the second terminal when the test signal is being generated.

7. The system of claim 5, wherein the processor is configured to determine common-mode transient immunity between the first terminal and the second terminal based on the test signal.

8. The system according to claim 5, further comprising: A first driver has an output coupled to the first capacitor and an input adapted to receive a first pulse signal; A second driver has an output coupled to the second capacitor and an input adapted to receive a second pulse signal; A variable voltage source coupled to the first driver and the second driver, and having a control terminal coupled to the processor; The second differential amplifier has a first input coupled to the first terminal, a second input coupled to the second terminal, a first output, and a second output; A first RC network is coupled to the first output of the second differential amplifier; A first comparator, which is coupled to the first RC network; A first voltage source is coupled to the first RC network and has a control terminal coupled to the processor; A second RC network is coupled to the second output of the second differential amplifier; A second comparator is coupled to the second RC network; A second voltage source is coupled to the second RC network and has a control terminal coupled to the processor.

9. The system of claim 8, wherein the processor is configured to: The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to a specific voltage that is lower than the normal operating voltages of the first driver and the second driver; The first voltage source and the second voltage source are adjusted to a position where the output signal of the second differential amplifier just exceeds the noise margin, wherein the output signal of the second differential amplifier just exceeds the noise margin is determined by monitoring the outputs of the first comparator and the second comparator; and The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to their normal operating voltages.

10. The system of claim 1, wherein the first capacitor is different from the second capacitor.

11. An electronic system comprising: A level shifter, comprising: First terminal and second terminal; Terminal voltage source; A first adjustable capacitor is coupled between the first terminal and the terminal voltage source; A second adjustable capacitor, coupled between the second terminal and the terminal voltage source; and A first differential amplifier has a first differential input coupled to the first terminal, a second differential input coupled to the second terminal, and a differential output.

12. The system according to claim 11, further comprising: Common-mode voltage source; A first switch is coupled between the first terminal and the common-mode voltage source; as well as A second switch is coupled between the second terminal and the common-mode voltage source.

13. The system according to claim 11, further comprising: A second differential amplifier has a first input coupled to the first terminal and a second input coupled to the second terminal. The second differential amplifier is configured to generate a test signal based on the voltage difference between the first terminal and the second terminal when the first terminal and the second terminal are decoupled from a common-mode voltage source.

14. The system of claim 13, further comprising: A processor, coupled to receive the test signal from the second differential amplifier, is configured to determine the common-mode transient immunity between the first terminal and the second terminal based on the test signal.

15. The system of claim 14, wherein the processor is configured to decouple the common-mode voltage source from the first terminal and the second terminal while the test signal is being generated.

16. The system of claim 14, wherein the processor is configured to adjust at least one of the first adjustable capacitor or the second adjustable capacitor based on the common-mode transient immunity.

17. The system according to claim 14, wherein: The first terminal is adapted to be coupled to a third capacitor having a third capacitance; The second terminal is adapted to be coupled to a fourth capacitor having a fourth capacitance; The first adjustable capacitor has a first capacitance; The second adjustable capacitor has a second capacitance; as well as The processor is configured to adjust at least one of the first capacitor or the second capacitor such that a first ratio of the first capacitor to the third capacitor matches a second ratio of the second capacitor to the fourth capacitor.

18. The system of claim 14, further comprising: A first driver has an output coupled to the first adjustable capacitor and an input adapted to receive a first pulse signal; A second driver having an output coupled to the second adjustable capacitor and an input adapted to receive a second pulse signal; A variable voltage source coupled to the first driver and the second driver, and having a control terminal coupled to the processor; The second differential amplifier has a first input coupled to the first terminal, a second input coupled to the second terminal, a first output, and a second output; A first RC network is coupled to the first output of the second differential amplifier; A first comparator, which is coupled to the first RC network; A first voltage source is coupled to the first RC network and has a control terminal coupled to the processor; A second RC network is coupled to the second output of the second differential amplifier; A second comparator is coupled to the second RC network; A second voltage source is coupled to the second RC network and has a control terminal coupled to the processor.

19. The system of claim 18, wherein the processor is configured to: The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to a specific voltage that is lower than the normal operating voltages of the first driver and the second driver; The first voltage source and the second voltage source are adjusted so that the output signal of the second differential amplifier just exceeds the noise margin, wherein the output signal of the second differential amplifier just exceeds the noise margin is determined by monitoring the outputs of the first comparator and the second comparator. and The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to their normal operating voltages.

20. An electronic system comprising: First terminal and second terminal; Terminal voltage source; A first adjustable capacitor is coupled between the first terminal and the terminal voltage source; A second adjustable capacitor is coupled between the second terminal and the terminal voltage source; Common-mode voltage source; A first switch is coupled between the first terminal and the common-mode voltage source; A second switch is coupled between the second terminal and the common-mode voltage source; A differential amplifier having a first input coupled to the first terminal, a second input coupled to the second terminal, and an amplifier output configured to provide a test signal; as well as A processor coupled to the amplifier output of the differential amplifier.

21. The system of claim 20, wherein The differential amplifier is configured to generate the test signal based on the voltage difference between the first terminal and the second terminal when the first terminal and the second terminal are decoupled from the common-mode voltage source.

22. The system of claim 21, wherein The processor is configured to determine the common-mode transient immunity between the first terminal and the second terminal based on the test signal.

23. The system of claim 22, wherein the processor is configured to adjust at least one of the first adjustable capacitor or the second adjustable capacitor based on the common-mode transient immunity.

24. The system according to claim 22, wherein: The first terminal is adapted to be coupled to a third capacitor having a third capacitance; The second terminal is adapted to be coupled to a fourth capacitor having a fourth capacitance; The first adjustable capacitor has a first capacitance; The second adjustable capacitor has a second capacitance; and The processor is configured to adjust at least one of the first capacitor or the second capacitor such that a first ratio of the first capacitor to the third capacitor matches a second ratio of the second capacitor to the fourth capacitor.

25. The system of claim 24, further comprising: A first driver has an output coupled to the first adjustable capacitor and an input adapted to receive a first pulse signal; A second driver having an output coupled to the second adjustable capacitor and an input adapted to receive a second pulse signal; A variable voltage source coupled to the first driver and the second driver, and having a control terminal coupled to the processor; The second differential amplifier has a first input coupled to the first terminal, a second input coupled to the second terminal, a first output, and a second output; A first RC network is coupled to the first output of the second differential amplifier; A first comparator, which is coupled to the first RC network; A first voltage source is coupled to the first RC network and has a control terminal coupled to the processor; A second RC network is coupled to the second output of the second differential amplifier; A second comparator is coupled to the second RC network; A second voltage source is coupled to the second RC network and has a control terminal coupled to the processor.

26. The system of claim 25, wherein the processor is configured to: The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to a specific voltage that is lower than the normal operating voltages of the first driver and the second driver; The first voltage source and the second voltage source are adjusted so that the output signal of the second differential amplifier just exceeds the noise margin, wherein the output signal of the second differential amplifier just exceeds the noise margin is determined by monitoring the outputs of the first comparator and the second comparator. and The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to their normal operating voltages.

27. An electronic system comprising: A first driver having an input adapted to receive a first pulse signal and an output; A second driver has an input adapted to receive a second pulse signal, and an output; A variable voltage source coupled to the first driver and the second driver, and having control terminals; A processor coupled to the control terminal of the variable voltage source; A differential amplifier having a first input coupled to the output of the first driver, a second input coupled to the output of the second driver, a first output, and a second output; A first RC network is coupled to the first output of the differential amplifier; A first comparator, which is coupled to the first RC network; A first voltage source is coupled to the first RC network and has a control terminal coupled to the processor; A second RC network is coupled to the second output of the differential amplifier; A second comparator is coupled to the second RC network; A second voltage source is coupled to the second RC network and has a control terminal coupled to the processor; The processor is configured as follows: The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to a specific voltage that is lower than the normal operating voltages of the first driver and the second driver; The first voltage source and the second voltage source are adjusted so that the output signal of the differential amplifier just exceeds the noise margin, wherein the output signal of the differential amplifier just exceeds the noise margin is determined by monitoring the outputs of the first comparator and the second comparator; and The variable voltage source is adjusted to set the output voltages of the first driver and the second driver to their normal operating voltages.

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