Semiconductor structure and method of fabricating the same
By employing a half-metal stacked structure and a vertical transistor design in the semiconductor structure, the contact resistance problem of the all-around gate transistor is solved, thereby improving semiconductor performance and current efficiency.
Patent Information
- Application Number
- CN202111231509.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-10-22
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2041-10-22
AI Technical Summary
As semiconductor structure dimensions shrink, the contact resistance between all-around gate transistors and other structures becomes larger, resulting in higher transistor current requirements and poorer semiconductor structure performance.
A stacked structure is formed by using a half-metal layer as the first and second conductive layer, and by designing the channel layer and dielectric layer, a vertical transistor is constructed to reduce contact resistance and increase the channel layer length to improve the short-channel effect.
It reduces the contact resistance between the stacked structure and other structures, improves the performance of the semiconductor structure, mitigates the short-channel effect of the transistor, and enhances current efficiency.
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Figure CN116033735B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND
[0002] The semiconductor structure can include a memory cell, which usually includes a transistor and a capacitor electrically connected with the transistor. The capacitor stores data information, and the transistor controls reading and writing of the data information in the capacitor. The gate of the transistor is electrically connected with a word line (WL), and the opening and closing of the transistor are controlled by a voltage on the word line; one of the source and the drain of the transistor is electrically connected with a bit line (BL), and the other of the source and the drain is electrically connected with the capacitor, and the data information is stored or output through the bit line.
[0003] With the miniaturization of the semiconductor structure, the transistor usually adopts a gate all around (GAA) transistor. In the related art, the GAA transistor includes a first conductive layer, a channel region and a second conductive layer which are sequentially stacked, one of the first conductive layer and the second conductive layer is a source, and the other is a drain, the side surface of the channel region is surrounded by a dielectric layer, and the dielectric layer is provided with a gate. However, the contact resistance of the above-mentioned transistor and other structures (such as a bit line or a capacitor) is large, the current required by the transistor is large, and the performance of the semiconductor structure is poor. SUMMARY
[0004] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are used to improve the performance of the semiconductor structure.
[0005] A first aspect of the embodiments of the present application provides a manufacturing method of a semiconductor structure, which includes: providing a substrate; forming a plurality of spaced-apart stacked structures on the substrate, the stacked structure including a first conductive layer, an insulating layer and a second conductive layer which are sequentially stacked, at least one of the first conductive layer and the second conductive layer being a semi-metallic layer; forming a channel layer covering the stacked structure, and a dielectric layer covering the channel layer; forming a word line extending in a first direction, the word line including a plurality of contact portions and a connecting portion connecting adjacent contact portions, the contact portion surrounding and contacting the side surface of the dielectric layer, and the contact portion being opposite to at least part of the insulating layer.
[0006] The manufacturing method of the semiconductor structure provided by the embodiments of the present application at least has the following advantages:
[0007] The method for manufacturing the semiconductor structure provided by the embodiments of the present application is characterized in that the first conductive layer, the insulating layer and the second conductive layer are sequentially stacked to form a stack structure, and at least one of the first conductive layer and the second conductive layer is a semimetal layer, which can reduce the contact resistance between the stack structure and other structures, and also reduce the contact resistance between the first conductive layer and / or the second conductive layer and the channel layer, thereby improving the performance of the semiconductor structure. In addition, the first conductive layer, the insulating layer, the second conductive layer, the channel layer, the dielectric layer and the contact part form a vertical transistor, and the length of the channel layer can be increased by adjusting the height of the stack structure, so as to improve the short channel effect of the transistor and improve the performance of the semiconductor structure.
[0008] The second aspect of the embodiments of the present application provides a semiconductor structure, which comprises a stack structure, a channel layer covering the side surface of the stack structure, a dielectric layer covering the side surface of the channel layer, and a gate ringed on the dielectric layer; the stack structure comprises a first conductive layer, an insulating layer and a second conductive layer which are sequentially stacked, one of the first conductive layer and the second conductive layer is a source electrode, the other of the first conductive layer and the second conductive layer is a drain electrode, and at least one of the source electrode and the drain electrode is a semimetal layer.
[0009] The semiconductor structure provided by the embodiments of the present application has at least the following advantages:
[0010] In the semiconductor structure of the embodiments of the present application, the first conductive layer, the insulating layer and the second conductive layer are sequentially stacked to form a stack structure, one of the first conductive layer and the second conductive layer is a source electrode, the other is a drain electrode, and at least one of the first conductive layer and the second conductive layer is a semimetal layer, which can reduce the contact resistance between the stack structure and other structures, and also reduce the contact resistance between the first conductive layer and / or the second conductive layer and the channel layer, thereby improving the performance of the semiconductor structure. In addition, the side surface of the stack structure is covered with the channel layer, the side surface of the channel layer is covered with the dielectric layer, the dielectric layer is ringed with the gate, and the stack structure, the channel layer, the dielectric layer and the gate form a vertical transistor, and the length of the channel layer can be increased by adjusting the height of the stack structure, so as to improve the short channel effect of the transistor and improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS
[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings required to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.
[0012] Figure 1A flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present application;
[0013] Figure 2 A schematic view of a first cross section after forming a second conductive layer in an embodiment of the present application;
[0014] Figure 3 A schematic view of a second cross section after forming a second conductive layer in an embodiment of the present application;
[0015] Figure 4 A schematic view of a first cross section after forming a stack structure in an embodiment of the present application;
[0016] Figure 5 A schematic view of a second cross section after forming a stack structure in an embodiment of the present application;
[0017] Figure 6 A schematic view of a first cross section after forming a channel layer in an embodiment of the present application;
[0018] Figure 7 A schematic view of a second cross section after forming a channel layer in an embodiment of the present application;
[0019] Figure 8 A schematic view of a first cross section after forming a dielectric layer in an embodiment of the present application;
[0020] Figure 9 A schematic view of a second cross section after forming a dielectric layer in an embodiment of the present application;
[0021] Figure 10 A schematic view of a first cross section after forming a word line in an embodiment of the present application;
[0022] Figure 11 A schematic view of a second cross section after forming a word line in an embodiment of the present application;
[0023] Figure 12 A schematic view of a first cross section after forming a first initial support layer in an embodiment of the present application;
[0024] Figure 13 A schematic view of a second cross section after forming a first initial support layer in an embodiment of the present application;
[0025] Figure 14 A schematic view of a first cross section after forming a first support layer in an embodiment of the present application;
[0026] Figure 15 A schematic view of a second cross section after forming a first support layer in an embodiment of the present application;
[0027] Figure 16A schematic view of a first cross section after forming an initial word line layer in an embodiment of the present application;
[0028] Figure 17 A schematic view of a second cross section after forming an initial word line layer in an embodiment of the present application;
[0029] Figure 18 A schematic view of a first cross section after forming a first photoresist layer in an embodiment of the present application;
[0030] Figure 19 A schematic view of a second cross section after forming a first photoresist layer in an embodiment of the present application;
[0031] Figure 20 A schematic view of a first cross section after etching a mask layer in an embodiment of the present application;
[0032] Figure 21 A schematic view of a second cross section after etching a mask layer in an embodiment of the present application;
[0033] Figure 22 A schematic view of a first cross section after forming an intermediate word line layer in an embodiment of the present application;
[0034] Figure 23 A schematic view of a second cross section after forming an intermediate word line layer in an embodiment of the present application;
[0035] Figure 24 A schematic view of a first cross section after forming a second photoresist layer in an embodiment of the present application;
[0036] Figure 25 A schematic view of a second cross section after forming a second photoresist layer in an embodiment of the present application;
[0037] Figure 26 A schematic view of a first cross section after forming a contact hole in an embodiment of the present application;
[0038] Figure 27 A schematic view of a second cross section after forming a contact hole in an embodiment of the present application;
[0039] Figure 28 A schematic view of a first cross section after removing a second photoresist layer in an embodiment of the present application;
[0040] Figure 29 A schematic view of a second cross section after removing a second photoresist layer in an embodiment of the present application;
[0041] Figure 30 Another schematic view of a first cross section after forming a contact hole in an embodiment of the present application;
[0042] Figure 31Another schematic view of a second cross section after forming a contact hole in the embodiment of the present application;
[0043] Figure 32 Schematic view of a first cross section after forming a third conductive layer in the embodiment of the present application;
[0044] Figure 33 Schematic view of a second cross section after forming a third conductive layer in the embodiment of the present application.
[0045] Legend of reference signs:
[0046] 10 - substrate; 11 - bit line;
[0047] 12 - shallow trench isolation structure; 20 - stack structure;
[0048] 21 - first conductive layer; 22 - insulating layer;
[0049] 23 - second conductive layer; 24 - top surface of the second conductive layer;
[0050] 30 - channel layer; 40 - dielectric layer;
[0051] 50 - first support layer; 51 - first initial support layer;
[0052] 61 - initial word line layer; 62 - intermediate word line layer;
[0053] 63 - word line; 64 - contact portion;
[0054] 65 - connecting portion; 71 - mask layer;
[0055] 72 - first photoresist layer; 73 - trench;
[0056] 81 - second support layer; 82 - second photoresist layer;
[0057] 83 - opening; 84 - contact hole;
[0058] 90 - third conductive layer. DETAILED DESCRIPTION
[0059] To improve the performance of the semiconductor structure, in the manufacturing method of the semiconductor structure provided by the embodiment of the present application, a vertical transistor is formed, and at least one of the source and the drain in the vertical transistor is a semi-metallic layer, so as to reduce the contact resistance between the vertical transistor and other structures and the contact resistance inside the vertical transistor, thereby improving the performance of the semiconductor structure.
[0060] In order to make the above objectives, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.
[0061] With reference to Figure 1 , the embodiments of the present application provide a manufacturing method of a semiconductor structure, which comprises the following steps:
[0062] Step S101: providing a substrate.
[0063] The substrate 10 can be a semiconductor bulk substrate. For example, the substrate 10 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate, etc. The substrate 10 can be doped or non-doped. For example, the substrate 10 can be an N-type substrate or a P-type substrate.
[0064] In some possible examples, with reference to Figure 2 and Figure 3 , Figure 2 the first cross section is a plane perpendicular to the second direction, Figure 3 the second cross section is a plane parallel to the second direction. A plurality of bit lines 11 can also be arranged in the substrate 10, and the plurality of bit lines 11 are spaced apart from each other and extend along the second direction. As shown in Figure 3 , the plurality of bit lines 11 extend along the horizontal direction (X direction) shown in Figure 3 . The bit lines 11 can be exposed to the surface of the substrate 10. As shown in Figure 2 and Figure 3 , the bit lines 11 are exposed to the upper surface of the substrate 10, so as to be electrically connected to other structures on the substrate 10.
[0065] With reference to Figure 2 and Figure 3 , a shallow trench isolation structure 12 (STI) is also arranged in the substrate 10. The shallow trench isolation structure 12 is arranged between adjacent bit lines 11, so as to isolate the bit lines 11. The filling material in the shallow trench isolation structure 12 can be an insulating material such as silicon nitride or silicon oxide.
[0066] Step S102: A plurality of spaced-apart stacked structures are formed on the substrate. The stacked structures include a first conductive layer, an insulating layer and a second conductive layer stacked sequentially, and at least one of the first conductive layer and the second conductive layer is a half-metal layer.
[0067] refer to Figure 4 and Figure 5 Multiple stacked structures 20 are formed on the substrate 10, with each stacked structure 20 spaced apart. Each stacked structure 20 includes a first conductive layer 21, an insulating layer 22, and a second conductive layer 23. One of the first conductive layer 21 and the second conductive layer 23 is electrically connected to a capacitor, and the other of the first conductive layer 21 and the second conductive layer 23 is electrically connected to a bit line 11 (BL). For example, the first conductive layer 21, the insulating layer 22, and the second conductive layer 23 are arranged along the vertical direction (…). Figure 5 The conductive layers (shown in the Z direction) are stacked sequentially, with the first conductive layer 21 electrically connected to the bit line 11 and the second conductive layer 23 electrically connected to the capacitor.
[0068] The insulating layer 22 can be an oxide layer; for example, the insulating layer 22 can be made of silicon oxide. At least one of the first conductive layer 21 and the second conductive layer 23 is a half-metal layer; for example, both the first conductive layer 21 and the second conductive layer 23 are half-metal layers. The material of the half-metal layer can be bismuth. By setting the first conductive layer 21 and / or the second conductive layer 23 as half-metal layers, the contact resistance between the stacked structure 20 and the bit line 11 and / or capacitor can be reduced, thereby improving the performance of the semiconductor structure.
[0069] Continue to refer to Figure 4 and Figure 5 Along the second direction ( Figure 5 (As shown in the X direction), each bit line 11 has at least one stacked structure 20, and the first conductive layer 21 is in contact with the bit line 11, thereby realizing the electrical connection between the first conductive layer 21 and the bit line 11. The stacked structure 20 can be columnar, such as a cylinder, elliptical cylinder, square cylinder or rectangular cylinder, and the stacked structure 20 can be arranged in an array.
[0070] refer to Figures 2 to 5 In some possible examples, a plurality of spaced-apart stacked structures 20 are formed on the substrate 10. The stacked structure 20 includes a first conductive layer 21, an insulating layer 22, and a second conductive layer 23 stacked sequentially. At least one of the first conductive layer 21 and the second conductive layer 23 may be a half-metal layer.
[0071] A first conductive layer 21, an insulating layer 22, and a second conductive layer 23 are deposited and formed on a substrate 10 in a stacked manner. For example... Figure 2 and Figure 3As shown, a first conductive layer 21 is deposited on the substrate 10, an insulating layer 22 is deposited on the first conductive layer 21, and a second conductive layer 23 is deposited on the insulating layer 22. The deposition can be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0072] The first conductive layer 21, the insulating layer 22, and the second conductive layer 23 are then etched to form multiple spaced-apart stacked structures 20. For example... Figure 4 and Figure 5 As shown, dry etching or wet etching removes part of the first conductive layer 21, the insulating layer 22 and the second conductive layer 23, so that the remaining first conductive layer 21, the insulating layer 22 and the second conductive layer 23 are separated to form a plurality of stacked structures 20 that are spaced apart from each other.
[0073] Step S103: Form a channel layer covering the stacked structure and a dielectric layer covering the channel layer.
[0074] refer to Figures 6 to 9 The channel layer 30 covers the stacked structure 20, and the dielectric layer 40 covers the channel layer 30. Specifically, the channel layer 30 covers the side and top surfaces of the stacked structure 20, and the dielectric layer 40 covers the side and top surfaces of the channel layer 30. The top surface refers to the surface facing away from the substrate 10. Figure 6 and Figure 7 As shown, the channel layer 30 covers the outer peripheral surface of the first conductive layer 21, the outer peripheral surface of the insulating layer 22, and the outer peripheral surface of the second conductive layer 23. The channel layer 30 also covers the top surface 24 of the second conductive layer.
[0075] In this structure, one of the first conductive layer 21 and the second conductive layer 23 forms the source, and the other forms the drain. The channel layer 30 surrounding the side surface of the stacked structure 20 forms a channel region to provide a conductive path between the source and the drain, allowing charge carriers to move from the source to the drain or vice versa. The dielectric layer 40 can be an oxide layer, and the dielectric layer 40 located on the side surface of the channel layer 30 forms a gate oxide layer.
[0076] like Figure 6 and Figure 7As shown, the channel region is layered. The material of the channel layer 30 can include molybdenum sulfide, such as molybdenum disulfide, or transition metal sulfides (TMDs). Layered molybdenum sulfide contains a band gap, resulting in a high on / off ratio for the field-effect transistor. Furthermore, layered molybdenum sulfide has a high specific surface area, which is beneficial for overcoming short-channel effects. The on / off ratio refers to the ratio of the on-state current to the off-state current of a device. Specifically, in a transistor, with constant source and drain voltages, the ratio of the source and drain currents measured with and without a gate voltage is the on / off ratio.
[0077] In some possible embodiments, the channel layer 30 is made of molybdenum sulfide, and the half-metal layer is made of bismuth. Preferably, the channel layer 30 is made of molybdenum sulfide, and the first conductive layer 21 and the second conductive layer 23 are both made of bismuth. With this configuration, the energy barrier at the interface between molybdenum sulfide and bismuth is reduced, which can reduce the interstitial states (MIGS) between the channel layer 30 and the first conductive layer 21, and between the channel layer 30 and the second conductive layer 23, thereby reducing the contact resistance between the channel layer 30 and the first conductive layer 21, and between the channel layer 30 and the second conductive layer 23.
[0078] In this embodiment, the channel layer 30 forming the covering stacked structure 20 and the dielectric layer 40 covering the channel layer 30 may include:
[0079] A channel layer 30 is deposited on the stacked structure 20 and the substrate 10, the channel layer 30 covering the top surface and side surfaces of the stacked structure 20, and the top surface of the substrate 10. (Reference) Figure 6 and Figure 7 The channel layer 30 is formed by a deposition process, covering the top and side surfaces of the stacked structure 20, as well as the top surface of the substrate 10. A dielectric layer 40 is then deposited on the channel layer 30. (Reference) Figure 8 and Figure 9 The dielectric layer 40 is formed by a deposition process and covers the entire surface of the channel layer 30.
[0080] Step S104: Forming a word line extending along a first direction, the word line including a plurality of contacts and a connecting portion connecting adjacent contacts, the contacts surrounding and contacting the side surface of the dielectric layer, the contacts corresponding to at least a portion of the insulating layer.
[0081] refer to Figure 10 and Figure 11 Word lines 63 are formed between the stacked structure 20 after the formation of the channel layer 30 and the dielectric layer 40. Multiple word lines 63 are spaced apart and arranged along a first direction. Figure 10 Extending in the Y direction (as shown). Figure 10 and Figure 11As shown, the word line 63 includes a plurality of contact portions 64 and connecting portions 65 connecting adjacent contact portions 64, wherein the contact portions 64 surround and contact side surfaces of the dielectric layer 40.
[0082] As shown, the contact portions 64 correspond to at least part of the insulating layer 22, and the contact portions 64 serve as gates of the transistors, i.e., part of the word line 63 is the gate. In a direction perpendicular to the substrate 10 (Z direction as shown), a projection of the insulating layer 22 in the direction at least partially overlaps a projection of the contact portions 64 in the direction. For example, a top surface of the contact portions 64 is lower than a top surface of the insulating layer 22, and a bottom surface of the contact portions 64 is higher than a bottom surface of the insulating layer 22. Figure 10 Figure 11 As shown, the contact portions 64 correspond to at least part of the insulating layer 22, and the contact portions 64 serve as gates of the transistors, i.e., part of the word line 63 is the gate. In a direction perpendicular to the substrate 10 (Z direction as shown), a projection of the insulating layer 22 in the direction at least partially overlaps a projection of the contact portions 64 in the direction. For example, a top surface of the contact portions 64 is lower than a top surface of the insulating layer 22, and a bottom surface of the contact portions 64 is higher than a bottom surface of the insulating layer 22. Figure 10 In the first direction, the connecting portions 65 connect two adjacent contact portions 64. The height of the connecting portions 65 can be the same as or different from the height of the contact portions 64, and the specific structure of the connecting portions 65 can be determined according to actual conditions.
[0083] In summary, in the embodiments of the present application, the first conductive layer 21, the insulating layer 22, and the second conductive layer 23 are sequentially stacked to form the laminated structure 20, and at least one of the first conductive layer 21 and the second conductive layer 23 is a semi-metallic layer, which can reduce the contact resistance between the laminated structure 20 and other structures, and also reduce the contact resistance between the first conductive layer 21 and / or the second conductive layer 23 and the channel layer 30, thereby improving the performance of the semiconductor structure. In addition, the first conductive layer 21, the insulating layer 22, the second conductive layer 23, the channel layer 30, the dielectric layer 40, and the contact portions 64 form a vertical transistor, and the length of the channel layer 30 can be increased by adjusting the height of the laminated structure 20, which facilitates improving the short channel effect of the transistor and improving the performance of the semiconductor structure.
[0084] In a possible embodiment of the present application, referring to
[0085] The word line 63 extending in the first direction is formed, and the word line 63 includes a plurality of contact portions 64 and connecting portions 65 connecting adjacent contact portions 64, wherein the contact portions 64 surround and contact side surfaces of the dielectric layer 40, and the step of the contact portions 64 corresponding to at least part of the insulating layer 22 further includes: filling a first support layer 50 between the laminated structure 20 covered with the channel layer 30 and the dielectric layer 40, wherein a surface of the first support layer 50 away from the substrate 10 is higher than a surface of the first conductive layer 21 away from the substrate 10, and lower than a surface of the insulating layer 22 away from the substrate 10. Figures 12 to 15 As shown, the contact portions 64 correspond to at least part of the insulating layer 22, and the contact portions 64 serve as gates of the transistors, i.e., part of the word line 63 is the gate. In a direction perpendicular to the substrate 10 (Z direction as shown), a projection of the insulating layer 22 in the direction at least partially overlaps a projection of the contact portions 64 in the direction. For example, a top surface of the contact portions 64 is lower than a top surface of the insulating layer 22, and a bottom surface of the contact portions 64 is higher than a bottom surface of the insulating layer 22.
[0086] Figures 12 to 15 As shown, the first support layer 50 can serve as a cushion layer to increase the distance between the subsequently formed word line 63 and the substrate 10, so that the bottom surface of the word line 63 is higher than the top surface of the first conductive layer 21, i.e. the surface of the word line 63 facing the substrate 10 is higher than the surface of the first conductive layer 21 facing away from the substrate 10. Meanwhile, the surface of the first support layer 50 facing away from the substrate 10 is lower than the surface of the insulating layer 22 facing away from the substrate 10, so that the bottom surface of the word line 63 is lower than the top surface of the first conductive layer 21, thereby ensuring that the word line 63 is opposite to the insulating layer 22. The material of the first support layer 50 can be silicon nitride or silicon oxynitride, and the first support layer 50 has a large selectivity ratio with the dielectric layer 40, for example, the selectivity ratio of the first support layer 50 with the dielectric layer 40 is greater than 5, so as to avoid damaging the dielectric layer 40 when etching the first support layer 50, thereby reducing the damage to the gate oxide layer of the transistor.
[0087] In a possible implementation of the present application, referring to Figures 12 to 15 filling the first support layer 50 between the stack structure 20 covered with the channel layer 30 and the dielectric layer 40, the surface of the first support layer 50 facing away from the substrate 10 is higher than the surface of the first conductive layer 21 facing away from the substrate 10, and lower than the surface of the insulating layer 22 facing away from the substrate 10 can include the following process:
[0088] forming the first initial support layer 51 on the dielectric layer 40, the first initial support layer 51 is filled between the stack structure 20 covered with the channel layer 30 and the dielectric layer 40, and the first initial support layer 51 covers the top surface of the dielectric layer 40. As shown in Figure 12 and Figure 13 As shown, the first initial support layer 51 is deposited, the first initial support layer 51 is filled between the stack structure 20 covered with the channel layer 30 and the dielectric layer 40, and the first initial support layer 51 also covers the top surface of the dielectric layer 40. Specifically, the upper surface of the first initial support layer 51 is higher than the upper surface of the dielectric layer 40.
[0089] After forming the first initial support layer 51, part of the first initial support layer 51 is removed, and the remaining first initial support layer 51 forms the first support layer 50. As shown in Figure 14 and Figure 15 As shown, along the direction perpendicular to the substrate 10, part of the first initial support layer 51 is removed by dry etching or wet etching, part of the first initial support layer 51 located between the stack structure 20 covered with the channel layer 30 and the dielectric layer 40 is reserved, and the remaining first initial support layer 51 forms the first support layer 50.
[0090] On the basis of the above embodiments, i.e. after forming the first support layer 50, in a possible example, referring to Figures 16 to 23to form word lines 63 extending along the first direction, the word lines 63 comprising a plurality of contact portions 64 and connection portions 65 connecting adjacent contact portions 64, the contact portions 64 surrounding and contacting side surfaces of the dielectric layers 40, the contact portions 64 being opposite to at least part of the insulating layers 22 can comprise the following steps:
[0091] Step S1041: forming an initial word line layer covering the first support layer and the dielectric layers.
[0092] Reference is made to Figure 16 and Figure 17 The initial word line layer 61 is formed by a deposition process, the initial word line layer 61 covering the first support layer 50 and the dielectric layers 40. As shown in Figure 16 and Figure 17 , the initial word line layer 61 covers the top surface of the first support layer 50 and covers the side surfaces and the top surface of the dielectric layers 40. There is also a gap between the initial word line layers 61 covering the side surfaces of the dielectric layers 40, that is, the initial word line layer 61 does not fill the space between the stack structure 20 covering the channel layers 30 and the dielectric layers 40.
[0093] Step S1042: removing part of the initial word line layer on the first support layer along the first direction, so that the initial word line layer forms a plurality of intermediate word line layers arranged at intervals.
[0094] Reference is made to Figures 18 to 23 Part of the initial word line layer 61 on the first support layer 50 is removed, so that the initial word line layer 61 forms a plurality of intermediate word line layers 62 arranged at intervals, each intermediate word line layer 62 extends along the first direction, that is, part of the initial word line layer 61 on the first support layer 50 is removed along the first direction, and the remaining initial word line layer 61 forms the intermediate word line layer 62.
[0095] Specifically, as shown in Figures 18 to 23 , removing part of the initial word line layer 61 on the first support layer 50 along the first direction, so that the initial word line layer 61 forms a plurality of intermediate word line layers 62 arranged at intervals can further comprise the following process:
[0096] A mask layer 71 covering the initial word line layer 61 is formed, the mask layer 71 fills the space between the stack structure 20 covering the channel layers 30, the dielectric layers 40 and the initial word line layer 61, and the mask layer 71 covers the top surface of the initial word line layer 61. As shown in Figure 18 and Figure 19 , the mask layer 71 is deposited on the initial word line layer 61, the mask layer 71 fills the space between the stack structure 20 of the channel layers 30, the dielectric layers 40 and the initial word line layer 61, and the mask layer 71 also covers the top surface of the initial word line layer 61. The top surface of the mask layer 71 is higher than the top surface of the initial word line layer 61.
[0097] After the mask layer 71 is formed, a first photoresist layer 72 is formed on the mask layer 71, the first photoresist layer 72 has a trench 73 extending along the first direction, the orthogonal projection of the trench 73 on the substrate 10 does not overlap with the orthogonal projection of the initial word line layer 61 on the substrate 10 located on the side surface of the stack structure 20. As shown in Figure 18 and Figure 19 , the first photoresist layer 72 is spin-coated on the mask layer 71, the first photoresist layer 72 has the trench 73 penetrating through the first photoresist layer 72, the trench 73 is staggered with the initial word line layer 61 located on the side surface and the top surface of the dielectric layer 40, and is opposite to the partial initial word line layer 61 on the first support layer 50.
[0098] After the first photoresist layer 72 is formed, the mask layer 71 is etched with the first photoresist layer 72 as a mask. By etching the mask layer 71 with the first photoresist layer 72 as a mask, the pattern on the first photoresist layer 72 is transferred to the mask layer 71, as shown in Figure 20 and Figure 21 , the mask layer 71 forms a pattern exposing the initial word line layer 61.
[0099] After the mask layer 71 is etched, the initial word line layer 61 is etched with the etched mask layer 71 as a mask to form an intermediate word line layer 62. By using anisotropic etching, the partial initial word line layer 61 on the first support layer 50 is removed, as shown in Figure 22 and Figure 23 , the remaining initial word line layer 61 forms the intermediate word line layer 62. The gap between the plurality of intermediate word line layers 62 exposes the first support layer 50.
[0100] Step S1043: removing the intermediate word line layer on the top surface of the dielectric layer and the partial intermediate word line layer on the side surface of the dielectric layer away from the substrate, and the remaining intermediate word line layer forms a word line.
[0101] The intermediate word line layer 62 on the top surface of the dielectric layer 40 and the upper partial intermediate word line layer 62 on the side surface of the dielectric layer 40 are etched and removed, and the remaining intermediate word line layer 62 forms a word line 63. As shown in Figure 10 and Figure 11 , the top surface of the word line 63 is lower than the top surface of the insulating layer 22, and the word line 63 is opposite to the insulating layer 22.
[0102] In another possible embodiment of the present application, the word line 63 extending along the first direction includes a plurality of contact portions 64 and a connecting portion 65 connecting adjacent contact portions 64, the contact portion 64 is connected with the stack structure 20, and the contact portion 64 is wrapped around the step on the side surface of the dielectric layer 40, referring to Figures 24 to 33 , the method for manufacturing a semiconductor structure further comprises:
[0103] A second support layer 81 is formed to cover the word lines 63, the first support layer 50, and the dielectric layer 40. As shown in Figure 24 and Figure 25 The second support layer 81 is deposited to cover the word lines 63, the first support layer 50, and the dielectric layer 40, and the top surface of the second support layer 81 is higher than the top surface of the dielectric layer 40. The surface of the second support layer 81 facing away from the substrate 10 can be flush, and the second support layer 81 is planarized, for example, by chemical mechanical polishing (CMP), so that the top surface of the second support layer 81 is flush. The material of the second support layer 81 can be the same as that of the first support layer 50, which is an insulating material, so that the second support layer 81 and the first support layer 50 form an integral whole, and the second support layer 81 and the first support layer 50 cover and isolate each word line 63, so that the word lines 63 are insulated from each other.
[0104] After the second support layer 81 is formed, a second photoresist layer 82 is formed on the second support layer 81, and the second photoresist layer 82 has a plurality of openings 83, which are opposite to the stack structures 20. As shown in Figure 24 and Figure 25 The second photoresist layer 82 is formed on the second support layer 81, and the second photoresist layer 82 has a plurality of openings 83, which correspond to the plurality of stack structures 20 respectively, and each opening 83 is opposite to the corresponding stack structure 20. The orthogonal projection of each opening 83 on the substrate 10 is within the orthogonal projection of the corresponding stack structure 20 on the substrate 10, or the orthogonal projection of each opening 83 on the substrate 10 coincides with the orthogonal projection of the corresponding stack structure 20 on the substrate 10.
[0105] After the second photoresist layer 82 is formed, the second support layer 81, the dielectric layer 40, and the channel layer 30 are etched with the second photoresist layer 82 as a mask to form a contact hole 84, which exposes the second conductive layer 23. As shown in Figure 26 and Figure 27 The contact hole 84 penetrates the second support layer 81, the dielectric layer 40, and the channel layer 30 to expose the second conductive layer 23. At the same time of forming the contact hole 84, the second photoresist layer 82 is also removed, or after the contact hole 84 is formed, the second photoresist layer 82 is removed. As shown in Figure 28 and Figure 29 After the second photoresist layer 82 is removed, the top surface of the second support layer 81 is exposed.
[0106] It should be noted that the area of the opening 83 of the contact hole 84 is larger than the area of the bottom of the contact hole 84, meaning that the upper part of the contact hole 84 is wider and the lower part is narrower. This configuration, after the third conductive layer 90 is formed within the contact hole 84, results in a wider upper portion of the third conductive layer 90, which increases the width of the operating window and facilitates alignment with the capacitor. Furthermore, the narrower lower portion of the third conductive layer 90 reduces the critical size of the transistor.
[0107] For example, taking the plane perpendicular to the substrate 10 as a cross-section, the cross-sectional shape of the contact hole 84 can be an inverted trapezoid, wider at the top and narrower at the bottom. For example... Figure 30 and Figure 31 As shown, the cross-sectional shape of the contact hole 84 can also be a connected rectangle or a trapezoid, with the rectangle positioned on the side of the trapezoid closer to the substrate 10, and the bottom edge of the rectangle coinciding with the top edge of the trapezoid.
[0108] After forming the contact hole 84, a third conductive layer 90 is formed within the contact hole 84, and the third conductive layer 90 is electrically connected to the second conductive layer. For example... Figure 32 and Figure 33 As shown, a third conductive layer 90 is deposited within the contact hole 84, and the third conductive layer 90 is in contact with the second conductive layer 23 to achieve electrical connection between the third conductive layer 90 and the second conductive layer 23. The third conductive layer 90 can be a capacitor contact pad, and a capacitor is formed on the third conductive layer 90.
[0109] refer to Figure 10 and Figure 11 This application also provides a semiconductor structure comprising: a stacked structure 20, a channel layer 30, a dielectric layer 40, and a gate. The stacked structure 20 is disposed on a substrate 10, which supports the stacked structure 20. The substrate 10 can be a semiconductor substrate, such as a silicon substrate.
[0110] The substrate 10 may also have multiple bit lines 11, which are spaced apart from each other and run along a second direction. Figure 11 Extending in the X direction (as shown). The bit line 11 may be exposed on the surface of the substrate 10 to facilitate electrical connection with other structures located on the substrate 10. A shallow trench isolation structure 12 may also be provided between adjacent bit lines 11 to isolate each bit line 11.
[0111] A plurality of stacked structures 20 are disposed on the substrate 10, with each stacked structure 20 spaced apart. Each stacked structure 20 includes a first conductive layer 21, an insulating layer 22, and a second conductive layer 23 stacked together. For example... Figure 10 and Figure 11As shown, the first conductive layer 21, the insulating layer 22 and the second conductive layer 23 are sequentially arranged in a direction away from the substrate 10. One of the first conductive layer 21 and the second conductive layer 23 is a source electrode, and the other one is a drain electrode. At least one of the source electrode and the drain electrode is a semimetallic layer, which can be made of bismuth. The insulating layer 22 can be made of silicon oxide. By arranging at least one of the source electrode and the drain electrode as a semimetallic layer, the contact resistance between the stack structure 20 and other structures (e.g., the bit line 11 and / or a capacitor) can be reduced, thereby improving the performance of the semiconductor structure.
[0112] With reference to Figure 10 and Figure 11 , in the second direction, at least one stack structure 20 is arranged on each bit line 11. One of the source electrode and the drain electrode in the stack structure 20 is in contact with the bit line 11, thereby realizing the electrical connection between the source electrode or the drain electrode and the bit line 11. The stack structure 20 can be columnar, such as a circular column, an elliptical column, a square column or a rectangular column. The stack structures 20 can be arranged in an array.
[0113] The side surface of the stack structure 20 is covered by a channel layer 30. The channel layer 30 surrounding the side surface of the stack structure 20 forms a channel region to provide a conductive channel between the source electrode and the drain electrode, so that the charge carriers can move from the source electrode to the drain electrode or from the drain electrode to the source electrode. The channel region is layered, and the channel layer 30 can be made of molybdenum sulfide, such as molybdenum disulfide. The layered molybdenum sulfide has a band gap, which forms a field effect transistor with a high on-off ratio. Preferably, the channel layer 30 is made of molybdenum sulfide, and the source electrode and the drain electrode are both made of bismuth, so as to reduce the gap state and the energy barrier between the channel layer 30 and the source electrode or the drain electrode, thereby reducing the contact resistance between the channel layer 30 and the source electrode or the drain electrode.
[0114] The side surface of the channel layer 30 is covered by a dielectric layer 40, which can be an oxide layer. The dielectric layer 40 located on the side surface of the channel layer 30 forms a gate oxide layer. Exemplarily, the dielectric layer 40 is made of silicon oxide.
[0115] With reference to Figure 10 and Figure 11 , a gate electrode is arranged around the dielectric layer 40. The gate electrode surrounds the side surface of the dielectric layer 40 and is in contact with the side surface of the dielectric layer 40. The gate electrode is opposite to at least part of the insulating layer 22. In a direction perpendicular to the substrate 10 (Z direction as shown), the projection of the dielectric layer 40 in the direction at least partially overlaps the projection of the gate electrode in the direction. Exemplarily, the top surface of the gate electrode is lower than the top surface of the dielectric layer 40, and the bottom surface of the gate electrode is higher than the bottom surface of the dielectric layer 40. Figure 10
[0116] The semiconductor structure in the embodiments of the present application further includes a word line 63 extending along the first direction, the word line 63 including a contact portion 64 and a connecting portion 65 connecting two adjacent contact portions 64, wherein the contact portion 64 is a gate electrode arranged around the dielectric layer 40, that is, a part of the word line 63 is a gate electrode. It can be understood that, along the first direction, the connecting portion 65 and the gate electrode are arranged at intervals, and the connecting portion 65 connects a plurality of gate electrodes in the first direction into one, forming the word line 63.
[0117] In some possible examples, referring to Figure 32 and Figure 33 , the word line 63 is arranged on the first support layer 50, the first support layer 50 is located below the word line 63 and fills between the stack structure 20 covered with the dielectric layer 40 and the channel layer 30 to raise the word line 63. The word line 63 can also be covered with a second support layer 81, and the second support layer 81 and the first support layer 50 electrically isolate the word line 63. The material of the second support layer 81 can be the same as that of the first support layer 50, so that the second support layer 81 and the first support layer 50 form one body.
[0118] Continuing to refer to Figure 32 and Figure 33 , the second support layer 81 also covers the dielectric layer 40, and the second support layer 81 has a contact hole penetrating through the dielectric layer 40 and the channel layer 30 to expose the second conductive layer 23 of the stack structure 20. The contact hole is filled with a third conductive layer 90, one end of the third conductive layer 90 is in contact with the second conductive layer 23 to realize the electrical connection between the third conductive layer 90 and the second conductive layer 23, and the other end of the third conductive layer 90 can be connected to a capacitor.
[0119] In the semiconductor structure of the embodiments of the present application, the first conductive layer 21, the insulating layer 22 and the second conductive layer 23 are sequentially stacked to form the stack structure 20, one of the first conductive layer 21 and the second conductive layer 23 is a source electrode, and the other is a drain electrode, and at least one of the first conductive layer 21 and the second conductive layer 23 is a semi-metallic layer, which can reduce the contact resistance between the stack structure 20 and other structures, and also reduce the contact resistance between the first conductive layer 21 and / or the second conductive layer 23 and the channel layer 30, thereby improving the performance of the semiconductor structure. In addition, the side surface of the stack structure 20 is covered with the channel layer 30, the side surface of the channel layer 30 is covered with the dielectric layer 40, the dielectric layer 40 is arranged around the gate electrode, and the stack structure 20, the channel layer 30, the dielectric layer 40 and the gate electrode form a vertical transistor, which can increase the length of the channel layer 30 by adjusting the height of the stack structure 20, thereby improving the short channel effect of the transistor and improving the performance of the semiconductor structure.
[0120] The embodiments or examples in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between embodiments can be mutually referred to.
[0121] In the description of the specification, the description referring to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific feature, structure, material or characteristic described can be combined in any one or more embodiments or examples in a suitable manner.
[0122] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; Multiple spaced-apart stacked structures are formed on the substrate. The stacked structure includes a first conductive layer, an insulating layer, and a second conductive layer stacked sequentially. At least one of the first conductive layer and the second conductive layer is a half-metal layer. A channel layer covering the stacked structure and a dielectric layer covering the channel layer are formed; A word line extending along a first direction is formed, the word line including a plurality of contact portions and a connecting portion connecting adjacent contact portions, the contact portions surrounding and contacting the side surface of the dielectric layer, the contact portions being opposite at least a portion of the insulating layer.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The channel layer is made of molybdenum sulfide, and / or the half-metal layer is made of bismuth.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The steps of forming a channel layer covering the stacked structure and a dielectric layer covering the channel layer include: The trench layer is deposited on the stacked structure and the substrate, the trench layer covering the top surface and side surfaces of the stacked structure, and the top surface of the substrate; The medium layer is deposited on the channel layer.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Forming word lines extending along a first direction, the word lines including a plurality of contact portions and connecting portions connecting adjacent contact portions, the contact portions surrounding and contacting a side surface of the dielectric layer, the step prior to the step of the contact portions being opposite at least a portion of the insulating layer, further comprising: A first support layer is filled between the stacked structures covering the channel layer and the dielectric layer, the surface of the first support layer facing away from the substrate being higher than the surface of the first conductive layer facing away from the substrate and lower than the surface of the insulating layer facing away from the substrate.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The step of filling a first support layer between the stacked structure covering the channel layer and the dielectric layer, wherein the surface of the first support layer facing away from the substrate is higher than the surface of the first conductive layer facing away from the substrate and lower than the surface of the insulating layer facing away from the substrate includes: A first initial support layer is formed on the dielectric layer, the first initial support layer filling the space between the stacked structure covering the channel layer and the dielectric layer, and the first initial support layer covering the top surface of the dielectric layer; A portion of the first initial support layer is removed, and the remaining first initial support layer forms the first support layer.
6. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The step of forming a word line extending along a first direction, the word line including a plurality of contact portions and a connecting portion connecting adjacent contact portions, the contact portions surrounding and contacting a side surface of the dielectric layer, the contact portions being opposite at least a portion of the insulating layer, includes: An initial word line layer is formed covering the first support layer and the dielectric layer; Remove a portion of the initial character line layer located on the first support layer along a first direction, so that the initial character line layer forms a plurality of spaced intermediate character line layers; Remove the intermediate word line layer on the top surface of the dielectric layer and the portion of the intermediate word line layer on the side surface of the dielectric layer away from the substrate, leaving the remaining intermediate word line layer to form word lines.
7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The step of removing a portion of the initial character line layer located on the first support layer along a first direction to discontinuate the initial character line layer and form multiple spaced intermediate character line layers includes: A mask layer is formed covering the initial word line layer, the mask layer filling the space between the stacked structure covering the channel layer, the dielectric layer and the initial word line layer, and the mask layer covering the top surface of the initial word line layer; A first photoresist layer is formed on the mask layer. The first photoresist layer has trenches extending along a first direction. The orthographic projection of the trenches on the substrate does not overlap with the orthographic projection of the initial word line layer located on the side surface of the stacked structure on the substrate. Using the first photoresist layer as a mask, the mask layer is etched. Using the etched mask layer as a mask, the initial word line layer is etched to form the intermediate word line layer.
8. The method for fabricating a semiconductor structure according to any one of claims 4-7, characterized in that, After forming a word line extending along a first direction, the word line including a plurality of contact portions and connecting portions connecting adjacent contact portions, the contact portions surrounding and contacting a side surface of the dielectric layer, and the contact portions opposing at least a portion of the insulating layer, the method further includes: A second support layer is formed covering the word line, the first support layer, and the dielectric layer, the second support layer being flush with the surface opposite to the substrate; A second photoresist layer is formed on the second support layer. The second photoresist layer has a plurality of openings, which are directly opposite to the stacked structure. Using the second photoresist layer as a mask, the second support layer, the dielectric layer and the channel layer are etched to form a contact hole, which exposes the second conductive layer. A third conductive layer is formed within the contact hole, and the third conductive layer is electrically connected to the second conductive layer.
9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The area of the opening of the contact hole is larger than the area of the bottom of the contact hole.
10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, With a plane perpendicular to the substrate as the cross-section, the cross-sectional shape of the contact hole includes a connected rectangle and a trapezoid, with the rectangle disposed on the side of the trapezoid closer to the substrate, and the bottom edge of the rectangle coinciding with the top base of the trapezoid.
11. The method for fabricating a semiconductor structure according to any one of claims 1-7, characterized in that, The substrate is provided with a plurality of spaced bit lines, which extend along a second direction; Along the second direction, at least one of the stacked structures is provided on each bit line, and the first conductive layer is electrically connected to the bit line.
12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The substrate also contains a shallow trench isolation structure, which is disposed between adjacent bit lines.
13. A semiconductor structure, characterized in that, The semiconductor structure is fabricated by the fabrication method of claim 1, and includes: a stacked structure, a channel layer covering the side surface of the stacked structure, a dielectric layer covering the side surface of the channel layer, and a gate disposed around the dielectric layer. The stacked structure includes a first conductive layer, an insulating layer, and a second conductive layer stacked sequentially. One of the first conductive layer and the second conductive layer is a source, and the other of the first conductive layer and the second conductive layer is a drain. At least one of the source and the drain is a half-metal layer.
14. The semiconductor structure according to claim 13, characterized in that, The channel layer is made of molybdenum sulfide, and / or the half-metal layer is made of bismuth.
15. The semiconductor structure according to claim 13 or 14, characterized in that, The semiconductor structure also includes word lines and bit lines; The bit line is disposed in the substrate, the stacked structure is disposed on the substrate, one of the source and the drain is electrically connected to the bit line, and the word line includes a gate and a connection portion connecting two adjacent gates.
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