A precise measurement method for trap parameters of heterogeneous semiconductor devices

Abstract

A precise measurement method for trap parameters of heterogeneous semiconductor devices relates to the field of semiconductor device reliability. The traditional method of using transient drain-source current changes during trap release to characterize trap parameters ignores the influence of trap filling introduced by test conditions on transient current changes. This part of the influence is included in the transient curve as part of the trap release, resulting in an erroneous analysis of the trap filling mechanism and trap amplitude. The present application proposes a correction method for the measurement error of this transient current curve change. Before the traditional transient current curve test, a step is designed to characterize the transient current changes caused by the test conditions, and the final transient curve changes are corrected using this characterization result. This method can well correct the influence of test conditions on transient current changes during trap release, obtain more accurate transient curve changes, and thus correctly evaluate the internal trap parameters and action mechanisms of heterogeneous semiconductor devices.

Description

Technical field:

[0001] The present invention relates to the field of semiconductor device reliability and is mainly used for extraction and analysis of trap parameters inside heterogeneous semiconductor devices. Background technology:

[0002] Heterojunction semiconductor devices, exemplified by GaN-based high electron mobility transistors (HEMTs), have become ideal core components for both military and civilian electronics applications. Due to their wide bandgap, high operating voltage, and high frequency, they are widely used in 5G communications, radar, and power grid transformation. However, due to inherent material defects and fabrication process limitations, traps can exist within heterojunction devices, leading to poor stability during operation and posing a serious risk to device reliability.

[0003] At present, the methods for trap testing in heterojunction devices mainly include deep level transient spectroscopy (DLTS) testing and transient current method testing. Among them, deep level transient spectroscopy testing is mainly used to characterize traps and defects in GaN materials, and a complete and mature trap testing process for heterojunction devices has not yet been established. Transient current method testing can achieve non-destructive testing of packaged devices, and usually uses the device drain-source current variation curve under constant voltage bias to further analyze the trap information inside the device. However, traditional transient current method testing usually obtains transient current changes under constant test voltage conditions to directly characterize the trap release process, ignoring the impact of the trap filling process caused by the test voltage on the transient current curve. This part of the impact is incorrectly calculated in the trap release process, resulting in errors in the test results, and even causes non-monotonic changes in the transient current curve, leading to incorrect analysis of the trap filling mechanism.

[0004] This technology proposes a correction method for test errors in transient current trap characterization technology. By obtaining the trap filling situation under test voltage conditions, the measured transient current curve is corrected to obtain a more accurate transient current response curve, enabling accurate analysis of the device's internal trap parameters and trap filling mechanism. This method can perform trap testing and analysis on both enhancement-mode and depletion-mode GaN HEMTs produced by different manufacturers, achieving accurate and non-destructive trap testing and trap characterization. Summary of the invention:

[0005] In the measurement of the traditional transient current method, a relatively large filling voltage is usually applied to the device to fill the traps in the device with electrons. Then, the filling voltage is converted to a smaller test voltage condition to monitor the change of the transient current curve during the trap release process. However, during the actual test process, a small test voltage applied to the device can also cause trap filling. Therefore, the measured transient current curve includes the superposition of trap filling under the small voltage condition and the original trap release process. There is a certain measurement error in the trap information calculated based on this, and this superposition process even changes the change trend of the transient current curve, resulting in an incorrect analysis of the trap filling mechanism.

[0006] To solve this problem, we designed a characterization of the trap filling under the test voltage condition before the trap test of the traditional transient current method. Using the result of this characterization to correct the finally measured transient curve, correctly analyze the trap filling mechanism inside the device, and obtain accurate information related to the traps.

[0007] An accurate measurement method for trap parameters of a heterojunction semiconductor device, characterized in that:

[0008] 1. Place the device under test in an incubator at a temperature of T1 and keep it for fifteen minutes so that the device temperature is consistent with the incubator temperature; apply a certain constant gate-source voltage VGS and drain-source voltage VDS as the test voltage to the device. This gate-source voltage VGS should be greater than the device threshold voltage VTH so that the device is in the conducting state; monitor the curve of the drain-source current of the device under test changing with time under the test voltage condition until the transient current is stable and unchanged. The application time of the test voltage is recorded as t1, and the transient current response of the trap filling process under this test voltage condition is recorded as Ids1. The range of the gate-source voltage VGS is VTH < VGS < VTH + 1, the range of the drain-source voltage VDS is 0V < VDS < 2V, and the range of the test time t1 is 10ms to 1000s.

[0009] 2. Place the device under test in an incubator at a temperature of T1 and keep it for fifteen minutes; apply a constant gate-source voltage VGF and drain-source voltage VDF as the filling voltage to the device. This drain-source voltage VDF should be greater than the drain-source voltage VDS under the test voltage condition in step 1), and the application time of the filling voltage is t2. After the time t2 ends, apply the same test voltage condition as in step 1) and the application time is still t1, and monitor the curve of the drain-source current of the device under test changing with time, then the transient current response Ids2 of the trap filling process under this test voltage condition can be obtained. The range of the gate-source voltage VGF is 0V < VGF < 10V, the range of the drain-source voltage VDF is VDS < VDF < 30V; the range of the application time t2 of the filling voltage is 1ms to 100s.

[0010] 3. Subtract Ids2-Ids1 from the transient current response curves obtained in step 2 and step 1 to eliminate the trap filling caused by the test voltage conditions, thereby obtaining the accurate transient current curve Ids corresponding to the trap release process; this curve is completely determined by the traps caused by the bias voltage stress, and therefore accurately reflects the trap information within the device. The number of peaks in the time constant spectrum is the number of traps contained in the transient current response curve, and the horizontal axis value corresponding to the peak is the time constant τ corresponding to the trap. Among them, the transient current responses Ids1 and Ids2 are the drain-source currents of the device under test before and after filling, respectively, with a sampling accuracy of up to 2ms. The data is collected using a logarithmic method with a base of 50. Ids2-Ids1 is the difference between the corresponding currents of Ids1 and Ids2 at the same sampling time point. If the time difference between the sampling points of Ids1 and Ids2 is less than 1ms, it means that they are at the same sampling time point.

[0011] 4. Repeat the testing and processing procedures of steps 1 and 2 at different temperatures (T2, T3, T4, T5) to obtain accurate transient current change curves corresponding to the trap release process at different temperatures; repeat the calculation process of step 3 to obtain the time constant of the trap at different temperatures; draw the Arrhenius equation and read the energy level of the trap by the slope of the fitting line.

[0012] The present invention proposes and corrects for the first time the influence of test voltage conditions on the final transient current curve during the trap test of the transient current method. For the trap test of heterojunction semiconductor devices, this method can accurately obtain the transient current change curve under voltage bias, thereby obtaining accurate trap information and related parameters. Description of the drawings:

[0013] Figure 1 Trap filling and trap release timing diagram under test conditions;

[0014] Figure 2 Comparison of the transient current curves measured at drain-source fill voltages of 5V and 10V and the actual transient current curves after processing;

[0015] Figure 3 Actual transient current curves and corresponding time constant spectra after treatment at drain-source fill voltages of 5V, 10V, 12V, 15V, and 20V;

[0016] Figure 4 The time constant spectra and Arrhenius plots obtained after processing at different temperatures. Specific implementation method:

[0017] The following example shows how to accurately measure the trap parameters of a p-GaN gate HEMT device. The commercial device EPC2007C produced by EPC is used as the device under test.

[0018] 1. Place the device under test in an incubator at 303K and keep it there for fifteen minutes to keep the device temperature consistent with the incubator temperature; apply a gate-source fill voltage VGS of 2.1V and a drain-source fill voltage VDS of 0.5V to the device, and monitor the drain-source current curve of the device under test over time until the drain-source current remains stable. The transient current response Ids1 of the trap filling process under the test voltage condition can be obtained. The test voltage application time t1 is 500s. The test timing is as follows: Figure 1 As shown in (a).

[0019] 2. Place the device under test in a 303K incubator for fifteen minutes; apply a gate-source voltage VGF of 0V and drain-source voltages VDF of 5V and 10V to the device and maintain the voltage bias. The filling voltage application time t2 is 15s. After t2 = 15s, apply a gate-source voltage VGS of 2.1V and a drain-source voltage VDS of 0.5V to the device and maintain the voltage bias time t1 for 500s. That is, the test voltage conditions and test time are the same as those in step 1. At the same time, monitor the curve of the drain-source current of the device under test over time to obtain the transient current response Ids2 of the trap filling process under the test voltage condition; the test timing is as follows: Figure 1 As shown in (b), the measured current response curves under 5V and 10V drain-source voltage VDF are as follows: Figure 2 As shown in (a) and (b), the measured curve corresponding to the drain-source voltage of 5V shows a monotonic decreasing trend, and the measured curve corresponding to the drain-source voltage of 10V shows a non-monotonic change trend, which is inconsistent with the mechanism of trap release of electrons and cannot further obtain the internal trap information of the device.

[0020] 3. Subtract Ids2-Ids1 from the transient current response curves obtained in step 2 and step 1 to eliminate the trap filling caused by the test voltage conditions, thereby obtaining the transient current curve Ids corresponding to the trap release process caused entirely by the bias voltage stress. Among them, the transient current responses Ids1 and Ids2 are the drain-source currents of the device under test before and after filling, respectively. The sampling accuracy is 2ms, and the data is collected by taking points in a logarithmic manner with a base of 50. Ids2-Ids1 is the difference in current corresponding to Ids1 and Ids2 at the same sampling time point. The time difference between the sampling points of Ids1 and Ids2 is less than 1ms, which means they are the same sampling time point. The processed curve is as follows Figure 2 As shown in the figure, the transient curves corresponding to the drain-source voltage VDF of 5V and 10V both show a monotonically increasing trend, which is consistent with the physical mechanism that the drain-source current increases due to the release of electrons from the trap. The drain-source voltage VDF applied during the filling process is changed to 12V, 15V and 20V respectively and the above three steps are repeated to obtain the actual transient current curves Ids under different filling drain-source voltages. Figure 3As shown in (a), the actual transient current curve Ids corresponding to different drain-source voltages VDF all show a monotonically increasing trend, correctly reflecting the trap information contained in the transient curve. The corresponding time constant spectrum is obtained by the structure function method as shown in Figure 3 As shown in (b), there are three peaks in the time constant spectrum, corresponding to three traps in the transient current response curve. These are named DP1, DP2, and DP3 in ascending order of time constant. The horizontal axis value corresponding to each peak is the time constant corresponding to that trap.

[0021] 4. Increase the temperature of the incubator by 10K and repeat the test and processing of steps 1 and 2 to obtain the accurate transient current change curve Ids corresponding to the trap release process at different temperatures, such as Figure 4 (a); The time constant corresponding to each trap is obtained by the structure function method as follows Figure 4 (b) The Arrhenius equation is plotted and the energy levels of the traps are read from the slope of the fitted line; the energy level of DP1 is 0.313 eV, the energy level of DP2 is 0.265 eV, and the energy level of DP3 is 0.467 eV.

Claims

1. An accurate measurement method for trap parameters of a heterojunction semiconductor device, characterized in that: 1) Place the device under test in an incubator at a temperature of T1 and keep it for fifteen minutes so that the device temperature is consistent with the incubator temperature; Apply a gate-source voltage VGS and a drain-source voltage VDS to the device as test voltages, where the gate-source voltage VGS should be greater than the device threshold voltage VTH, so that the device is in the on state; Monitor the curve of the drain-source current of the device under test changing with time until the current is stable and unchanged. The application time of the test voltage is recorded as t1, and the transient current response during the trap filling process under this test voltage condition is recorded as Ids1; 2) Place the device under test in an incubator at a temperature of T1 and keep it for fifteen minutes; Apply a constant gate-source voltage VGF and a drain-source voltage VDF to the device as the filling voltage. The drain-source voltage VDF should be greater than the drain-source voltage VDS under the test voltage condition in step 1). The application time of the filling voltage is t2; After the time t2 ends, apply the same test voltage condition as in step 1) to the device and keep the bias application time still t1, and monitor the curve of the drain-source current of the device under test changing with time, then the transient current response Ids2 during the trap release process under this test voltage condition can be obtained; 3) Subtract the transient current response curves obtained in step 2) and step 1), Ids = Ids2 - Ids1, to exclude the trap filling caused by the test voltage condition, and thus obtain the transient current curve Ids corresponding to the trap release process completely caused by the filling voltage stress; Analyze and process this curve by the structure function method to obtain the corresponding time constant spectrum. The number of peaks in the time constant spectrum is the number of traps contained in the transient current response curve, and the abscissa value corresponding to the peak is the time constant τ corresponding to the trap; 4) Repeat the test and processing procedures of step 1) and step 2) successively at different temperatures to obtain the accurate transient current change curves corresponding to the trap release process at different temperatures; Repeat the calculation process of step 3) to obtain the time constants of the traps at different temperatures, draw the Arrhenius equation and read the trap energy level through the slope of the fitted straight line.

2. The accurate measurement method for trap parameters of a heterojunction semiconductor device according to claim 1, characterized in that: Trap test stage: Apply a gate-source voltage VGS and a drain-source voltage VDS to the device under test as test voltages, where the range of the gate-source voltage VGS is VTH < VGS < VTH + 1, and the range of the drain-source voltage VDS is 0 V < VDS < 2 V. The test time t1 ranges from 10 ms to 1000 s.

3. The accurate measurement method for trap parameters of a heterojunction semiconductor device according to claim 1, characterized in that: Trap filling stage: Apply a constant gate-source voltage VGF and a drain-source voltage VDF to the device as the filling voltage, where the range of the gate-source voltage VGF is 0 V < VGF < 10 V, and the range of the drain-source voltage VDF is VDS < VDF < 30 V; The application time t2 of the filling voltage ranges from 1 ms to 100 s.

4. The method for accurately measuring trap parameters of a heterogeneous semiconductor device according to claim 1, wherein: The sampling accuracy of the transient current responses Ids1 and Ids2 can reach 2 ms, and data is collected by taking points in a logarithmic manner with a base of 50.

5. The method for accurately measuring trap parameters of a heterogeneous semiconductor device according to claim 1, wherein: The transient current curve corresponding to the trap release process completely caused by the filling voltage stress is Ids=Ids2-Ids1, where Ids1 and Ids2 are the drain-source currents of the device under test before and after filling, respectively.

6. The method for accurately measuring trap parameters of a heterogeneous semiconductor device according to claim 1, wherein: The transient current curve corresponding to the trap release process is Ids = Ids2-Ids1, where Ids2-Ids1 is the difference between the currents of Ids1 and Ids2 at the same sampling time point. If the time difference between the sampling points of Ids1 and Ids2 is less than 1ms, they are at the same sampling time point.

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