Implementation Method of High-Speed Serial Communication Based on Optical Isolation between FPGAs

Abstract

The present invention discloses a method for implementing high-speed serial communication based on optical isolation between FPGAs. The sending end and the receiving end of data communication are two independent FPGA boards. An 8b10b encoder / decoder and a parallel / serial or serial / parallel conversion module are provided on the FPGA board. Optical one-way communication without a feedback loop is implemented through an optical module. The output of the optical module is connected to four input IOs of the receiving board, and the data lines are of equal length. The receiving board performs oversampling at an 8-fold sampling rate based on an external 4-input and uses IDDR inside the FPGA with different clock phases to convert the serial data selected and output at the sampling points into parallel data for subsequent processing. In the present invention, FPGAs are used for both receiving and sending, which are inexpensive and have low power consumption. It is applicable to low-power data interfaces that require optical isolation in most designs, and the rate can meet the requirements of medium and small-sized devices.

Description

Technical Field

[0001] The present invention relates to high-speed communication between FPGAs and FPGAs, to the technical field of optically isolated serial communication applications, and to a method for realizing high-speed serial communication based on optical isolation. Background Art

[0002] Optical isolation refers to the use of optical fiber for unidirectional data transmission, leveraging the unidirectional nature of light to provide irreversible, reliable, unidirectional optical transmission. Serial communication, based on optical isolation, primarily utilizes serial communication; parallel communication cannot guarantee data link latency. Currently, serial communication is primarily used for high-speed communications.

[0003] With the development of communications services, data transmission rates are constantly increasing. For security reasons, unidirectional optical fiber is required for data transmission in some special applications. Currently, simple and easy-to-implement optical communication uses high-speed serial modules in FPGAs. These modules are widely used due to their high transmission rates and reliable transmission. However, in applications requiring low power consumption, a small size, and relatively simple functionality, FPGAs with high-speed serial communication modules are expensive, bulky, and consume a lot of power, making them unsuitable. Parallel communication with an on-board clock can also meet high-speed transmission requirements, but it is less secure. In practice, unidirectional optical communication technology based on physical isolation is required. Based on these considerations and practical application requirements, the inexpensive, compact, and low-power FPGA is used to implement optical fiber-based serial communication. Summary of the Invention

[0004] In response to the above-mentioned existing technologies, the present invention proposes a method for implementing high-speed serial communication between FPGAs based on optical isolation. The optical port uses FPGA for reception and transmission, which is inexpensive, low-power, and has a speed that can meet actual usage requirements; the code architecture is simple and highly portable; it is suitable for low-power data interfaces that require optical isolation in most designs, and the speed can meet the needs of small and medium-sized devices.

[0005] To solve the above technical problems, the present invention proposes a method for realizing high-speed serial communication based on optical isolation between FPGAs. The sending end and the receiving end of data communication are two independent FPGA boards, which are respectively denoted as FPGA1 board and FPGA2 board. An 8b10b encoder and a parallel-to-serial conversion module are provided on the FPGA1 board. A serial-to-parallel conversion module and an 8b10b decoder are provided on the FPGA2 board. An optical module is connected between the FPGA1 board and the FPGA2 board, and optical unidirectional communication without a feedback loop is realized through this optical module. The FPGA1 board encodes the received data with 8b10b, and then converts the encoded parallel data into serial data and sends it out through the optical module. The output of the optical module is connected to four input IOs of the FPGA2 board, and the data lines are of equal length. The FPGA1 board outputs the sampled data to the four input IOs of the FPGA2 board through the optical module after serial-to-parallel conversion. The FPGA2 board performs oversampling at an 8-fold sampling rate based on external 4 inputs and using different clock phases of IDDR inside the FPGA, converts the serial data selected and output at the sampling points into parallel data, and performs subsequent processing.

[0006] Furthermore, in the method for realizing high-speed serial communication based on optical isolation between FPGAs according to the present invention:

[0007] Both the FPGA1 board and the FPGA2 board use the PGL22G FPGA of Unisoc for serial transceiver of data, adjustment of sampling window, bit synchronization, and byte synchronization. 8b10b encoding is used for data communication to balance 0 and 1 on the transmission link. The optical module is an optical fiber.

[0008] The oversampling at an 8-fold sampling rate means that the times T1, T2, T3, and T4 from the input port to their respective sampling point IDDRs are equal, and are constrained through a constraint file inside the FPGA, which is equivalent to a signal being sent to four IDDRs for sampling simultaneously. The sampling clocks CLK0°, CLK45°, CLK90°, CLK135°, CLK180°, CLK225°, CLK270°, and CLK315° are of the same source, output through an internal phase-locked loop, with the same frequency and the phase difference meeting the requirements. 8 samplings are performed within one clock cycle, which are respectively SAMPLE1, SAMPLE2, SAMPLE3, SAMPLE4, SAMPLE5, SAMPLE6, SAMPLE7, and SAMPLE8. If the sampling clock of the data is 100 MHz, then the sampling rate at this time is 800 Mbps.

[0009] One sampling of the data line generates 8-fold sampled data, and the sampling points are selected according to the sampled data as shown in the following table:

[0010] Sampling data (8bit) Sampling point 11111111 / 00000000 bit4 11111110 / 00000001 bit5 11111100 / 00000011 bit6 11111000 / 00000111 bit7 11110000 / 00001111 bit0 11100000 / 00011111 bit1 11000000 / 00111111 bit2 10000000 / 01111111 bit3 00000000 / 11111111 bit4

[0011] The endian order of the 8-bit sampled data is {bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0}.

[0012] During the serial-to-parallel conversion process, the data sender will send a synchronization code to complete the synchronization of bit positions and bytes between the sender and the receiver, so that the data sent by the sender can be correctly received at the receiver.

[0013] During 8b10b encoding, the lower 5-bit original data EDCBA is encoded into a 6-bit code abcdei through 5b / 6b encoding, and the higher 3-bit original data HGF is encoded into a 4-bit code fghj through 3b / 4b encoding. Finally, the two parts are combined to form a 10-bit code abcdeifghj; when the 10-bit code is sent, it is sent in the order of sending the lower bits first and then the higher bits.

[0014] Compared with the prior art, the beneficial effects of the present invention are:

[0015] In the implementation method of the present invention, the FPGA is used for the reception and transmission of the optical port, which is cheap, low in power consumption, and the rate can meet the actual usage requirements; in the process of code writing, the basic Verilog language and BRAM resources are used, and each FPGA has these two resources. The code architecture is simple and highly portable. This method is applicable to some low-power data interfaces that require optical isolation in most designs, and the rate can meet the requirements of medium and small-sized devices. In terms of cost and application environment, it provides a greater selection space for the device selection. Brief Description of the Drawings

[0016] Figure 1 It is the structural block diagram of the implementation method of high-speed serial communication based on optical isolation between FPGAs of the present invention;

[0017] Figure 2 It is the internal block diagram of the 8-fold oversampling FPGA in the embodiment of the present invention;

[0018] Figure 3 It is Figure 2 The schematic diagram of the 8-fold oversampling implementation shown;

[0019] Figure 4 It is the schematic diagram of 8b10b encoding in the embodiment of the present invention;

[0020] Figure 5 It is the structural block diagram of traditional optical module communication. Detailed Embodiments

[0021] The design idea of a method for implementing high-speed serial communication based on optical isolation between FPGAs proposed by the present invention is as follows: In traditional optical module communication, as shown in Figure 5 , the high-speed serial communication hardware module carried by the FPGA used has a high transmission rate and strong versatility. However, it is expensive and has high power consumption. For the case where the communication rate requirement is relatively low and the overall power consumption cannot be too high, the above traditional communication method obviously cannot meet the requirements. In response to this, the present invention realizes high-speed serial communication based on optical isolation between FPGAs by using low-power FPGAs. Its basic structure block diagram is as shown in Figure 1 . The FPGAs for data communication are on two independent boards, and the FPGAs are connected by an optical fiber. Unidirectional optical communication without a feedback loop is performed. In order to achieve a higher sampling rate at the receiving end, the output of the optical module is connected to four input IOs of the FPGA, and the data lines are of equal length. The serial-to-parallel conversion module at the receiving end samples the received data with a suitable sampling window and outputs it after serial-to-parallel conversion. The high-speed serial communication FPGA uses the PGL22G FPGA of Unisoc, which is low-cost, low-power, and 100% domestic.

[0022] The following further describes the present invention in conjunction with the accompanying drawings and specific embodiments, but the following embodiments are by no means any limitation to the present invention.

[0023] As shown in Figure 1As shown in the figure, a method for implementing high-speed serial communication based on optical isolation between FPGAs is proposed by the present invention. The sending end and the receiving end of data communication are two independent FPGA boards, which are respectively denoted as FPGA1 board and FPGA2 board. An 8b10b encoder and a parallel-to-serial conversion module are provided on the FPGA1 board; a serial-to-parallel conversion module and an 8b10b decoder are provided on the FPGA2 board; an optical module is connected between the FPGA1 board and the FPGA2 board, and optical unidirectional communication without a feedback loop is realized through the optical module; the FPGA1 board encodes the received data with 8b10b, and then converts the encoded parallel data into serial data and sends it out through the optical module; the output of the optical module is connected to four input IOs of the FPGA2 board, and the data lines are of equal length; the FPGA1 board outputs the sampled data to four input IOs of the FPGA2 board through the optical module after serial-to-parallel conversion; the FPGA2 board performs oversampling at an 8-fold sampling rate based on external 4 inputs and using different clock phases with IDDR inside the FPGA, converts the serial data selected and output at the sampling points into parallel data, and performs subsequent processing. Both the FPGA1 board and the FPGA2 board use the PGL22G FPGA of Unisoc, which is low-cost, low-power, and 100% domestic. The serial-to-parallel conversion and parallel-to-serial conversion modules of PGL22G are mainly for serial transceiver of data, adjustment of sampling window, bit synchronization, and byte synchronization; 8b10b encoding is used for data communication to balance 0 and 1 on the transmission link and ensure the normal operation of the optical module. The optical module is an optical fiber.

[0024] In an embodiment, high-speed serial communication based on optical isolation is performed between FPGAs. The implementation method will be described in detail below.

[0025] (1) Oversampling at an 8-fold sampling rate

[0026] During optical communication, there is physical isolation between the two boards, and only one optical fiber is used for connection, which belongs to asynchronous communication. At the receiving end, in order to select a suitable sampling window and sampling points for sampling, the data needs to be sampled by oversampling.

[0027] In the embodiment of the present invention, there is no inherent oversampling IP core that can be used in the selected FPGA, and it needs to be implemented inside the FPGA by a program. If a single pin is used as the data input, it is difficult to ensure that the delay from the input pin to each sampling register is equal. Unequal delay cannot guarantee the correctness of 8-fold oversampling. Based on the above considerations, oversampling at an 8-fold sampling rate is proposed based on external 4 inputs and using different clock phases with IDDR inside the FPGA.

[0028] As Figure 2 shown, ensure that the time from the input port to the respective sampling point IDDR is equal. Figure 2Among them, for the oversampling with an 8-fold sampling rate, the time T1, T2, T3, and T4 from the input port to their respective sampling points are equal, and it is constrained through a constraint file inside the FPGA, which is equivalent to a signal being sent to four IDDRs for sampling simultaneously. The sampling clocks CLK0°, CLK45°, CLK90°, CLK135°, CLK180°, CLK225°, CLK270°, and CLK315° are of the same source, output through an internal phase-locked loop, with the same frequency and the phase difference meeting the requirements.

[0029] The oversampling principle of the data is as Figure 3 shown. 8 samplings are performed within one clock cycle, namely SAMPLE1, SAMPLE2, SAMPLE3, SAMPLE4, SAMPLE5, SAMPLE6, SAMPLE7, and SAMPLE8. If the sampling clock of the data is 100 MHz, then the sampling rate at this time is 800 Mbps.

[0030] (2) Sampling Point Selection

[0031] One sampling of the data line generates 8-fold sampled data. The sampling points are selected according to the sampled data as follows:

[0032]

[0033]

[0034] The endian order of the 8-bit data of the sampled data is {bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0}.

[0035] (3) Implementation of Serial-to-Parallel and Parallel-to-Serial Conversions

[0036] The parallel-to-serial module mainly converts the parallel data to be sent into serial data and sends it out through an optical module.

[0037] The serial-to-parallel conversion module converts the serial data output by the sampling point selection into parallel data for subsequent processing.

[0038] During the process of serial-to-parallel conversion, the sending end of the data will send a synchronization code to complete the synchronization of bit positions and bytes between the sending end and the receiving end, ensuring that the data sent by the sending end (such as 0x01, 0x02, 0x04, 0x08, etc.) can be correctly received at the receiving end. Normal data transmission can only be carried out after the synchronization code is established.

[0039] At the receiving end of the data, the byte synchronization code sent by the sending end will be received to ensure that the received data can be byte-aligned.

[0040] (4) Implementation of 8b10b Encoding

[0041] The optical module cannot transmit constant high and constant low signals, and data cannot be correctly transmitted during actual testing. Therefore, 8b10b encoding is introduced in the present invention to ensure the balance of 0 and 1 on the transmission line.

[0042] During 8b10b encoding, the lower 5-bit original data EDCBA is encoded into a 6-bit code abcdei through 5b / 6b encoding, and the higher 3-bit original data HGF is encoded into a 4-bit code fghj through 3b / 4b. Finally, the two parts are combined to form a 10-bit code abcdeifghj; when the 10-bit code is sent, it is sent in the order of sending the lower bits first and then the higher bits.

[0043] Figure 4 The principle of 8b10b encoding is shown. In 8b / 10b encoding, K28.1, K28.5, and K28.7 are used as control characters of the K code, called "comma". In any data combination, comma only appears as a control character and does not appear in the data payload part. Therefore, the comma character can be used to indicate the start and end flags of the frame, or the control character that always corrects and aligns with the data stream.

[0044] In summary, the present invention uses a domestic FPGA with low power consumption to implement high-speed serial communication based on optical isolation between FPGAs. The frame structure shown in Figure 1 can meet the requirements. In practice, 8-fold oversampling is used for serial data acquisition, and 8b10b encoding is used to solve the problem of 0 and 1 balance in the line. The hardware structure of the device for implementing high-speed serial communication based on optical isolation between FPGAs in the present invention is simple, and the selected device is also a domestic low-power FPGA device, which can meet the requirements. After testing on the hardware platform, the reliable rate that can be achieved is 230 bps. It has been promoted and used in subsequent projects.

[0045] Although the present invention has been described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many variations without departing from the purpose of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for implementing high-speed serial communication based on optical isolation between FPGAs, characterized in that, The transmitter and receiver of data communication are two independent FPGA boards, denoted as FPGA1 board and FPGA2 board respectively; an 8b10b encoder and a parallel-to-serial conversion module are provided on the FPGA1 board; a serial-to-parallel conversion module and an 8b10b decoder are provided on the FPGA2 board; An optical module is connected between the FPGA1 board and the FPGA2 board, and optical unidirectional communication without a feedback loop is achieved through this optical module; The FPGA1 board caches the received data locally using RAM, encodes the data through an 8b10b encoder, converts the parallel data to be transmitted after encoding into serial data and sends it out through the optical module; the output of the optical module is connected to four input IOs of the FPGA2 board, and the data lines are of equal length; the FPGA1 board outputs the encoded data to four input IOs of the FPGA2 board through serial-to-parallel conversion through the optical module; the FPGA2 board performs oversampling with an 8-fold sampling rate based on external 4 inputs and uses IDDR inside the FPGA with different clock phases, converts the serial data selected and output at the sampling points into parallel data for subsequent processing.

2. The method for implementing high-speed serial communication based on optical isolation between FPGAs according to claim 1, wherein Both the FPGA1 board and the FPGA2 board use PGL22G FPGAs of Unisoc for serial data transceiver, sampling window adjustment, bit synchronization, and byte synchronization; 8b10b encoding is used for data communication to balance 0 and 1 on the transmission link; the optical module is an optical fiber.

3. The method for implementing high-speed serial communication based on optical isolation between FPGAs according to claim 2, characterized in that For the oversampling with an 8-fold sampling rate, the times T1, T2, T3, and T4 from the input port to their respective sampling point IDDRs are equal, and are constrained through a constraint file inside the FPGA, which is equivalent to a signal being sent to four IDDRs for sampling simultaneously. The sampling clocks CLK0°, CLK45°, CLK90°, CLK135°, CLK180°, CLK225°, CLK270°, and CLK315° are of the same source, are output through an internal phase-locked loop, have the same frequency, and the phase difference meets the requirements; 8 samplings are performed within one clock cycle, namely SAMPLE1, SAMPLE2, SAMPLE3, SAMPLE4, SAMPLE5, SAMPLE6, SAMPLE7, and SAMPLE8. If the sampling clock of the data is 100 MHz, the sampling rate at this time is 800 Mbps.

4. The method for realizing high-speed serial communication based on optical isolation between FPGAs according to claim 3, wherein One sampling of the data line generates 8 times the sampled data, and the sampling points are selected according to the sampled data by the following method: When the sampled data is 8 bits of 11111111 / 00000000, the sampling point is bit4; When the sampled data is 8 bits of 11111110 / 00000001, the sampling point is bit5; When the sampled data is 8 bits of 11111100 / 00000011, the sampling point is bit6; When the sampled data is 8 bits of 11111000 / 00000111, the sampling point is bit7; The sampled data is 8-bit, 11110000 / 00001111, and the sampling point is bit0; The sampled data is 8-bit, 11100000 / 00011111, and the sampling point is bit1; The sampled data is 8-bit, 11000000 / 00111111, and the sampling point is bit2; The sampled data is 8-bit, 10000000 / 01111111, and the sampling point is bit3; The sampled data is 8-bit, 00000000 / 11111111, and the sampling point is bit4; The 8-bit data endian order of the sampled data is {bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0}.

5. The method for implementing high-speed serial communication based on optical isolation between FPGAs according to claim 3, wherein During the serial-to-parallel conversion process, the data sender will send a synchronization code to complete the synchronization of bit positions and bytes between the sender and the receiver, so that the data sent by the sender can be correctly received at the receiver.

6. The method for implementing high-speed serial communication based on optical isolation between FPGAs according to claim 1, wherein During 8b10b encoding, the lower 5-bit original data EDCBA is encoded into a 6-bit code abcdei through 5b / 6b encoding, and the upper 3-bit original data HGF is encoded into a 4-bit code fghj through 3b / 4b. Finally, the two parts are combined to form a 10-bit code abcdeifghj; when the 10-bit code is sent, it is sent in the order of sending the lower bits first and then the higher bits.

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