On-chip pulse encoder based on dual-mode integrate-and-fire neuron
By using an on-chip pulse encoder based on dual-mode integral ignition neurons, image pixels are directly encoded into pulse data, solving the problem of low encoding efficiency of the host computer in neuromorphic systems. This achieves high-speed parallel encoding and low-power real-time processing, making it suitable for resource-constrained edge applications.
Patent Information
- Application Number
- CN202310036522.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-09
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2043-01-09
AI Technical Summary
Existing technologies require encoding image pixels and transmitting pulse data via a host computer when verifying FPGA prototypes of neural network cores, resulting in low learning and reasoning efficiency of neuromorphic systems.
Design an on-chip pulse encoder based on dual-mode integral ignition neurons, which can directly encode image pixels into pulse data and achieve high-speed parallel encoding through a global scheduler and pulse arbitrator. It supports burst encoding, first pulse time encoding and rate encoding, and is suitable for event-driven neural network cores.
It achieves real-time on-chip encoding of image pixels, improves encoding throughput, reduces resource requirements, is suitable for resource-constrained real-time intelligent edge applications, and provides a low-cost and low-power encoding scheme.
Smart Images
Figure CN116050487B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of FPGA, and particularly relates to an on-chip pulse encoder based on a dual-mode integral firing neuron. BACKGROUND
[0002] At present, a neuromorphic system containing various event-driven neural network cores has been constructed on an FPGA, but when verifying the FPGA prototype of the neural network core, the host computer needs to code the image pixels and transmit the coded pulse data. The host computer mainly completes two tasks:
[0003] 1) processing the original image data to convert the image pixels into pulse data;
[0004] 2) sending the pulse data to the hardware FPGA through an Ethernet link for the neural network core to learn and infer (such as image classification and identification).
[0005] After the host computer transmits the pulse data required for learning and inference of the neural network core to the neuromorphic system through the Ethernet link, the neural network core can start to learn the overall and edge features of things, train and optimize various network hyperparameters, and reasonably classify and identify new things that have not been learned.
[0006] Therefore, it is necessary to develop an on-chip pulse encoder based on a dual-mode integral firing neuron. SUMMARY
[0007] The application aims to provide an on-chip pulse encoder based on a dual-mode integral firing neuron, which has on-chip real-time coding capability and can directly encode image pixels into pulse data to provide them for a neuromorphic system carrying an event-driven neural network core.
[0008] The on-chip pulse encoder based on a dual-mode integral firing neuron comprises an input pixel memory, a global scheduler, a pulse arbiter, an encoding module array and a parameter register.
[0009] The global scheduler is connected with the input pixel memory, the pulse arbiter and the parameter register respectively.
[0010] The encoding module array is connected with the input pixel memory, the pulse arbiter and the parameter register respectively.
[0011] The encoding module array comprises N encoding cores.
[0012] Under the control of the global scheduler, the pulse encoder configures the mode of neurons in all encoding cores according to the parameter register; before each encoding operation, the input pixel memory takes out N pixels and simultaneously transmits the N pixels to N encoding cores of the encoding module array, and the N encoding cores encode the N pixels in a time-division multiplexing manner in parallel; all pulse AER (address-event representation) data generated by encoding is output from the pulse arbitrator in series;
[0013] The neuron adopts a dual-mode integral firing neuron supporting three neural encoding modes, and the neuron supports a deterministic mode and a random mode.
[0014] The parameter register stores a plurality of configurable parameters, respectively S, T, w, and V th , Ca + , wherein S is an encoding mode, T is an encoding time window, w is a synaptic weight, and V th is a preset membrane potential threshold, and Ca + is a calcium concentration; by configuring parameters S and Ca + , the pulse encoder performs three encoding schemes, wherein the three encoding schemes are burst encoding, first pulse time encoding, and rate encoding.
[0015] Optionally, in the deterministic mode, the neuron updates the neuron membrane potential at each time step, and when the neuron membrane potential at a certain time step reaches or exceeds the preset membrane potential threshold, the neuron emits a pulse and resets the membrane potential to a resting value; when the configured calcium concentration is greater than zero, the neuron emits a pulse only once for an input image pixel within the entire encoding time window.
[0016] In the random mode, the dual-mode integral firing neuron converts a pixel into a firing probability at each time step, and determines whether the neuron emits a pulse at the time step by comparing the size of the firing probability with that of a random number variable.
[0017] Optionally, when the encoding mode of the pulse encoder uses burst encoding, S is configured to be 0, Ga + is 0, and the values of parameters T, w, and V th are configured according to requirements.
[0018] When the encoding mode of the pulse encoder uses rate encoding, S is configured to be 1, Ga + is 0 by default, and the values of parameters T, w, and V th are configured according to requirements.
[0019] When the encoding mode of the pulse encoder uses first pulse time encoding, S is configured to be 0, Ga +> 0, and configuring parameters T, w, V according to the demand th .
[0020] Optionally, the encoding core comprises a weight register, an operation unit, a membrane potential memory, a comparator unit, a comparison potential register, a linear feedback shift register, a firing flag memory and a pulse data register.
[0021] The operation unit is connected with the membrane potential memory and the weight register respectively.
[0022] The comparator unit is connected with the operation unit, the comparison potential register, the linear feedback shift register, the firing flag memory and the pulse data register respectively.
[0023] Optionally, the weight register is a 5-bit×1 weight register.
[0024] The membrane potential memory is a 13-bit×98 membrane potential memory.
[0025] The comparison potential register is a 21-bit×1 comparison potential register.
[0026] The firing flag memory is a 1-bit×98 firing flag memory.
[0027] The pulse data register is a 16-bit×1 pulse data register.
[0028] Optionally, the operation unit is used to update the membrane potential of the neuron.
[0029] When using burst coding or first spike time coding, the membrane potential V m (t) of the neuron of pixel r is defined as:
[0030] V m (t) = V m (t-1) + ΔV m (t);
[0031] ΔV m (t) = w×r;
[0032] When using rate coding, the membrane potential V m (t) of the neuron of pixel r is defined as:
[0033] V m (t) = ΔV m (t) = w×r.
[0034] Wherein, r represents the input pixel at time step t; V m (t) represents the membrane potential of pixel r at time step t, and V m(t-1) represents the neuron membrane potential of pixel r at time step t-1; ΔV m (t) represents the membrane potential increment at time step t; w is the synaptic weight.
[0035] Optionally, the comparator unit is configured to compare the neuron membrane potential V m (t) with a comparison potential V compare .
[0036] At time step t, when the neuron membrane potential V m (t) ≥ V compare .
[0037] If the encoding mode is burst encoding or rate encoding, the neuron emits a spike;
[0038] If the encoding mode is first spike time encoding and the neuron has emitted a spike before time step t, the neuron does not emit a spike;
[0039] wherein: when burst encoding or first spike time encoding is selected, the comparison potential V compare is equal to V th ; when rate encoding is used, the comparison potential V compare is equal to V th × rand.
[0040] Optionally, after the encoding core transmits the encoded AER spike data to the spike arbiter, the global scheduler suspends the encoding operation and the comparison operation of the encoding module array, and then controls the spike arbiter to serially output all the AER spike data; after the output is completed, the global scheduler restarts the encoding module array to start encoding.
[0041] Optionally, the input pixel memory uses an 8-bit × M input pixel memory, and the maximum value of M is 784.
[0042] Optionally, the maximum value of N is 8.
[0043] The present application has the following advantages:
[0044] 1) The present application supports hardware on-chip encoding, and is very suitable for deployment between an image sensor and a neuromorphic system, uses very few resources to perform on-chip real-time encoding on pixels from the sensor, and then transmits the encoded AER spike data to the neuromorphic system for training and inference.
[0045] 2) The present application supports multi-core time division multiplexing, high-speed parallel encoding, and improves the encoding throughput.
[0046] 3) The present application provides a high-speed, low-cost, and low-power encoding scheme for embedded edge real-time processing.
[0047] 4) The present application is very suitable for resource-limited real-time intelligent edge applications.
[0048] In summary, the present application proposes a configurable on-chip pulse encoder based on a dual-mode integral firing neuron, which has an on-chip real-time encoding function. The present application can directly encode image pixels into pulse data, which is provided to a neuromorphic system equipped with an event-driven neural network core. Moreover, the present application has the advantages of low cost, low power consumption and high speed. It can be deployed between an image sensor and a neuromorphic system, real-time encode input pixels into pulse data, and then provide them to a neuromorphic system equipped with an event-driven neural network core. BRIEF DESCRIPTION OF DRAWINGS
[0049] Figure 1 is a schematic diagram of the update of the membrane potential of a traditional integral firing neuron at different time steps;
[0050] Figure 2 is a schematic diagram of the burst encoding in the present embodiment;
[0051] Figure 3 is a schematic diagram of the first pulse time encoding in the present embodiment;
[0052] Figure 4 is a schematic diagram of the rate encoding in the present embodiment;
[0053] Figure 5 is a schematic diagram of the pulse encoder architecture in the present embodiment;
[0054] Figure 6 is a schematic diagram of the circuit of each encoding core in the present embodiment;
[0055] Figure 7 is a schematic diagram of the circuit of the pulse encoding process in the present embodiment;
[0056] Figure 8 is a circuit diagram of the operation unit in the present embodiment;
[0057] Figure 9 is a circuit diagram of the comparator unit in the present embodiment. DETAILED DESCRIPTION
[0058] The present application will be described in detail below with reference to the accompanying drawings.
[0059] As shown in Figure 5 , in the present embodiment, an on-chip pulse encoder based on a dual-mode integral firing neuron mainly includes the following parts:
[0060] 1) Parameter configuration part: The present application supports a dual-mode integral firing neuron, which can select the encoding working mode of the hardware circuit through parameter configuration.
[0061] 2) Encoding part: The present application uses multi-core operation and time-division multiplexing. At each time step, multiple operation cores operate on all pixel encoding in time-division multiplexing. The multi-core high-speed parallel processing encodes the pixel into pulse data according to the encoding mode selected by the parameter configuration. The design supports three encoding schemes, and the three schemes use the same circuit module to implement encoding, which is very resource-saving.
[0062] 3) Pulse arbitration part: When multiple cores have pulse data to be output at a certain time step, the pulse arbitrator starts to work and serially outputs the pulse data in order without omission or loss.
[0063] I. Introduction of dual-mode integrate-and-fire neuron model:
[0064] At present, there are various bionic neuron models, such as Hodgkin-Huxley (HH), Izhikevich, Leaky Integrate-and-Fire (LIF), etc. The HH model and the Izhikevich model have very high bionics, but the calculation complexity is also very high. The LIF neuron model only retains the most core bionic characteristics: membrane potential leakage, membrane potential accumulation and neuron pulse emission, thereby avoiding complex operation and greatly reducing the model operation complexity. After abandoning the membrane potential leakage feature of the LIF neuron model, the model will degenerate into an integrate-and-fire (IF) model, which is easier to implement in hardware processing. Therefore, based on the characteristics of the integrate-and-fire neuron, a dual-mode integrate-and-fire neuron model is designed in this paper.
[0065] 1.1 Traditional integrate-and-fire neuron model
[0066] The traditional integrate-and-fire neuron model processes pulse data. For example, the membrane potential update formula of the time-step-based integrate-and-fire model neuron is as formula (1):
[0067] V m (t)=V m (t-1)+w×s(t) (1)
[0068] Wherein, V m (t) represents the neuron membrane potential at time step t, V m (t-1) represents the neuron membrane potential at time step t-1, w is the synaptic weight, and s(t) represents the input pulse sequence (if there is a pulse at time step t, s(t)=1; otherwise, s(t)=0). When V m (t) reaches a preset membrane potential threshold V th at a certain time step t, the neuron will emit a pulse, and the membrane potential will be reset to the resting value, and the calculation formula is as formula (2):
[0069] V m (t)=V m (t)-V th (2)
[0070] Among them, the parameters w and V of the traditional integral ignition neuron th It is configurable. For example... Figure 1 As shown, the membrane potential V of a conventional integral ignition neuron is illustrated. m Updates at different time steps t.
[0071] 1.2 Dual-mode Integral Ignition Neuron
[0072] In this embodiment, a dual-mode integral firing neuron supporting three types of neural encoding is employed. Based on a time-step-based integral firing neuron, image pixels are encoded to convert pixels into AER (address-event representation) pulse data containing pulse addresses and timestamps. When encoding the input pixel r, the neuron supports deterministic and random modes, and the circuit has a configurable parameter set: (S, T, w, V). th Ca + ), where S is the encoding method, T is the encoding time window, w is the synaptic weight, and V is the encoding time window. th As a preset membrane potential threshold, Ca + This refers to calcium concentration. The following describes two neuron modes and how to configure parameters to enable the circuit to execute three encoding schemes (including burst coding, first-pulse timing coding, and rate coding).
[0073] 1.2.1 Determine the mode
[0074] In deterministic mode, the dual-mode integral firing neuron updates its membrane potential at each time step. When the neuron's membrane potential reaches or exceeds a preset membrane potential threshold at a certain time step, the neuron fires a pulse and simultaneously resets its membrane potential to the resting value. Furthermore, if the configured calcium concentration is greater than zero, the neuron fires only one pulse per input image pixel within the entire encoding time window.
[0075] 1.2.2 Random Mode
[0076] In random mode, the dual-mode integral firing neuron no longer updates the membrane potential in a deterministic manner, but instead converts the pixel into an emission probability at each time step. The neuron determines whether to fire a pulse at that time step by comparing the emission probability with the magnitude of a random number variable.
[0077] 1.3 Implementation of Three Encoding Methods
[0078] 1.3.1 Burst Coding
[0079] In this embodiment, the burst coding converts each input pixel into a sequence of multiple pulses with equal time intervals within a coding time window, the greater the pixel value, the shorter the time interval between pulses, and the more the corresponding number of pulses. The burst coding schematic is shown in Figure 2 When using burst coding, the pulse encoder should configure parameters S = 0 and Ga + = 0, where the neuron is in a deterministic mode. When encoding the input pixel r, the neuron model updates the membrane potential at each time step t by equation (3) (V m (0) = 0V at t = 0):
[0080] V m (t) = V m (t-1) + w x r (3)
[0081] where V m (t) and V m (t-1) represent the neuron membrane potential of pixel r at time step t and time step t-1, respectively, w is the synaptic weight, and r represents the input pixel at time step t. When the neuron membrane potential V m (t) reaches or exceeds the preset membrane potential threshold V th , the neuron emits a pulse, and the time step t is recorded as the time stamp of the pixel encoding into pulse data.
[0082] 1.3.2 First spike time coding
[0083] The first spike time coding converts the input image pixel into a single pulse event. The first spike time coding scheme believes that the greater the pixel value, the more information it carries, and the earlier the corresponding emitted pulse, and the encoding schematic is shown in Figure 3 When using the first spike time coding, the pulse encoder needs to configure parameters S = 0 and Ga + > 0, where the neuron is in a deterministic mode. When the calcium concentration Ca + is greater than zero, the neuron will limit the membrane potential after emitting a pulse, so the neuron will not emit more pulses. Therefore, only the time step t of the first pulse emitted by the neuron needs to be recorded as the time stamp of the pixel encoding into pulse data.
[0084] 1.3.3 Rate coding
[0085] The rate coding model is the most widely used coding model in neural network models. The rate coding principle is shown in Figure 4 . It encodes the strength of the external stimulus into the probability of pulse emission, that is, the stronger the external stimulus, the greater the probability of pulse emission of the corresponding neuron. When using rate coding, the pulse encoder only needs to configure parameter S = 1, where the calcium concentration Ca +The signal is masked. In this encoding scheme, the neuron is in a random mode, and the pixel value r is normalized to an emission probability P. Whether the neuron fires a pulse at time step t is determined by comparing P with a random number variable rand, where rand is generated online by the circuit. The emission probability P is calculated as follows: at each time step t, the input pixel r is multiplied by the synaptic weight w, and then calculated according to a preset membrane potential threshold V. th Normalized to the emission probability P, defined by equation (4):
[0086]
[0087] Since the hardware is not convenient for performing the division operation in equation (4), the preset membrane potential threshold V can be used. th Multiply by the random number rand (i.e., rand × V) th Then, it is compared with the synaptic weight multiplied by the input pixel (i.e., w×r) to determine whether to emit a pulse. Only when w×r ≥ rand×V th When a neuron fires a pulse, it fires a pulse; otherwise, it does not fire a pulse. If a pulse is fired, this time step t is used as the timestamp for encoding the pixel as pulse data.
[0088] 1.4 Configurable Encoding Method
[0089] If the user selects burst coding, the parameters S=0 and Ga must be configured. + =0. Then configure the parameter group (T, w, V) according to the requirements. th The numerical values (e.g., T=50, w=2, V) th =4096).
[0090] If the user selects the first pulse time encoding, parameters S=0 and Ga must be configured. + =1. Then configure the parameter group (T, w, V) according to the requirements. th The numerical values (e.g., T=50, w=2, V) th =4096).
[0091] If the user selects rate encoding, parameter S = 1 must be configured. Then, configure the parameter group (T, w, V) according to requirements. th The numerical values (e.g., T=50, w=2, V) th =4096), at this time the parameter Ga + You can leave it unset (the default value is 0 if not set).
[0092] II. Pulse Encoder Hardware Design
[0093] like Figure 5The diagram shows the overall architecture of the on-chip pulse encoder based on dual-mode integral ignition neurons proposed in this embodiment. This pulse encoder consists of a parameter register, a global scheduler, and an 8-bit × M input pixel memory (M supports a maximum value of M). max =784, i.e., the number of stored pixels), and an array of encoding modules containing N encoding cores (N supports a maximum value of N). max =8) It consists of a pulse arbitrator. The global scheduler is connected to the input pixel memory, the pulse arbitrator, and the parameter register, respectively. The encoding module array is connected to the input pixel memory, the pulse arbitrator, and the parameter register, respectively.
[0094] Under the control of the global scheduler, the pulse encoder performs the following four tasks:
[0095] 1) Configure the pattern of neurons in all coding cores (i.e., the coding scheme of the circuit) according to the parameter register.
[0096] 2) Before each encoding operation, N pixels are retrieved from the input pixel memory and simultaneously passed to N encoding cores.
[0097] 3) N encoding cores encode these pixels in parallel using time-division multiplexing.
[0098] 4) All pulse AER data generated by encoding is serially output from the pulse arbitrator.
[0099] The design of the module circuit will be described in detail next.
[0100] 2.2 Core Coding Design
[0101] The encoding core is a key circuit block in the pulse encoder hardware circuit and a fundamental component of the encoding module array. Within the entire encoding time window, each encoding core encodes 98 pixels of data (8 cores encode 784 pixels in parallel). The circuit design of the encoding core is as follows... Figure 6 As shown, the encoding core includes a weight register, an arithmetic unit, a membrane potential memory, a comparator unit, a comparison potential register, a linear feedback shift register, a transmit flag memory, and a pulse data register. The arithmetic unit is connected to the membrane potential memory and the weight register, respectively. The comparator unit is connected to the arithmetic unit, the comparison potential register, the linear feedback shift register, the transmit flag memory, and the pulse data register, respectively. All encoding schemes use the same circuit to perform the encoding operation. Figure 7As shown. In this embodiment, the weight register is a 5-bit × 1 weight register, the membrane potential memory is a 13-bit × 98 membrane potential memory, the comparison potential register is a 21-bit × 1 comparison potential register, the transmit flag memory is a 1-bit × 98 transmit flag memory, and the pulse data register is a 16-bit × 1 pulse data register. The 8-bit unsigned fraction rand provided for rate encoding is generated online by a linear feedback shift register.
[0102] 2.2.1 Operation Unit
[0103] like Figure 8 As shown, in this embodiment, the arithmetic unit is used to update the neuron membrane potential. When burst coding or first-pulse time coding is used, where parameter S = 0, the neuron membrane potential V of pixel r is... m (t) is defined as:
[0104] V m (t)=V m (t-1)+ΔV m (t) (5)
[0105] ΔV m (t)=w×r (6)
[0106] Where: r represents the input pixel at time step t; V m (t) and V m (t-1) represent the neuron membrane potentials of pixel r at time step t and time step t-1, respectively; ΔV m (t) represents the membrane potential increment at time step t; w is the synaptic weight; ΔV m (t) represents the membrane potential increment at time step t. When rate encoding is used (S=1), the neuron membrane potential V of pixel r is... m (t) is defined as:
[0107] V m (t)=ΔV m (t)=w×r (7)
[0108] 2.2.2 Comparator Unit
[0109] like Figure 9 As shown, in this embodiment, the comparator unit converts the neuron's membrane potential V m (t) and comparison potential V compare Compare them.
[0110] At time step t, when the neuron membrane potential V m (t)≥V compare When the encoding method is burst encoding (S=0, Ga += 0) or rate coding (S = 1), the neuron will fire a spike. If the encoding is first spike time coding (S = 0, Ga + > 0) and the neuron has already fired a spike before time step t, the neuron will not fire a spike. Wherein: when the burst coding or the first spike time coding is selected, the comparison potential V compare is equal to V th ; when the rate coding is used, the comparison potential V compare is equal to V th * rand.
[0111] 2.3 Spike arbiter
[0112] After the encoding core transmits the encoded AER spike data to the spike arbiter, the global scheduler suspends the encoding operation and the comparison operation of the encoding module array, and then controls the spike arbiter to serially output all the AER spike data. After the output is completed, the global scheduler restarts the encoding module array to start encoding.
[0113] The above embodiment is a preferred embodiment of the method of the present application, but the embodiment of the method of the present application is not limited by the above embodiment, and any change, modification, replacement, combination, simplification made without departing from the spirit and principle of the present application shall be an equivalent replacement manner, and all shall be included in the protection scope of the present application.
Claims
1. An on-chip pulse encoder based on a dual-mode integrate-and-fire neuron, characterized by: The pulse encoder comprises an input pixel memory, a global scheduler, a pulse arbiter, an encoding module array and a parameter register; The global scheduler is connected with the input pixel memory, the pulse arbiter and the parameter register respectively; The encoding module array is connected with the input pixel memory, the pulse arbiter and the parameter register respectively; The coding module array comprises N coding cores; Under the control of the global scheduler, the pulse encoder configures the mode of neurons in all encoding cores according to parameter registers; before each encoding operation, the input pixel memory takes out N pixels and simultaneously delivers the N pixels to the N encoding cores of the encoding module array, N encoding cores encode the N pixels in a time-division multiplexing manner in parallel; all the pulse AER data generated by encoding is output in series from the pulse arbitrator; The neuron adopts a dual-mode integral firing neuron supporting three kinds of neural encoding, and the neuron supports a deterministic mode and a random mode; The parameter register stores a plurality of configurable parameters, respectively S , T , w , V th , Ca + , wherein S is an encoding mode, T is an encoding time window, w is a synaptic weight, V th is a preset membrane potential threshold, Ca + is a calcium concentration; by configuring parameters S and Ca + , the pulse encoder performs three encoding schemes, wherein the three encoding schemes are burst encoding, first pulse time encoding and rate encoding, respectively.
2. The dual-mode integral firing neuron based on-chip pulse encoder of claim 1, wherein: In the deterministic mode, the neuron updates the neuron membrane potential at each time step, and when the neuron membrane potential reaches or exceeds a preset membrane potential threshold at a certain time step, the neuron emits a pulse, and the membrane potential is reset to a resting value; when the configured calcium concentration is greater than zero, the neuron emits a pulse only once for an input image pixel within an entire encoding time window; In the random mode, the dual-mode integral firing neuron converts a pixel into a firing probability at each time step, and determines whether the neuron emits a pulse at the time step by comparing the size of the firing probability with that of a random number variable.
3. The on-chip pulse encoder based on the dual-mode integral firing neuron according to claim 2, wherein: When the encoding method of the pulse encoder uses burst encoding, the configuration S = 0, Ga + = 0, and parameters are configured according to requirements T , w , V th the value of the number When the encoding method of the pulse encoder uses rate coding, configure S = 1, by default Ga + = 0, and configure the parameters as needed T , w , V th the value of the number; When the encoding of the pulse encoder uses the first pulse time encoding, the configuration S = 0, Ga + > 0, the parameters are configured according to the requirements T , w , V th the value of the number.
4. The dual-mode integral firing neuron based on-chip pulse encoder of claim 3, wherein: The encoding core comprises a weight register, an operation unit, a membrane potential memory, a comparator unit, a comparison potential register, a linear feedback shift register, a firing flag memory and a pulse data register; The operation unit is connected with the membrane potential memory and the weight register respectively; The comparator unit is connected with the operation unit, the comparison potential register, the linear feedback shift register, the firing flag memory and the pulse data register respectively.
5. The dual-mode integral firing neuron based on-chip pulse encoder of claim 4, wherein: The weight register adopts a 5-bit x 1 weight register; The membrane potential memory adopts a 13-bit x 98 membrane potential memory; The comparison potential register adopts a 21-bit x 1 comparison potential register; The firing flag memory adopts a 1-bit x 98 firing flag memory; The pulse data register adopts a 16-bit x 1 pulse data register.
6. The on-chip pulse encoder based on dual-mode integrate-and-fire neuron according to claim 4 or 5, characterized in that: The operation unit is used to update the neuron membrane potential; When using burst coding or first-pulse time coding, the pixel r neuron membrane potential V m ( t ) is defined as: ； ； When using rate coding, the pixel r neuron membrane potential V m ( t ) is defined as: ； where: r represents the time step t input pixel at time step V m ( t ) represents the membrane potential of pixel r at time step t , V m ( t - 1) represents the membrane potential of pixel r at time step t - 1; Δ V m ( t ) represents the increment of the membrane potential at time step t ; w is the synaptic weight.
7. The dual-mode integral firing neuron based on-chip pulse encoder of claim 6, wherein: The comparator unit is configured to compare the neuron membrane potential V m ( t ) with a comparison potential V compare At time step t When the neuronal membrane potential V m ( t ) ≥ V compare ; When the encoding mode is burst encoding or rate encoding, the neuron emits a pulse; If the encoding is first spike time encoding and the neuron has already fired a spike before the time step t then the neuron does not fire a spike; wherein: when burst coding or first pulse time coding is selected, the comparison potential V compare is equal to V th when rate coding is employed, the comparison potential V compare is equal to V th x rand, rand is a random number.
8. The dual-mode integral firing neuron based on-chip pulse encoder according to claim 1 or 2 or 3 or 4 or 5 or 7, characterized in that: After the encoding core transmits the AER pulse data obtained through encoding to the pulse arbiter, the global scheduler suspends the encoding operation and the comparison operation of the encoding module array, and then controls the pulse arbiter to serially output all AER pulse data; after the output is completed, the global scheduler restarts the encoding module array to start encoding.
9. The dual-mode integral firing neuron based on-chip pulse encoder of claim 8, wherein: The input pixel memory uses 8 bits x M input pixel memory, M The maximum value is 784.
10. The dual-mode integral firing neuron based on-chip pulse encoder of claim 9, wherein: The maximum value of the N is 8.