MOSCAP device trench preparation method and MOSCAP device

Abstract

The application provides a MOSCAP device trench preparation method, comprising the following steps: S1, providing a wafer to be processed, performing photoetching and ion implantation on the wafer to form a first ion implantation area; S2, annealing the wafer to diffuse the first ion implantation area to form a second ion implantation area; S3, growing an oxide layer on the wafer; and S4, removing the oxide layer by wet etching to form a target trench structure. The preparation method can improve the relatively sharp angle formed in the dry etching process, thereby reducing the stress at the angle and improving the reliability of the device. The application further provides a MOSCAP device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a MOSCAP device trench preparation method and a MOSCAP device. BACKGROUND

[0002] MOSCAP capacitors are widely used in integrated circuit design due to their compatibility with traditional processes, and are used to store electric charges to form complete circuit functions. With the development of semiconductor technology and integration, higher requirements for the density and reliability of capacitors in the design process have been proposed. Current mainstream methods for increasing capacitors include using new dielectric materials, reducing the thickness of the dielectric layer, and increasing the area of the upper and lower plates.

[0003] The above three solutions have corresponding advantages and disadvantages. Using new dielectric materials has compatibility problems with traditional processes, and redeveloping old processes cannot meet the development requirements. Reducing the thickness of the dielectric layer can significantly increase the capacitance density of the device, but a too-thin gate oxide layer can cause breakdown and reliability problems. Increasing the area of the upper and lower plates can improve the capacitance value of a single device, but does not significantly improve the capacitance density of the overall circuit, which is not conducive to increasing the integration. Therefore, a trench MOSCAP device has emerged. This device structure belongs to the third method described above. Without changing the unit area of the device, the upper and lower plates are bent through the trench, thereby increasing the area of the upper and lower plates and effectively improving the capacitance density, which significantly helps to improve the integration of the circuit.

[0004] However, the trench process presents a significant challenge to reliability. Since the current trench process mainly uses dry etching process, there are some relatively sharp angles at the bottom and top of the trench. The stress at this location is significantly greater than that at other flat surfaces, which affects the subsequent gate oxide layer growth process, affects the quality of the oxide layer, and thus affects the reliability of the device.

[0005] Therefore, it is necessary to provide a new MOSCAP device trench preparation method and a MOSCAP device to solve the above problems in the prior art. SUMMARY

[0006] The present application aims to provide a MOSCAP device trench preparation method and a MOSCAP device that can improve the relatively sharp angles formed during the dry etching process, thereby reducing the stress at this location and improving the reliability of the device.

[0007] To achieve the above-mentioned purpose, the MOSCAP device trench preparation method of the present application comprises the following steps,

[0008] S1: providing a wafer to be processed, performing lithography and ion implantation on the wafer to form a first ion implantation region;

[0009] S2: annealing the wafer to diffuse the first ion implantation region to form a second ion implantation region;

[0010] S3: growing an oxide layer on the wafer;

[0011] S4: removing the oxide layer by wet etching to form a target trench structure.

[0012] The MOSCAP device trench preparation method has the following advantages: compared with a conventional dry etching process, the preparation method changes the properties of a silicon surface by high-dose ion implantation, makes the ion distribution more uniform by annealing, then places the wafer in a furnace tube for oxidation, and the growth rate of the oxide layer in the region subjected to ion implantation is obviously higher than that in the region not subjected to ion implantation, and then removes the surface oxide by wet etching with high selectivity, so that the region subjected to ion implantation consumes more silicon due to the faster growth rate of the oxide layer, thereby a relatively gentle trench can be obtained, the appearance of the trench is improved, and the reliability of the device is improved.

[0013] Optionally, the step of performing lithography and ion implantation on the wafer further comprises forming a shallow trench isolation on the wafer surface before the step.

[0014] Optionally, the first ion implantation region is located at the edge of the shallow trench isolation.

[0015] Optionally, the step of performing lithography on the wafer surface to form a shallow trench isolation comprises forming a shallow trench isolation after performing the processes of lithography, etching, cleaning, medium deposition, and CMP on the wafer surface.

[0016] Optionally, the step of forming a target trench structure further comprises growing a gate oxide layer and a polycrystalline layer on the wafer again after the step is completed.

[0017] Optionally, in the step of providing a wafer to be processed, performing lithography and ion implantation on the wafer to form a first ion implantation region, the implanted ions include arsenic ions, and the implantation dose is 1E15-6E15 ions / square centimeter.

[0018] Optionally, the step of growing an oxide layer on the wafer comprises oxidizing the wafer by using a dry oxidation process or a wet oxidation process to generate an oxide layer.

[0019] The application further provides a MOSCAP device prepared by the preparation method of the application, which comprises a substrate and a target trench structure arranged on the substrate, and the bottom surface and the wall extending to the surface of the substrate of the target trench structure are all circular arc surfaces.

[0020] The MOSCAP device of the application has a relatively gentle trench, and the morphology of the trench is improved, thereby improving the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A flow chart of the preparation method of the trench of the MOSCAP device of the application;

[0022] Figure 2 A wafer cross-sectional schematic diagram of forming a shallow trench isolation in the embodiment of the application;

[0023] Figure 3 A wafer cross-sectional schematic diagram of forming a first ion implantation region in the embodiment of the application;

[0024] Figure 4 A wafer cross-sectional schematic diagram of forming a second ion implantation region in the embodiment of the application;

[0025] Figure 5 A wafer cross-sectional schematic diagram after forming an oxide layer in the embodiment of the application;

[0026] Figure 6 A cross-sectional schematic diagram of forming a target trench structure in the embodiment of the application;

[0027] Figure 7 A cross-sectional schematic diagram of the trench MOSCAP device in which a gate oxide layer and a polycrystalline layer are grown in the embodiment of the application. DETAILED DESCRIPTION

[0028] In order to make the objects, technical solutions and advantages of the application clearer, the technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings of the application. Obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the common meanings of the same by those skilled in the art. The similar words such as “comprise” used herein mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, and do not exclude other elements or objects.

[0029] Figure 1 A flow chart of the trench preparation method for the MOSCAP device of the present application is shown in FIG. 1. Figure 1 The trench preparation method for the MOSCAP device of the present application comprises the following steps,

[0030] S1: providing a wafer to be processed, and performing photoetching and ion implantation on the wafer to form a first ion implantation region;

[0031] S2: annealing the wafer to diffuse the first ion implantation region to form a second ion implantation region;

[0032] S3: growing an oxide layer on the wafer;

[0033] S4: removing the oxide layer by wet etching to form a target trench structure.

[0034] The trench preparation method for the MOSCAP device of the present application has the following advantages: compared with the conventional dry etching process, the preparation method of the present application first changes the properties of the silicon surface by high-dose ion implantation, then makes the ion distribution more uniform by annealing, and then oxidizes the wafer in a furnace tube. The growth rate of the oxide layer in the region subjected to ion implantation is significantly higher than that in the region not subjected to ion implantation. Then, the surface oxide is removed by the high selectivity of wet etching. The region subjected to ion implantation consumes more silicon due to the faster growth rate of the oxide layer, so that a relatively gentle trench can be obtained, the morphology of the trench is improved, and the reliability of the device is improved.

[0035] In some embodiments, the step of performing photoetching and ion implantation on the wafer further comprises forming a shallow trench isolation on the surface of the wafer before the step is performed.

[0036] In some embodiments, the first ion implantation region is located at the edge of the shallow trench isolation.

[0037] In some embodiments, the step of forming a shallow trench isolation on the surface of the wafer comprises forming a shallow trench isolation after performing the photoetching, etching, cleaning, medium deposition, and CMP process on the surface of the wafer.

[0038] In some embodiments, the step of forming a target trench structure is further comprises growing a gate oxide layer and a polycrystalline layer on the wafer again after the step is performed.

[0039] In some embodiments, the ions implanted in the step of providing a wafer to be processed, lithographing on the wafer, implanting ions to form a first ion implantation region, include arsenic ions, and the implantation dose is 1E15-6E15 ions / cm2. In some specific embodiments, the dose of the arsenic ions is 2E15 ions / cm2. In some other specific embodiments, the dose of the arsenic ions is 4E15 ions / cm2.

[0040] In some embodiments, the step of growing an oxide layer on the wafer includes oxidizing the wafer to form an oxide layer using a dry oxidation process or a wet oxidation process.

[0041] The present application also provides a MOSCAP device prepared by the preparation method of the present application, which includes a wafer and a target trench structure disposed on the substrate, and the bottom surface and the wall extending to the surface of the wafer of the target trench structure are both arc surfaces.

[0042] The MOSCAP device of the present application has a relatively gentle trench, and the morphology of the trench is improved, thereby improving the reliability of the device.

[0043] The technical solutions of the present application are described in detail below through Example 1.

[0044] Example 1

[0045] Figure 2 Fig. 1 is a cross-sectional view of a wafer for forming a shallow trench isolation in a specific embodiment of the present application, Figure 3 Fig. 2 is a cross-sectional view of a wafer for forming a first ion implantation region in a specific embodiment of the present application, Figure 4 Fig. 3 is a cross-sectional view of a wafer for forming a second ion implantation region in a specific embodiment of the present application, Figure 5 Fig. 4 is a cross-sectional view of a wafer after forming an oxide layer in a specific embodiment of the present application, Figure 6 Fig. 5 is a cross-sectional view of a wafer for forming a target trench structure in a specific embodiment of the present application, Figure 7 Fig. 6 is a cross-sectional view of a trench MOSCAP device in which a gate oxide layer and a polycrystalline layer are grown in a specific embodiment of the present application. The specific steps of the trench preparation method of the MOSCAP device of the present application are described below in combination with Figures 2-7 The specific steps of the trench preparation method of the MOSCAP device of the present application are described below in combination with

[0046] Step S10 is performed: a wafer to be processed is provided, which includes a silicon substrate 10, and the surface of the silicon substrate 10 is subjected to lithography, etching, cleaning, medium deposition, and CMP treatment to form two shallow trench isolations 101.

[0047] Step S20 is performed after step S10, photoresist is coated on the silicon substrate 10, and photoetching is performed, the photoresist that has been patterned is used as a mask, arsenic ions with a dose of 1E15 ions / cm2 are implanted into the silicon substrate 10, the photoresist is removed by cleaning, and the first ion implantation region 1001 is formed;

[0048] Step S30 is performed after step S20, the wafer is placed in an annealing device, the temperature is controlled to be 1050C, and the time is controlled to be 30S, so that the first ion implantation region 1001 is diffused to a desired position, and the second ion implantation region 1002 is formed;

[0049] Step S40 is performed after step S30, the wafer is placed in an oxidation furnace, and oxidation is performed by a dry oxidation method or a wet oxidation method, so that the oxide layer 103 is formed, and the oxide layer 103 is composed of silicon oxide;

[0050] Step S50 is performed, the wafer on which the oxide layer 103 is grown is subjected to a wet etching process, the oxide layer 103 is removed, and the target trench structure 1004 is formed;

[0051] Step S60 is performed, the wafer on which the oxide layer 103 is removed is subjected to processes such as oxidation, photoetching, etching, and medium deposition, so that the gate oxide layer 105 and the polycrystal layer 106 are formed, and the trench MOSCAP device is prepared.

[0052] Referring to Figure 2 , after step S10, two shallow trench isolations 101 with a spacing are formed on the substrate 101.

[0053] Referring to Figure 3 , after step S20, the first ion implantation region 1001 is formed after arsenic ions with a dose of 1E15 ions / cm2 are implanted into the silicon substrate 10, the first ion implantation region 1001 is located between the two shallow trench isolations 101 and at the edge of one of the shallow trench isolations 101, and photoresist 102 is attached to the surface of the silicon substrate 10 above the first ion implantation region 1001. The high-dose ion doping used in the present application can change the properties of the silicon wafer surface, and thus change the oxidation rate.

[0054] Referring to Figure 4 , after step S30, the temperature and time of annealing are controlled so that the arsenic ions are diffused to a desired position to form the second ion implantation region 1002, and the ions are more uniformly distributed after the annealing diffusion.

[0055] Referring to Figure 5After step S40 is performed, the oxide layer 103 formed covers the surface of the wafer, and the growth rate of the oxide layer in the region subjected to ion implantation is obviously higher than that in the region not subjected to ion implantation, and the consumption of silicon in the region subjected to ion implantation and the region not subjected to ion implantation is 1.8:1-2.2:1 when generating silicon oxide. In some specific embodiments, the consumption of silicon in the region subjected to ion implantation and the region not subjected to ion implantation is 2:1 when generating silicon oxide.

[0056] With reference to Figure 6 After step S50 is performed, the bottom surface and the wall of the target trench structure 1004 formed by the wet etching process are both arc surfaces, and the trench is relatively gentle, the preparation method of the present application can improve the morphology of the trench and improve the reliability of the device.

[0057] With reference to Figure 7 After step S60 is performed, the target trench structure 1004 is prepared, and then a gate oxide layer 105 and a polycrystalline layer 106 are formed on the surface of the wafer through processes such as oxidation, photolithography, etching, and dielectric deposition, and the preparation method of the present application is compatible with the traditional process and can form a complete device structure.

[0058] Although the embodiments of the present application are described in detail above, it is obvious for those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes all belong to the scope and spirit of the present application described in the claims. Moreover, the present application described herein can have other embodiments, and can be implemented or realized in various ways.

Claims

1. A method for fabricating trenches in a MOSCAP device, characterized in that, The method comprises the following steps: S1: providing a wafer to be processed, forming a shallow trench isolation on the wafer surface, and performing photolithography and ion implantation on the wafer to form a first ion implantation region at the edge of the shallow trench isolation; S2: annealing the wafer to diffuse the first ion implantation region to form a second ion implantation region; S3: growing an oxide layer on the wafer; S4: removing the oxide layer by wet etching to form a target trench structure.

2. The method of claim 1, wherein the MOSCAP device trench is formed by: The step of forming a shallow trench isolation on the wafer surface comprises the following steps: performing photolithography, etching, cleaning, medium deposition and CMP process on the wafer surface to form a shallow trench isolation.

3. The method of claim 1, wherein the MOSCAP device trench is formed by: After the step of forming a target trench structure is completed, the method further comprises the steps of: growing a gate oxide layer and a polycrystalline layer on the wafer again.

4. The method of claim 1, wherein the MOSCAP device trench is formed by a process comprising: In the step of providing a wafer to be processed and performing photolithography and ion implantation on the wafer to form a first ion implantation region, the implanted ions include arsenic ions, and the implantation dose is 1E15-6E15 ions / cm2.

5. The method of claim 1, wherein the MOSCAP device trench is formed by a process comprising: The step of growing an oxide layer on the wafer comprises using a dry oxidation process or a wet oxidation process to oxidize the wafer to generate an oxide layer. ​ 6. A MOSCAP device, characterized by, The MOSCAP device prepared by the method of any one of claims 1-5 comprises a substrate and a target trench structure disposed on the substrate, and the bottom surface and the wall extending to the surface of the substrate of the target trench structure are both circular arc surfaces.

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