Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present disclosure discloses a method for manufacturing a semiconductor device, comprising: providing a substrate having at least one trench; forming a first polysilicon layer within the trench, the first polysilicon layer covering the sidewalls and bottom of the trench but not completely filling the trench; performing an annealing process on the first polysilicon layer; and, after the annealing process, forming a second polysilicon layer in the region of the trench not filled by the first polysilicon layer. This method effectively reduces voids in the first and second polysilicon layers filling the trench, thereby improving the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), include many conductive lines. When forming the conductive lines, it is usually necessary to fill a polysilicon layer in a trench.

[0003] However, due to limitations in process conditions or because the aspect ratio of the trench is too large, large pores are likely to exist in the polysilicon layer filled in the trench, affecting the electrical performance of the conductive line. Summary of the Invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate having at least one trench; forming a first polysilicon layer in the trench, the first polysilicon layer covering the sidewalls and bottom of the trench and not completely filling the trench; performing an annealing process on the first polysilicon layer; and after performing the annealing process, forming a second polysilicon layer in the area of ​​the trench not filled by the first polysilicon layer.

[0005] In the above solution, before performing the annealing process, the ratio of the thickness of the first polysilicon layer to the depth of the trench is between 1:5 and 1:4.

[0006] In the above solution, before the annealing process is performed on the first polysilicon layer, the area of ​​the trench not filled by the first polysilicon layer forms a first opening, and the first opening has a cross-sectional shape that is narrow at the top and wide at the bottom.

[0007] In the above solution, after the first polysilicon layer is subjected to the annealing process, the area of ​​the trench not filled by the first polysilicon layer forms a second opening, and the second opening has a cross-sectional shape that is wider at the top and narrower at the bottom.

[0008] In the above solution, the depth of the second opening is smaller than the depth of the first opening.

[0009] In the above solution, the temperature range of the annealing process is between 500° C. and 700° C., the pressure range of the annealing process is between 10 Torr and 100 Torr, and the time range of the annealing process is between 1 hour and 2 hours.

[0010] In the above solution, the following steps are completed in the same process: the step of forming the first polysilicon layer, the step of performing the annealing process, and the step of forming the second polysilicon layer.

[0011] In the above solution, the device for completing the same process includes a furnace tube.

[0012] In the above solution, the first polysilicon layer and / or the second polysilicon layer includes doped polysilicon.

[0013] In the above solution, the doped polysilicon includes at least one of boron-doped polysilicon, phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0014] In the above solution, before forming the first polysilicon layer in the trench, the method further includes: depositing an insulating layer on the sidewall of the trench.

[0015] In the above solution, the first polysilicon layer includes a first sublayer and a second sublayer; forming the first polysilicon layer in the trench includes:

[0016] forming the first sub-layer in the trench, wherein the first sub-layer covers the sidewalls and the bottom of the trench;

[0017] The second sub-layer is formed on the first sub-layer.

[0018] In the above solution, the deposition temperature of the first polysilicon layer and / or the second polysilicon layer is between 350° C. and 700° C., and the deposition pressure is between 0.2 Torr and 4 Torr.

[0019] In the above solution, after forming the second polysilicon layer, the method further includes: performing an annealing process on the second polysilicon layer.

[0020] The present disclosure also provides a semiconductor device, comprising:

[0021] a substrate having at least one trench therein;

[0022] a first polysilicon layer covering the sidewalls and bottom of the trench; a second opening is formed above the first polysilicon layer, and the second opening has a cross-sectional shape that is wider at the top and narrower at the bottom;

[0023] The second polysilicon layer is located in the second opening.

[0024] In the above solution, the substrate includes a base material and a plurality of discrete device layers formed on the base material, and the grooves are formed between adjacent device layers.

[0025] In the above solution, the first polysilicon layer includes a first sublayer and a second sublayer located on the first sublayer, and the first sublayer is a seed layer of the second sublayer.

[0026] In the above solution, the semiconductor device further includes: an insulating layer, wherein the insulating layer is located between the first polysilicon layer and the sidewall of the trench.

[0027] The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device, wherein the method includes: providing a substrate having at least one trench; forming a first polysilicon layer in the trench, wherein the first polysilicon layer covers the sidewalls and bottom of the trench and does not completely fill the trench; performing an annealing process on the first polysilicon layer; and after performing the annealing process, forming a second polysilicon layer in the area of ​​the trench not filled by the first polysilicon layer. After the first polysilicon layer is formed in the trench, an annealing process is performed, which can significantly reduce the lattice defects of the first polysilicon layer, flatten the first polysilicon layer, and improve the filling capacity of the second polysilicon layer. Therefore, the present disclosure can effectively reduce or even eliminate the pores in the first polysilicon layer and the second polysilicon layer that are finally filled in the trench, thereby improving the electrical performance of the semiconductor device.

[0028] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims, or similar descriptions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 is a schematic structural diagram of an exemplary semiconductor device;

[0031] Figure 2 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0032] Figures 3 to 8 A process flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In semiconductor devices such as DRAM, the quality of the conductive lines will affect the electrical performance of the final device. Figure 1 is a schematic structural diagram of an exemplary semiconductor device, such as Figure 1 As shown, the semiconductor device includes: a substrate 10; a plurality of trenches TH1 are formed in the substrate 10, and the plurality of trenches TH1 are filled with a polysilicon layer 12.

[0040] The polysilicon layer 12 is formed in the trench TH1 by conventional deposition. It can be seen that there are pores 13 in the polysilicon layer 12. The presence of the pores 13 increases the resistance of the polysilicon layer and affects the electrical performance of the conductive line formed subsequently.

[0041] Based on this, the following technical solutions are proposed in the embodiments of the present disclosure:

[0042] The present disclosure provides a method for manufacturing a semiconductor device, such as Figure 2 As shown, the method includes the following steps:

[0043] Step 210: providing a substrate, wherein the substrate has at least one trench;

[0044] Step 220: forming a first polysilicon layer in the trench, wherein the first polysilicon layer covers the sidewalls and the bottom of the trench but does not completely fill the trench;

[0045] Step 230: performing an annealing process on the first polysilicon layer;

[0046] Step 240 : After performing the annealing process, forming a second polysilicon layer at the area of ​​the trench not filled by the first polysilicon layer.

[0047] After forming the first polysilicon layer within the trench, the disclosed embodiment performs an annealing process, significantly reducing lattice defects in the first polysilicon layer, flattening the first polysilicon layer, and improving the filling capacity of the second polysilicon layer. Therefore, the disclosed embodiment can effectively reduce or even eliminate voids in the first and second polysilicon layers ultimately filling the trench, improving the electrical performance of the semiconductor device.

[0048] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0049] Figures 3 to 8 A process flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0050] First, if Figure 3 As shown, step 210 is performed to provide a substrate 20 , wherein the substrate 20 has at least one trench TH2 .

[0051] The trench TH2 may be formed in the substrate 20 by using a dry etching process or a wet etching process.

[0052] In some specific embodiments, the substrate 20 includes a base material 201 and a plurality of discrete device layers 202 formed on the base material 201, and the trench TH2 is formed between adjacent device layers 202. Specifically, the base material 201 can be a semiconductor material, such as silicon. The device layer 202 can be formed of a single layer of material or multiple layers of material; the device layer 202 can include a conductive layer or an insulating layer; the device layer 202 can be retained in the final semiconductor device or removed during the semiconductor device manufacturing process. In short, the embodiments of the present disclosure do not limit the material, number of layers, and use of the device layer 202.

[0053] According to some embodiments, Figure 4 As shown, a first polysilicon layer 21 is formed in the trench TH2 (see Figure 6 ), the method further includes: depositing an insulating layer 23 on the sidewalls of the trench TH2. The insulating layer 23 is used to isolate the device layer 202 from the first polysilicon layer 21. The material of the insulating layer 23 may include, but is not limited to, oxides, nitrides, and oxynitrides, such as silicon oxide, silicon nitride, and silicon oxynitride.

[0054] Then, if Figure 5 、 Figure 6As shown, step 220 is performed to form a first polysilicon layer 21 in the trench TH2 , wherein the first polysilicon layer 21 covers the sidewalls and the bottom of the trench TH2 but does not completely fill the trench TH2 .

[0055] According to some embodiments, the first polysilicon layer 21 may include a first sub-layer 211 and a second sub-layer 212. The first polysilicon layer 21 is formed in the trench TH2, including:

[0056] The first sub-layer 211 is formed in the trench TH2, and the first sub-layer 211 covers the sidewalls and the bottom of the trench TH2. Figure 5 As shown;

[0057] The second sub-layer 212 is formed on the first sub-layer 211, as shown in FIG. Figure 6 shown.

[0058] The first sub-layer 211 and the second sub-layer 212 are made of the same material, both being polysilicon layers. The first sub-layer 211 is a seed layer, and forms a plurality of "nuclear centers" on the sidewalls and bottom of the trench TH2. These "nuclear centers" prevent abnormal growth of grains in the subsequently deposited second sub-layer 212, reduce the lattice mismatch between the second sub-layer 212 and the trench TH2, and improve the uniformity and growth quality of the second sub-layer 212.

[0059] The first polysilicon layer 21 may be a doped polysilicon layer, for example, at least one of boron-doped polysilicon, phosphorus-doped polysilicon, or arsenic-doped polysilicon.

[0060] The first polysilicon layer 21 may be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include but are not limited to chemical vapor deposition (CVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, or a combination thereof.

[0061] In an exemplary embodiment, the first polysilicon layer 21 is formed by a low-pressure chemical vapor deposition process (LPCVD). Specifically, the deposition temperature of the first polysilicon layer 21 is between 350° C. and 700° C., and the deposition pressure is between 0.2 Torr and 4 Torr. The gas used to form the first polysilicon layer 21 may include, but is not limited to, silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), etc. In an actual process, two or more gases from silane (SiH4), disilane (Si2H6), and dichlorosilane (SiH2Cl2) may be selected and mixed or used alternately. When the first polysilicon layer 21 is a doped polysilicon layer, during preparation, one or more gases selected from phosphine (PH3), boron trichloride (BCl3), borane (B2H6), and arsine (AsH4) are introduced into the chamber to form a doped polysilicon layer.

[0062] In an actual process, the ratio of the thickness of the first polysilicon layer 21 to the depth of the trench TH2 is between 1:5 and 1:4. If the first polysilicon layer 21 is too thick or too thin, it will have an adverse effect on the subsequently grown second polysilicon layer 22.

[0063] Continue to refer Figure 6 Before the first polysilicon layer 21 is subjected to the subsequent annealing process, the area of ​​the trench TH2 not filled by the first polysilicon layer 21 forms a first opening H1. The depth of the first opening H1 is h1, and the first opening H1 has a cross-sectional shape that is narrow at the top and wide at the bottom. It can be understood that the first opening H1 with a cross-sectional shape that is narrow at the top and wide at the bottom is not conducive to the subsequent second polysilicon layer 22 (see Figure 8 ) deposition.

[0064] Next, if Figure 7 As shown, step 230 is performed to perform an annealing process on the first polysilicon layer 21. The annealing process can discharge the semi-reactants or impurities in the first polysilicon layer 21, significantly reduce the lattice defects of the first polysilicon layer 21, and make the first polysilicon layer 21 more flat, which is beneficial to the subsequent second polysilicon layer 22 (see Figure 8 Here, the semi-reactants or impurities include but are not limited to hydrogen, hydrogen chloride, etc.

[0065] After performing the annealing process, Figure 7 As shown, the area of ​​the trench TH2 not filled by the first polysilicon layer 21 forms a second opening H2, the second opening H2 has a depth h2, and the second opening H2 has a cross-sectional shape that is wide at the top and narrow at the bottom. Figure 6It can be seen that the depth h2 of the second opening H2 is less than the depth h1 of the first opening H1, that is, h2

[0066] The annealing process is carried out in an annealing furnace; specifically, the annealing furnace can be a furnace tube. In one embodiment of the present disclosure, the temperature range of the annealing process is between 500°C and 700°C, the pressure range is between 10 Torr and 100 Torr, and the time range is between 1 hour and 2 hours. Optionally, during the annealing process, nitrogen is introduced into the annealing furnace. Here, the nitrogen is used to stabilize the pressure in the process chamber so that the annealing process can be carried out within the set pressure range.

[0067] Finally, if Figure 8 As shown, step 240 is performed: after performing the annealing process, a second polysilicon layer 22 is formed in the area of ​​the trench TH2 that is not filled by the first polysilicon layer 21. That is, the second polysilicon layer 22 is formed in the second opening H2.

[0068] At this point, the trench TH2 is filled with the first polysilicon layer 21 and the second polysilicon layer 22 . The porosity of the first polysilicon layer 21 and the second polysilicon layer 22 is much smaller than the porosity of the polysilicon layer 12 in the related art.

[0069] The second polysilicon layer 22 may be a doped polysilicon layer, such as at least one of boron-doped polysilicon, phosphorus-doped polysilicon, or arsenic-doped polysilicon. The doping element in the second polysilicon layer 22 may be the same as or different from the doping element in the first polysilicon layer 21.

[0070] The second polysilicon layer 22 may be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include but are not limited to chemical vapor deposition (CVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, or a combination thereof.

[0071] ​In a specific embodiment, the second polysilicon layer 22 is formed by a low-pressure chemical vapor deposition process (LPCVD). Specifically, the deposition temperature of the second polysilicon layer 22 is between 350° C. and 700° C., and the deposition pressure is between 0.2 Torr and 4 Torr. The gas used to form the second polysilicon layer 22 may include, but is not limited to, silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), etc. In an actual process, two or more gases selected from silane (SiH4), disilane (Si2H6), and dichlorosilane (SiH2Cl2) may be mixed or used alternately. When the second polysilicon layer 22 is a doped polysilicon layer, during preparation, one or more gases selected from phosphine (PH3), boron trichloride (BCl3), borane (B2H6), and arsine (AsH4) are introduced into the chamber to form the doped polysilicon layer.

[0072] In one embodiment of the present disclosure, the steps of forming the first polysilicon layer 21, performing the annealing process, and forming the second polysilicon layer 22 are completed in the same process. In this way, the surface of the first polysilicon layer 21 is prevented from being oxidized and forming an oxide layer during the transition between different processes, which would increase the resistance of the first polysilicon layer 21 and the second polysilicon layer 22.

[0073] Specifically, the apparatus for performing the same process may include, but is not limited to, a furnace tube. Specifically, the following steps can be performed sequentially within the furnace tube: forming a first polysilicon layer, performing an annealing process, and forming a second polysilicon layer. During this process, the substrate with the first polysilicon layer formed thereon does not need to be removed from the furnace tube, and the first polysilicon layer will not be oxidized.

[0074] In one embodiment, after forming the second polysilicon layer, the method further includes: performing an annealing process on the second polysilicon layer. The annealing process is primarily intended to repair defects in the second polysilicon layer, further reduce porosity in the second polysilicon layer, and improve film quality of the second polysilicon layer.

[0075] The process conditions for annealing the second polysilicon layer may be the same as or different from the process conditions for annealing the first polysilicon layer, and will not be described in detail here.

[0076] The first polysilicon layer and the second polysilicon layer in the embodiment of the present disclosure can constitute conductive lines, such as bit lines and word lines in DRAM devices; but are not limited to this, and can also constitute other conductive structures, such as conductive plugs, such as bit line plugs in DRAM devices.

[0077] The semiconductor device manufacturing method provided by the embodiments of the present disclosure forms a first polysilicon layer within a trench, performs an annealing process, and then deposits a second polysilicon layer on the first polysilicon layer. The polysilicon layer formed by filling the trench using this method can significantly reduce the porosity within the polysilicon layer, improve the film quality of the polysilicon layer, and thus enhance the electrical performance of the polysilicon layer.

[0078] Furthermore, in one embodiment of the present disclosure, the steps of forming the first polysilicon layer 21, performing an annealing process, and forming the second polysilicon layer 22 are all completed in the same process. This results in little or no oxide layer being formed between the first polysilicon layer 21 and the second polysilicon layer 22 ultimately formed within the trench. This helps reduce the resistance of the ultimately formed polysilicon layer, resulting in a semiconductor device with excellent electrical properties.

[0079] The present disclosure also provides a semiconductor device, such as Figure 8 As shown, the semiconductor device includes: a substrate 20 having at least one trench TH2 therein; a first polysilicon layer 21 covering the sidewalls and bottom of the trench TH2, with a second opening H2 formed above the first polysilicon layer 21; and a second polysilicon layer 22 formed within the second opening H2. The second opening H2 has a cross-sectional shape that is wider at the top and narrower at the bottom. The second opening H2 has a cross-sectional shape that is wider at the top and narrower at the bottom because the first polysilicon layer 21 is grown to cover the sidewalls and bottom of the trench TH2 and is annealed after formation.

[0080] In some embodiments, the substrate 20 includes a base material 201 and a plurality of discrete device layers 202 formed on the base material, and the trench TH2 is formed between adjacent device layers 202. Specifically, the base material 201 can be a semiconductor material, such as silicon. The device layer 202 can be formed of a single layer of material or a plurality of layers of material; the device layer 202 can include a conductive layer or an insulating layer; the device layer 202 can be retained in the final semiconductor device or removed during the preparation process of the semiconductor device. In summary, the embodiments of the present disclosure do not limit the material, number of layers, and use of the device layer 202.

[0081] In some embodiments, an insulating layer 23 is further provided between the sidewalls of the trench TH2 and the first polysilicon layer 21. The insulating layer 23 is used to isolate the device layer 202 from the first polysilicon layer 21. The material of the insulating layer 23 may include, but is not limited to, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and the like.

[0082] Optionally, the first polysilicon layer 21 may include a first sublayer 211 and a second sublayer 212, wherein the first sublayer 211 is a seed layer for the second sublayer 212. Here, the first sublayer 211 is a seed layer, and the first sublayer 211 forms a plurality of "core centers" on the sidewalls and bottom of the trench TH2. The "core centers" can prevent abnormal growth of grains in the subsequently deposited second sublayer 212, reduce the lattice mismatch between the second sublayer 212 and the trench TH2, and improve the uniformity and growth quality of the second sublayer 212.

[0083] The first polysilicon layer 21 and / or the second polysilicon layer 22 may be a doped polysilicon layer, for example, at least one of boron-doped polysilicon, phosphorus-doped polysilicon, or arsenic-doped polysilicon.

[0084] The first polysilicon layer 21 and / or the second polysilicon layer 22 may be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include but are not limited to chemical vapor deposition (CVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, or a combination thereof.

[0085] In a specific embodiment, a low pressure chemical vapor deposition process (LPCVD) is used to form the first polysilicon layer 21 and / or the second polysilicon layer 22. Specifically, the deposition temperature of the first polysilicon layer 21 and / or the second polysilicon layer 22 is between 350°C and 700°C, and the deposition pressure is between 0.2 Torr and 4 Torr. The gas used to form the first polysilicon layer 21 and / or the second polysilicon layer 22 may include but is not limited to silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), etc. In the actual process, two or more gases can be selected from silane (SiH4), disilane (Si2H6), and dichlorosilane (SiH2Cl2) and mixed or used alternately. When the first polysilicon layer 21 and / or the second polysilicon layer 22 are doped polysilicon layers, during preparation, one or more gases selected from phosphine (PH3), boron trichloride (BCl3), borane (B2H6), and arsine (AsH4) are introduced into the chamber to form the doped polysilicon layer.

[0086] It is understood that performing an annealing process on the first polysilicon layer 21 can significantly reduce lattice defects in the first polysilicon layer 21, improve the flatness of the first polysilicon layer 21, and facilitate improving the filling capacity of the subsequently formed second polysilicon layer 22, thereby greatly reducing the possibility of pores in the polysilicon layer. In addition, during the annealing process, the annealing process also serves to discharge semi-reactants or impurities generated during the formation of the first polysilicon layer 21 from the first polysilicon layer 21, thereby improving the film quality of the formed first polysilicon layer 21.

[0087] The annealing process is carried out in an annealing furnace; specifically, the annealing furnace can be a furnace tube. In one embodiment of the present disclosure, the temperature range of the annealing process is between 500°C and 700°C, the pressure range is between 10 Torr and 100 Torr, and the time range is between 1 hour and 2 hours. Optionally, during the annealing process, nitrogen is introduced into the annealing furnace. Here, the nitrogen is used to stabilize the pressure in the process chamber so that the annealing process can be carried out within the set pressure range.

[0088] The first polysilicon layer and the second polysilicon layer in the embodiment of the present disclosure can constitute conductive lines, such as bit lines and word lines in DRAM devices; but are not limited to this, and can also constitute other conductive structures, such as conductive plugs, such as bit line plugs in DRAM devices.

[0089] In the semiconductor device of the embodiment of the present disclosure, the polysilicon layer formed has almost no pores, which reduces the resistance of the polysilicon layer filled in the trench TH2 and helps to form a semiconductor device with good electrical quality. It should be understood that the formation of the semiconductor device can be formed using a semiconductor device manufacturing method provided in each of the above embodiments.

[0090] It should be noted that the semiconductor device fabrication methods provided in the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and are not limited here. The embodiments of the semiconductor device fabrication methods provided in the present disclosure and the embodiments of the semiconductor device are based on the same concept; the technical features of the technical solutions described in the embodiments can be combined arbitrarily unless they conflict.

[0091] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: providing a substrate having at least one trench; forming a first polysilicon layer in the trench, wherein the first polysilicon layer covers the sidewalls and the bottom of the trench but does not completely fill the trench; performing an annealing process on the first polysilicon layer; After performing the annealing process, forming a second polysilicon layer at an area of ​​the trench not filled by the first polysilicon layer; Before the first polysilicon layer is subjected to the annealing process, the area of ​​the trench not filled by the first polysilicon layer constitutes a first opening, and the first opening has a cross-sectional shape that is narrow at the top and wide at the bottom; after the first polysilicon layer is subjected to the annealing process, the area of ​​the trench not filled by the first polysilicon layer constitutes a second opening, and the second opening has a cross-sectional shape that is wide at the top and narrow at the bottom.

2. The method according to claim 1, characterized in that Before the annealing process is performed, a ratio of the thickness of the first polysilicon layer to the depth of the trench is between 1:5 and 1:

4.

3. The method according to claim 1, characterized in that A depth of the second opening is smaller than a depth of the first opening.

4. The method according to claim 1, wherein The temperature range of the annealing process is between 500° C. and 700° C., the pressure range of the annealing process is between 10 Torr and 100 Torr, and the time range of the annealing process is between 1 hour and 2 hours.

5. The method according to claim 1, wherein The following steps are completed in the same process: the step of forming the first polysilicon layer, the step of performing the annealing process, and the step of forming the second polysilicon layer.

6. The method according to claim 5, characterized in that The device for completing the same process includes a furnace tube.

7. The method according to claim 1, characterized in that The first polysilicon layer and / or the second polysilicon layer include doped polysilicon.

8. The method according to claim 7, characterized in that The doped polysilicon includes at least one of boron-doped polysilicon, phosphorus-doped polysilicon or arsenic-doped polysilicon.

9. The method according to claim 1, characterized in that Before forming the first polysilicon layer in the trench, the method further includes: depositing an insulating layer on the sidewall of the trench.

10. The method according to claim 1, characterized in that The first polysilicon layer includes a first sublayer and a second sublayer; forming the first polysilicon layer in the trench includes: forming the first sub-layer in the trench, wherein the first sub-layer covers the sidewalls and the bottom of the trench; The second sub-layer is formed on the first sub-layer.

11. The method according to claim 1, wherein The deposition temperature of the first polysilicon layer and / or the second polysilicon layer is between 350° C. and 700° C., and the deposition pressure is between 0.2 Torr and 4 Torr.

12. The method according to claim 1, characterized in that After forming the second polysilicon layer, the method further includes performing an annealing process on the second polysilicon layer.

13. A semiconductor device manufactured by the method according to any one of claims 1 to 12, characterized in that: include: a substrate having at least one trench therein; a first polysilicon layer covering the sidewalls and bottom of the trench; A second opening is formed above the first polysilicon layer, and the second opening has a cross-sectional shape that is wide at the top and narrow at the bottom; The second polysilicon layer is located in the second opening.

14. The semiconductor device according to claim 13, wherein: The substrate includes a base material and a plurality of discrete device layers formed on the base material, and the trench is formed between adjacent device layers.

15. The semiconductor device according to claim 13, wherein The first polysilicon layer includes a first sublayer and a second sublayer located on the first sublayer, and the first sublayer is a seed layer of the second sublayer.

16. The semiconductor device according to claim 13, wherein The semiconductor device further includes an insulating layer located between the first polysilicon layer and a sidewall of the trench.

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