A semiconductor device and its manufacturing method

Abstract

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology. It simplifies the manufacturing process of the source and drain regions of the lower gate-around transistor in a CFET device, thereby reducing the integration difficulty of the CFET device. The semiconductor device includes: a first semiconductor substrate, a junctionless gate-around transistor, and an enhancement-mode junction-around transistor. The junctionless gate-around transistor is formed on the first semiconductor substrate. The enhancement-mode junction-around transistor is formed above the junctionless gate-around transistor and spaced apart from it. The enhancement-mode junction-around transistor has the opposite conductivity type to the junctionless gate-around transistor. The manufacturing method of the semiconductor device is used to manufacture the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Complementary field effect transistors (CFETs) consist of vertically stacked NMOS (N-Metal-Oxide-Semiconductor) and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0003] However, the manufacturing process of existing CFET devices is quite complicated, which makes the integration of CFET devices more difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which simplifies the manufacturing process of the source and drain regions of the lower ring gate transistor in a CFET device, thereby reducing the integration difficulty of the CFET device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: a first semiconductor substrate, a junctionless gate ring transistor, and an enhancement-junction gate ring transistor.

[0006] The aforementioned junctionless gate-around transistor is formed on a first semiconductor substrate. An enhancement-mode junction-around transistor is formed above and spaced apart from the junctionless gate-around transistor. The enhancement-mode junction-around transistor has the opposite conductivity type to the junctionless gate-around transistor.

[0007] Compared to existing technologies, in the semiconductor device provided by this invention, the enhancement-mode junction-gate-around (JGROUP) transistor is located above the junctionless gate-around (GROUP) transistor. Furthermore, the JGROUP transistor and the GROUP transistor have different conductivity types; therefore, the JGROUP transistor and the GROUP transistor together form a CFET device to improve the integration density of the CMOS device. Additionally, the transistor located below in the semiconductor device is a GROUP transistor. Therefore, since there is no PN junction in a junctionless gate-around transistor (GMT-AOT), and the source, drain, and channel regions contain the same type of impurity doping, in the actual manufacturing process, when forming the first semiconductor layer for manufacturing the GMT-AOT on the first semiconductor substrate, at least a portion of this first semiconductor layer can be doped to form the source, drain, and channel regions of the GMT-AOT. This solves the problem of high process complexity in existing technologies, which require multiple epitaxial and etching processes to form the source and drain regions of the N-type and P-type GMT-AOT transistors in a CFET device after forming the fin structure. This simplifies the manufacturing process of CFET devices, reduces the integration difficulty, and improves the manufacturing efficiency. Furthermore, the transistor located at the top of the semiconductor device is an enhancement-mode junction-around-gate transistor (AMG-AOT). Therefore, since the electrical performance of enhancement-mode junction-mode gate-around transistors (JMTs) is less affected by doping process fluctuations compared to junctionless gate-around transistors (JMTs), and the on-state current of JMTs is relatively large, it is beneficial to improve the electrical characteristics of CFET devices when the upper transistor is an JMT.

[0008] This invention provides a method for manufacturing a semiconductor device, the method comprising:

[0009] Provide a first semiconductor substrate.

[0010] A junctionless gate-around transistor is formed on a first semiconductor substrate; and an enhancement-type junction-around transistor is formed above the junctionless gate-around transistor and spaced apart from it. The enhancement-type junction-around transistor has the opposite conductivity type to the junctionless gate-around transistor.

[0011] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention can be referred to the analysis of the beneficial effects of semiconductor devices described above, and will not be repeated here. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0013] Figure 1Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 1 and structural diagram Figure 2 ;

[0014] Figure 2 Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 3 and structural diagram Figure 4 ;

[0015] Figure 3 Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 5 and structural diagram Figure 6 ;

[0016] Figure 4 Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 7 and structural diagram Figure 8 ;

[0017] Figure 5 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 9 ;

[0018] Figure 6 Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 10 and structural diagram Figure 10 one;

[0019] Figure 7 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 10 two;

[0020] Figure 8 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 10 three;

[0021] Figure 9 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 10 Four;

[0022] Figure 10 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 10 five;

[0023] Figure 11Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 10 Six Harmony Structure Diagram Figure 10 seven;

[0024] Figure 12 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 10 eight;

[0025] Figure 13 Parts (1) and (2) are schematic diagrams of the manufacturing process of a semiconductor device provided in an embodiment of the present invention. Figure 10 Nine Harmony Structure Diagram Figure 2 ten;

[0026] Figure 14 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 eleven;

[0027] Figure 15 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 twelve;

[0028] Figure 16 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 Thirteen;

[0029] Figure 17 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 fourteen;

[0030] Figure 18 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 fifteen;

[0031] Figure 19 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 sixteen;

[0032] Figure 20 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 Seventeen;

[0033] Figure 21 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 eighteen;

[0034] Figure 22The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 2 nineteen;

[0035] Figure 23 The image below is a structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 3 ten;

[0036] Figure 24 The figure below is a flowchart of a semiconductor device manufacturing method provided by an embodiment of the present invention.

[0037] Reference numerals: 1 is the first semiconductor substrate, 2 is the first strain buffer layer, 3 is the first semiconductor layer, 4 is the third semiconductor layer, 5 is the first bonding sublayer, 6 is the second semiconductor substrate, 7 is the semiconductor substrate, 8 is the second strain buffer layer, 9 is the second semiconductor layer, 10 is the fourth semiconductor layer, 11 is the second bonding sublayer, 12 is the bonding layer, 13 is the bonding structure, 14 is the first mask layer, 15 is the first fin, 16 is the second mask layer, 17 is the second fin, 18 is the fin structure, 19 is the first region, 20 is the second region, 21 is the third region, 22 is the shallow trench isolation structure, 23 is the sacrificial gate, 24 is the gate sidewall, 25 is the source region, 26 is the drain region, 27 is the dielectric layer, 28 is the third mask layer, 29 is the channel region, 30 is the first material part, 31 is the second material part, 32 is the gate stack structure, 33 is the junctionless gate-around transistor, and 34 is the enhancement-mode junction gate-around transistor. Detailed Implementation

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0043] Complementary field effect transistors (CFETs) consist of vertically stacked NMOS (N-Metal-Oxide-Semiconductor) and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0044] However, the existing manufacturing process for CFET devices is relatively cumbersome and makes it difficult to integrate N-type and P-type gate-around transistors within a CFET device. Specifically, the following description uses an example of a P-type gate-around transistor located above an N-type gate-around transistor to illustrate the process of manufacturing a CFET device using existing methods: First, a fin structure is formed on a semiconductor substrate. This fin structure includes at least two stacked layers. Each stacked layer includes a sacrificial layer and a channel layer located on the sacrificial layer. Next, a sacrificial gate and sidewalls are formed across the fin structure. Using the sacrificial gate and sidewalls as a mask, the fin structure is selectively etched to remove the portions of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for manufacturing the source and drain regions of the N-type gate-around transistor is formed on the semiconductor substrate. At this point, the remaining portions of the sacrificial layer and channel layer corresponding to the N-type and P-type gate-around transistors are exposed after etching. Both can serve as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining portion after etching the sacrificial layer and channel layer corresponding to the N-type gate-around transistor, but also on both sides of the remaining portion after etching the sacrificial layer and channel layer corresponding to the P-type gate-around transistor. Next, the first semiconductor material located on both sides of the remaining portion after etching the sacrificial layer and channel layer corresponding to the P-type transistor needs to be removed. The remaining portion of the first semiconductor material forms the source and drain regions included in the N-type gate-around transistor. Then, an epitaxial isolation layer is formed covering the source and drain regions included in the N-type gate-around transistor, facing away from the semiconductor substrate surface. Next, the source and drain regions of the P-type gate-around transistor are formed on the epitaxial isolation layer using an epitaxial growth process. A dielectric layer is formed covering the formed structure, with its top flush with the top of the sacrificial gate. Finally, the portion of each sacrificial layer corresponding to the gate formation region is removed to obtain the channel regions included in the N-type and P-type gate-around transistors. A gate stack structure surrounding the channel region is formed using processes such as atomic layer deposition to obtain a CFET device.

[0045] As can be seen from the above manufacturing process, existing manufacturing methods require multiple epitaxial and etching processes to form the source and drain regions of N-type and P-type gate-around transistors, resulting in high process complexity and integration difficulty. Furthermore, this also makes the manufacturing process of CFET devices more cumbersome, hindering their integration.

[0046] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, an enhancement-mode junction-gate-around (JGROUP) transistor and a junctionless gate-around (GROUP) transistor constitute a CFET device. Furthermore, the lower transistor in the semiconductor device is a junctionless GROUP transistor, which simplifies the manufacturing process of the source and drain regions included in the lower GROUP transistor of the CFET device and improves the manufacturing efficiency of the CFET device.

[0047] like Figure 20 As shown, an embodiment of the present invention provides a semiconductor device, which includes: a first semiconductor substrate 1, a junctionless gate ring transistor 33, and an enhancement-mode gate ring transistor 34.

[0048] like Figure 20 As shown, the junctionless gate ring transistor 33 is formed on the first semiconductor substrate 1. An enhancement-mode junction gate ring transistor 34 is formed above and spaced apart from the junctionless gate ring transistor 33. The enhancement-mode junction gate ring transistor 34 has the opposite conductivity type to the junctionless gate ring transistor 33.

[0049] Specifically, the aforementioned first semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrate on which no other structures are formed. Alternatively, the first semiconductor substrate can also be a semiconductor substrate on which some structures are formed. Specifically, the specific structure of the first semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, if the semiconductor device provided in this embodiment of the invention is applied to a second or higher layer semiconductor device included in an integrated circuit, the first semiconductor substrate can at least include a semiconductor substrate, a first layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first layer device structure. In this case, the materials of each part of the first semiconductor substrate can be set according to actual needs, as long as they can be applied to the semiconductor device provided in this embodiment of the invention.

[0050] For the aforementioned junctionless gate-around transistor and enhancement-mode junction-around transistor, in terms of conductivity type, the junctionless gate-around transistor can be N-type, while the enhancement-mode junction-around transistor is P-type. Alternatively, the junctionless gate-around transistor can also be P-type, in which case the enhancement-mode junction-around transistor is N-type.

[0051] It is understandable that, such as Figure 20 As shown, in the semiconductor device provided in this embodiment of the invention, the enhancement-mode junction-gate-around transistor 34 is located above the junctionless gate-around transistor 33. Furthermore, as mentioned above, the enhancement-mode junction-gate-around transistor 34 and the junctionless gate-around transistor 33 have different conductivity types. Therefore, the enhancement-mode junction-gate-around transistor 34 and the junctionless gate-around transistor 33 together form a CFET device to improve the integration density of the CMOS device.

[0052] From a structural perspective, such as Figure 20As shown, the transistor located at the bottom in the semiconductor device is a junctionless gate-ring transistor 33. Based on this, the junctionless gate-ring transistor 33 has no PN junction, and its source region 25, drain region 26, and channel region 29 have the same impurity doping type (for example, in the case where the conductivity type of the junctionless gate-ring transistor is N-type, the source region, drain region, and channel region of the junctionless gate-ring transistor are all N-type active regions doped with N-type impurities such as phosphorus). Therefore, in the actual manufacturing process, such as... Figure 1 and Figure 2 As shown in parts (1) and (2), when forming the first semiconductor layer 3 for manufacturing a junctionless gate ring transistor on the first semiconductor substrate 1, at least a portion of the first semiconductor layer 3 can be doped to form the source region, drain region, and channel region of the junctionless gate ring transistor. This solves the problem in the prior art that the source and drain regions of the N-type gate ring transistor and the P-type gate ring transistor in the CFET device need to be formed after the fin structure is formed through multiple epitaxial and etching processes, which leads to high process complexity. This simplifies the manufacturing process of the CFET device, reduces the integration difficulty of the CFET device, and also improves the manufacturing efficiency of the CFET device.

[0053] Specifically, the junctionless gate-around transistor may consist of only one active layer (along its length, the active layer includes a source region, a drain region, and a channel region between the source and drain regions). Alternatively, as... Figure 20 As shown, the junctionless gate ring transistor 33 may also include at least two active layers stacked along the thickness direction of the first semiconductor substrate 1. Adjacent active layers are spaced apart. Each active layer has a gap with the first semiconductor substrate 1. The height of this gap can be set according to the thickness of the gate stack structure 32 included in the junctionless gate ring transistor 33. When the junctionless gate ring transistor 33 includes at least two active layers, the material of each active layer can be the same or different. In practical applications, because different semiconductor materials have different conductivity and carrier mobility, when the material of each active layer is different, the conduction characteristics of the channel region 29 of each active layer can be adjusted by adjusting the material of each active layer, which is beneficial to improving the driving performance of the junctionless gate ring transistor 33.

[0054] Furthermore, in junctionless gate-around transistors (JGOT) comprising at least two active layers, the thickness of each active layer can be the same or different. In practical applications, the on-resistance of the channel region in the bottom active layer of a JGOT is greater than the on-resistance of the channel region in the top active layer. Based on this, such as... Figure 22As shown, the thickness of the bottom active layer in the junctionless gate ring transistor 33 can be set to be greater than the thickness of the top active layer to increase the conductive area of ​​the channel region 29 in the bottom active layer. This is beneficial to improve the conduction uniformity of the channel region 29 in each active layer of the junctionless gate ring transistor 33, thereby improving the electrical performance of the junctionless gate ring transistor 33.

[0055] As for enhancement-mode junction-gate-around transistors, such as Figure 20 As shown, the upper transistor in the semiconductor device is an enhancement-mode junction-gate-around transistor 34. Therefore, compared to the non-junction-gate-around transistor 33, the electrical performance of the enhancement-mode junction-gate-around transistor is less affected by fluctuations in the doping process, and the on-state current of the enhancement-mode junction-gate-around transistor is relatively large. Thus, having the upper transistor as the enhancement-mode junction-gate-around transistor 34 is beneficial for improving the electrical characteristics of the CFET device.

[0056] Specifically, the channel region in this enhanced junction-gate-around transistor can consist of only one layer of nanowire or sheet. Or, as... Figure 20 As shown, the channel region 29 in the enhancement-mode junction-gate-around transistor 34 may also include at least two layers of nanowires or sheets stacked along the thickness direction of the first semiconductor substrate 1, with adjacent nanowires or sheets spaced apart. Furthermore, each nanowire or sheet layer has a gap with the first semiconductor substrate 1. The height of this gap can be set according to the thickness of the gate stack structure 32 included in the enhancement-mode junction-gate-around transistor 34. Wherein, when the channel region 29 in the enhancement-mode junction-gate-around transistor 34 includes two layers of nanowires or sheets, the material of each nanowire or sheet layer can be the same or different. The thickness of each nanowire or sheet layer can be the same or different. Specifically, the beneficial effects of different materials for each nanowire or sheet layer and different thicknesses for each nanowire or sheet layer can be referred to the previously described analysis of the beneficial effects of different materials for each active layer and different thicknesses for each active layer, and will not be repeated here.

[0057] In practical applications, the channel region of the junctionless gate ring transistor and the channel region of the enhancement-mode junction ring gate transistor can be made of the same material. For example, the channel regions of both the junctionless gate ring transistor and the enhancement-mode junction ring gate transistor can be made of any semiconductor material such as silicon, silicon germanium, germanium, or group III-V compounds. Alternatively, as... Figure 21As shown, the materials of the channel region 29 in the junctionless gate ring transistor 33 and the channel region 29 in the enhancement-mode gate ring transistor 34 can also be different. For example, if the material of the channel region 29 in the junctionless gate ring transistor 33 is silicon, the material of the channel region 29 in the enhancement-mode gate ring transistor 34 can be germanium-silicon, germanium, or a group III-V compound, etc. In this case, the materials of the channel regions 29 in the junctionless gate ring transistor 33 and the enhancement-mode gate ring transistor 34 can be adjusted so that the threshold voltage and other electrical properties of the two transistors can meet the operating requirements of different application scenarios, thereby improving the applicability of the semiconductor device provided in the embodiments of the present invention in different application scenarios.

[0058] In addition, such as Figure 22 As shown, the thickness of the channel region 29 in the junctionless gate ring transistor 33 can be the same as or different from the thickness of the channel region 29 in the enhancement-mode gate ring transistor 34. When the thickness of the channel region 29 in the junctionless gate ring transistor 33 differs from that in the enhancement-mode gate ring transistor 34, the conduction characteristics of the channel region 29 in the junctionless gate ring transistor 33 located below the enhancement-mode gate ring transistor 34 can be improved by setting the thickness of the channel region 29 in the junctionless gate ring transistor 33 to be greater than that in the enhancement-mode gate ring transistor 34. This improves the electrical performance of the junctionless gate ring transistor 33.

[0059] Furthermore, the width of the channel region in the aforementioned junctionless gate-around transistor can be the same as or different from the width of the channel region in the enhancement-mode junction-around transistor. Specifically, when the width of the channel region in the junctionless gate-around transistor differs from the width of the channel region in the enhancement-mode junction-around transistor, such as... Figure 23 As shown, by setting the width of the channel region 29 included in the junctionless gate ring transistor 33 to be greater than the width of the channel region 29 included in the enhancement-type junction gate ring transistor 34, the conductive area of ​​the channel region 29 in the junctionless gate ring transistor 33 can be increased, thereby improving the conduction characteristics of the channel region 29 in the junctionless gate ring transistor 33 located below the enhancement-type junction gate ring transistor 34, which is beneficial to improving the electrical performance of the junctionless gate ring transistor 33.

[0060] Specifically, when the thickness of the channel region in a junctionless gate-around transistor (JGOT) differs from that in an enhancement-mode gate-around transistor (AMG), the difference in thickness can be set according to the actual application scenario, and is not specifically limited here. Similarly, when the width of the channel region in a JGOT differs from that in an AMGOT, the difference in width can also be set according to the actual application scenario, and is not specifically limited here.

[0061] like Figure 20 As shown, both the junctionless gate-around transistor 33 and the enhancement-mode gate-around transistor 34 further include a gate stack structure 32. The gate stack structure 32 surrounds the outer periphery of the corresponding channel region 29. Specifically, the gate stack structure 32 may include at least a gate dielectric layer surrounding the outer periphery of the channel region 29, and a gate electrode formed on the gate dielectric layer. The gate dielectric layer may be made of materials with high dielectric constants, such as HfO2, ZrO2, TiO2, or Al2O3. The gate electrode may be made of conductive materials such as TiN, TaN, or TiSiN.

[0062] In one example, such as Figure 19 As shown, the channel region 29 of the aforementioned enhancement-mode junction-to-gate-around transistor includes a first material portion 30 and a second material portion 31 surrounding the outer periphery of the first material portion 30. The material of the second material portion 31 is different from the material of the first material portion 30. The material of the first material portion 30 is the same as the material of the channel region included in the junctionless gate-to-gate-around transistor.

[0063] As mentioned above, different semiconductor materials have different conductivity and carrier mobility. Therefore, when the channel region of the enhancement-mode junction-gate-around (GNA) transistor includes a first material portion and a second material portion with different materials, the threshold voltage of the GNA transistor can be adjusted by changing the material type of the second material portion according to the requirements of different application scenarios, thereby improving the applicability of the GNA transistor in different application scenarios. Furthermore, since the material of the first material portion is the same as the material of the channel region of the junctionless gate-around transistor, and the material of the second material portion is different from the material of the first material portion, the material of the second material portion is different from the material of the channel region of the junctionless gate-around transistor. Based on this, when the channel region of the GNA transistor includes a first material portion and a second material portion, the semiconductor device provided by the embodiments of the present invention also provides a possible implementation scheme for the integration of CFET devices with heterogeneous channel materials. Moreover, the material of the first material portion is the same as the material of the channel region of the junctionless gate-around transistor. Based on this, when manufacturing junctionless gate ring transistors and enhancement-mode gate ring transistors, corresponding sacrificial layers of the same material can be used to form at least the gap between the channel region of the junctionless gate ring transistor and the first semiconductor substrate, and to form at least the gap between the channel region of the enhancement-mode gate ring transistor and the junctionless gate ring transistor. This eliminates the need for strict etching precision requirements due to the different materials of each sacrificial layer, and reduces the difficulty of selective etching when releasing the channel region.

[0064] Specifically, from a material perspective, the material of the second material section can be any semiconductor material different from that of the first material section. When germanium-silicon or high-mobility germanium materials are used to fabricate the channel region of a P-type transistor, the carrier mobility of the channel region can be improved, thereby enhancing the performance of the P-type transistor. However, when germanium-silicon or high-mobility germanium materials are used to fabricate the channel region of an N-type transistor, problems arise such as poor interface states, high source-drain contact resistance, low N-type impurity solid concentration, and rapid diffusion. Therefore, the types of the first and second material sections can be determined based on the conductivity type of junctionless gate-around transistors and enhancement-mode junction-around-around transistors, and are not specifically limited here.

[0065] For example, in the case where the conductivity type of the enhancement-mode junction-to-gate-around transistor (AMG-AOOT) is P-type, the material of the first material portion is silicon, and the material of the second material portion is a high-mobility channel material. This high-mobility channel material includes at least one of germanium-silicon, germanium, or a group III-V compound, to improve the carrier mobility of the AMG-AOOT and enhance its electrical performance.

[0066] For example, when the conductivity type of the enhancement-type junction-gate-around transistor is N-type, the material of the first material section is a high-mobility channel material, and the material of the second material section is silicon, so as to reduce the impact of the high-mobility channel material on the enhancement-type junction-gate-around transistor while ensuring that the junction-free gate-around transistor has a high carrier mobility.

[0067] Structurally, the width and thickness of the first material portion can be smaller than the width and thickness of the channel layer included in the junctionless gate-around transistor (JGOT). Based on this, in actual manufacturing, the gate stack structures of the JGOT and enhancement-mode JGOT transistors are formed on the outer periphery of their respective channel regions. Furthermore, the maximum area formed by the gate stack structure is the area released after removing the sacrificial gate and bonding layer, or the area released after removing the portion of the sacrificial gate, bonding layer, and corresponding sacrificial layer (third semiconductor layer and / or fourth semiconductor layer, etc.) located within the gate formation region. Therefore, when the width and thickness of the first material portion are smaller than the width and thickness of the channel layer included in the JGOT, the proportion of the second material portion in the aforementioned area can be reduced, or the second material portion can be prevented from occupying the aforementioned area, ensuring that the gate stack structure included in the enhancement-mode JGOT transistor has a relatively large formation space, facilitating the formation of the gate stack structure included in the enhancement-mode JGOT transistor.

[0068] Of course, the thickness and width of the first material portion can also be equal to the thickness and width of the channel region included in the junctionless gate-ring transistor. In this embodiment of the invention, the thickness and width of the first material portion are not specifically limited.

[0069] In one example, such as Figure 20 As shown, the channel region 29 of the junctionless gate ring transistor 33 has a different crystal orientation than the channel region 29 of the enhancement-mode junction gate ring transistor 34.

[0070] When using the above technical solution, in practical applications, the electron mobility and hole mobility corresponding to channel regions with different crystal orientations are different. For example, when the channel region material is silicon, the electron mobility corresponding to the channel region with the

[100] crystal orientation is approximately 350 cm⁻¹. -2 The corresponding hole mobility is approximately 75m / V·s. -2 The electron mobility corresponding to the

[110] crystal orientation channel region is approximately 230 cm⁻¹. -2 The hole mobility is approximately 180 cm / s, corresponding to a hole mobility of about 180 cm / s. -2 Approximately / V·s. In this case, since the conduction types of junctionless gate-around transistors (JGOT) and enhancement-mode JGOT transistors are opposite, when the crystal orientations of the channel regions included in the JGOT and the enhancement-mode JGOT transistors are different, the crystal orientation suitable for carrier conduction of the corresponding doping type can be determined at least according to the conduction types of these two transistors. This allows for simultaneous improvement of the carrier mobility of both JGOT and enhancement-mode JGOT transistors, thereby enhancing the electrical performance of the semiconductor device.

[0071] For example, the channel region of one of the junctionless gate ring transistors and enhancement-type junction ring transistors with a P-type conductivity type has a

[110] crystal orientation. For instance, when the conductivity type of the junctionless gate ring transistor is P-type, the crystal orientation of the junctionless gate ring transistor can be

[110] . In this case, since the channel region with a

[110] crystal orientation is conducive to the transport of holes, and the channel carriers of the P-type transistor are holes, setting the crystal orientation of the channel region of one of the junctionless gate ring transistors and enhancement-type junction ring transistors with a P-type conductivity type to the

[110] crystal orientation can improve the hole mobility of the channel region, thereby improving the electrical performance of the P-type transistor.

[0072] For example, when the material of the channel region included in one of the junctionless gate ring transistors and the enhancement-type junction ring gate transistors with an N-type conductivity type is silicon, the crystal orientation of the channel region included in one of the junctionless gate ring transistors and the enhancement-type junction ring gate transistors with an N-type conductivity type is

[100] crystal orientation. Alternatively, when the material of the channel region included in one of the junctionless gate ring transistors and the enhancement-type junction ring gate transistors with an N-type conductivity type is a high-mobility channel material, the crystal orientation of the channel region included in one of the junctionless gate ring transistors and the enhancement-type junction ring gate transistors with an N-type conductivity type is

[111] crystal orientation.

[0073] In practical applications, channel regions with different crystal orientations exhibit varying electron mobilities. Furthermore, channel regions with the same crystal orientation but made of different materials also exhibit different electron mobilities. Additionally, when the channel material is silicon, channel regions with the

[100] crystal orientation are more conducive to electron transport. Conversely, when the channel material is germanium-silicon or germanium, which are high-mobility channel materials, channel regions with the

[111] crystal orientation are more conducive to electron transport. Based on this, since the channel carriers of an N-type transistor are electrons, when the material of the channel region included in one of the junctionless gate ring transistors and the enhancement-type gate ring transistors with an N-type conductivity type is silicon, setting the crystal orientation of the channel region included in one of the junctionless gate ring transistors and the enhancement-type gate ring transistors with an N-type conductivity type to the

[100] crystal orientation, or when the material of the channel region included in one of the junctionless gate ring transistors and the enhancement-type gate ring transistors with an N-type conductivity type is a high-mobility channel material, setting the crystal orientation of the channel region included in one of the junctionless gate ring transistors and the enhancement-type gate ring transistors with an N-type conductivity type to the

[111] crystal orientation, the electron mobility of the channel region can be improved, thereby improving the electrical performance of the N-type transistor.

[0074] Of course, depending on the different requirements for carrier mobility of junctionless gate ring transistors and enhancement-junction gate ring transistors in actual application scenarios, the crystal orientation of the channel region included in both can be set to other suitable directions, as long as they can be applied to the semiconductor devices provided in the embodiments of the present invention.

[0075] In one example, such as Figure 13 Parts (1) and (2) in the text, and Figure 20 As shown, the aforementioned semiconductor device may further include a shallow trench isolation structure 22, a gate sidewall 24, and a dielectric layer 27. The shallow trench isolation structure 22 is formed on the first semiconductor substrate 1 to isolate different active regions of the first semiconductor substrate, preventing leakage. The thickness of the shallow trench isolation structure 22 can be set according to actual conditions. The material of the shallow trench isolation structure 22 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. The gate sidewall 24 is formed on at least both sides of the gate stack structure 32 along its length to isolate the gate stack structure 32 from other conductive structures, improving the electrical characteristics of the semiconductor device. The material of the gate sidewall 24 can be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 27 covers the first semiconductor substrate 1, and its top is flush with the top of the gate stack structure 32. In actual manufacturing, the presence of the dielectric layer 27 can protect the source region 25 and the drain region 26 from subsequent operations such as removing the sacrificial gate and the corresponding sacrificial layer (the third semiconductor layer and / or the fourth semiconductor layer, etc.), improving the yield of the semiconductor device. The dielectric layer 27 can be made of insulating materials such as silicon oxide or silicon nitride.

[0076] like Figure 24 As shown, this embodiment of the invention provides a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 23 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0077] First, a first semiconductor substrate is provided. The specific structure of this first semiconductor substrate can be found in the preceding text and will not be repeated here.

[0078] like Figures 19 to 23 As shown, a junctionless gate ring transistor 33 is formed on a first semiconductor substrate 1. An enhancement-type junction gate ring transistor 34 is formed above the junctionless gate ring transistor 33 and spaced apart from it. The enhancement-type junction gate ring transistor 34 has the opposite conductivity type to the junctionless gate ring transistor 33.

[0079] In practical applications, forming a junctionless gate ring transistor on the first semiconductor substrate and forming an enhancement-type junction ring transistor spaced apart from the junctionless gate ring transistor above it may include the following steps:

[0080] like Figure 6 As shown in parts (1) and (2) of the diagram, a bonding structure 13 is formed. The bonding structure 13 includes a first semiconductor substrate 1, at least one first semiconductor layer 3, a bonding layer 12, and at least one second semiconductor layer 9. Along the thickness direction of the first semiconductor substrate 1, at least one first semiconductor layer 3, the bonding layer 12, and at least one second semiconductor layer 9 are sequentially stacked on the first semiconductor substrate 1.

[0081] Specifically, each of the aforementioned first semiconductor layers is a film layer used to manufacture the active layer of the junctionless gate-around transistor described above. Therefore, the number of layers, crystal orientation, and material of the first semiconductor layer in the bonding structure are the same as those of the active layer in the junctionless gate-around transistor. Wherein, when the junctionless gate-around transistor includes at least two active layers, the channel region of the junctionless gate-around transistor includes at least two nanowires or sheets. Furthermore, as... Figure 1 and Figure 2 As shown in sections (1) and (2), the bonding structure includes at least two first semiconductor layers 3 and at least one third semiconductor layer 4. Each third semiconductor layer 4 is located between two adjacent first semiconductor layers 3, or between the bottom first semiconductor layer 3 and the first semiconductor substrate 1. The third semiconductor layer 4 is made of a different material than the first semiconductor layer 3.

[0082] Specifically, in the case where the bonding structure includes at least two first semiconductor layers, such as Figure 1 (1) part and Figure 2 As shown in part (1), the number of third semiconductor layers 4 in the bonding structure can be the same as the number of first semiconductor layers 3 in the bonding structure. Each third semiconductor layer 4 is located between two adjacent first semiconductor layers 3, or between the bottom first semiconductor layer 3 and the first semiconductor substrate 1.

[0083] Alternatively, the number of third semiconductor layers in the bonding structure may be one less than the number of first semiconductor layers in the bonding structure. In this case, since at least one first semiconductor layer is formed on the first semiconductor substrate, when the first semiconductor substrate is a semiconductor-on-insulator substrate, and the semiconductor material of the semiconductor-on-insulator substrate is different from the material of the first semiconductor layer, such as Figure 1 As shown in part (2), a semiconductor layer formed on a buried oxide layer in a semiconductor substrate on an insulator can be used as a sacrificial layer at the bottom. In this case, each third semiconductor layer 4 is located only between two adjacent first semiconductor layers 3.

[0084] Furthermore, as mentioned above, the channel region of a junctionless gate-around transistor can be made of high-mobility channel materials such as germanium-silicon or germanium. Based on this, when at least one first semiconductor layer contains germanium, such as... Figure 2 As shown in sections (1) and (2), the bonding structure may further include a first strain buffer layer 2 located between the first semiconductor substrate 1 and at least one first semiconductor layer 3. The presence of the first strain buffer layer 2 can provide stress to the at least one first semiconductor layer 3, thereby causing strain in the source region, drain region, and channel region of the junctionless gate-ring transistor formed based on the first semiconductor layer 3, thereby improving the carrier mobility in the junctionless gate-ring transistor and enhancing the electrical performance of the junctionless gate-ring transistor.

[0085] It should be noted that, when the bonding structure includes the first strain buffer layer and at least two first semiconductor layers, if the materials of the first strain buffer layer and the first semiconductor layers have a certain etching selectivity, the first strain buffer layer can be used as a sacrificial layer as the bottom layer. In this case, the bonding structure may include only one third semiconductor layer, with each third semiconductor layer located only between two adjacent first semiconductor layers.

[0086] The third semiconductor layer is a film layer used to at least form the gap between two adjacent active layers of the junctionless gate ring transistor. Therefore, the thickness of the third semiconductor layer can be set according to the thickness of the gate stack structure included in the junctionless gate ring transistor. The material of the third semiconductor layer can be any semiconductor material different from that of the first semiconductor layer.

[0087] Regarding the aforementioned at least one second semiconductor layer, each second semiconductor layer is a film layer used to at least fabricate the nanowires or sheets included in the channel region of the enhanced junction gate-around transistor (GMT-AOOT) described above. Therefore, the information such as the number of layers, crystal orientation, and material of the second semiconductor layer included in the bonding structure is the same as the information such as the number of layers, crystal orientation, and material of the nanowires or sheets included in the channel region of the GMT-AOOT transistor. For example, Figure 6 As shown in sections (1) and (2), when the channel region of the enhancement-type junction gate-around transistor includes at least two nanowires or sheets, the bonding structure 13 includes at least two second semiconductor layers 9, and the bonding structure 13 also includes at least one fourth semiconductor layer 10. Each fourth semiconductor layer 10 is located between two adjacent second semiconductor layers 9, and the materials of the fourth semiconductor layer 10 and the second semiconductor layer 9 are different.

[0088] Specifically, in cases where the bonding structure includes at least two second semiconductor layers, such as Figure 6 As shown in (2), the number of fourth semiconductor layers 10 in the bonding structure 13 can be one less than the number of second semiconductor layers 9 in the bonding structure 13. In this case, each fourth semiconductor layer 10 is located only on two adjacent second semiconductor layers 9.

[0089] Or, such as Figure 6 As shown in section (1), the number of fourth semiconductor layers 10 in the bonding structure 13 can be the same as the number of second semiconductor layers 9. In this case, each fourth semiconductor layer 10 is located on two adjacent second semiconductor layers 9, or on the top second semiconductor layer 9. The fourth semiconductor layer 10 located on the top second semiconductor layer 9 can reduce the damage caused by the etchant to the top of the second semiconductor layer 9 below it during the subsequent formation of the fin structure, thereby improving the formation quality of the channel region in the enhancement junction gate-around transistor.

[0090] The fourth semiconductor layer is a film layer used to at least form the gap between two adjacent nanowires or sheets included in the enhancement-junction-around-gate transistor. Therefore, the thickness of the fourth semiconductor layer can be set according to the thickness of the gate stack structure included in the enhancement-junction-around-gate transistor. The material of the fourth semiconductor layer can be any semiconductor material different from that of the second semiconductor layer.

[0091] As for the aforementioned bonding layer, this bonding layer is a film layer formed to bond at least one first semiconductor layer and at least one second semiconductor layer together. Specifically, the material and thickness of the bonding layer can be determined according to the actual application scenario, and are not specifically limited here. For example, if both the first semiconductor layer and the second semiconductor layer are made of silicon, the material of the bonding layer can be silicon dioxide.

[0092] In practical applications, the formation of the above-mentioned bonding structure may include the following steps: such as Figure 1 and Figure 2 As shown in parts (1) and (2), epitaxial growth and atomic layer deposition processes can be used to sequentially form at least one first semiconductor layer 3 and a first bonding layer 5 on at least one first semiconductor layer 3 along the thickness direction of the first semiconductor substrate 1. Wherein, as Figure 1 As shown in parts (1) and (2) of the diagram, when the bonding structure includes at least two first semiconductor layers 3, it is also necessary to use processes such as epitaxial growth to form the aforementioned at least one third semiconductor layer 4. Additionally, as... Figure 2 As shown in parts (1) and (2) of the diagram, when the first semiconductor layer 3 contains germanium, a first strain buffer layer 2 may be formed on the first semiconductor substrate 1 using a process such as epitaxial growth before forming at least one first semiconductor layer 3. Next, as... Figure 3 and Figure 4 As shown in sections (1) and (2), a second semiconductor substrate 6 is formed. This second semiconductor substrate 6 includes a semiconductor substrate 7, at least one second semiconductor layer 9 formed on the semiconductor substrate 7, and a second bonding layer 11 formed on the at least one second semiconductor layer 9. The semiconductor substrate 7 can be any semiconductor substrate such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, or a silicon-on-insulator substrate. Furthermore, if the bonding structure includes at least two second semiconductor layers 9, the second semiconductor substrate 6 also includes the aforementioned at least one fourth semiconductor layer 10. In this case, when forming the second semiconductor substrate 6, at least one second semiconductor layer 9 (or at least two second semiconductor layers 9 and at least one fourth semiconductor layer 10) can be formed on the semiconductor substrate 7 using processes such as epitaxial growth, and the aforementioned second bonding layer 11 can be formed using processes such as atomic layer deposition. Then, as... Figure 5 As shown, bonding processes such as direct silicon-to-silicon bonding or polymer bonding can be used to bond the second semiconductor substrate 6 to the first bonding sublayer 5, with the second bonding sublayer 11 facing away from the semiconductor substrate 7. Finally, as... Figure 6 As shown in parts (1) and (2) above, at least the semiconductor substrate is removed.

[0093] A bonding structure 13 is obtained. The bonding layer 12 includes a first bonding sublayer 5 and a second bonding sublayer 11. Specifically, after the second semiconductor substrate 6 is bonded to the first bonding sublayer 5, the structure to be removed can be determined based on the second semiconductor...

[0094] The film structure included in the substrate 6 is determined so that, after obtaining the bonding structure 13, the second semiconductor layer 9, which is closest to the semiconductor substrate, or the fourth semiconductor layer 10, which is closest to the semiconductor substrate, is exposed.

[0095] It should be noted that, as Figure 1 and Figure 2 As shown in parts (1) and (2) of the diagram, a semiconductor substrate 1 is formed on the substrate 1.

[0096] When the first semiconductor layer 3 is used to manufacture a junctionless gate ring transistor, at least a portion of the O region of the first semiconductor layer 3 can be doped to form the source region, drain region, and channel region included in the junctionless gate ring transistor, thereby solving the problem of existing...

[0097] In some technologies, multiple epitaxial and etching processes are required to form the source and drain regions of the N-type gate ring transistor and P-type gate ring transistor in the CFET device after forming the fin structure, resulting in high process complexity. Simplifying the manufacturing process of CFET devices can reduce the integration difficulty of CFET devices and improve the manufacturing efficiency of CFET devices.

[0098] 5. Furthermore, in this embodiment of the invention, the specific order of the two operation steps—forming at least one first semiconductor layer on at least one first semiconductor layer, and a first bonding layer located on at least one first semiconductor layer, and forming a second semiconductor substrate—is not specifically limited. Secondly, in the case where the semiconductor substrate is a non-insulator-on-a-semiconductor substrate, or where the material of the semiconductor layer located on the buried oxide layer in the insulator-on-a-semiconductor substrate is different from the material of the second semiconductor layer...

[0099] With a certain etching selectivity, the second semiconductor substrate further includes a fourth semiconductor layer with an equal number of layers as the second semiconductor layers. Each fourth semiconductor layer is located between two adjacent second semiconductor layers, or between the bottom second semiconductor layer and...

[0100] Between semiconductor substrates.

[0101] Furthermore, as mentioned above, the material of the channel region in an enhancement-mode junction-gate-around transistor can be a germanium-containing semiconductor material. Based on this, when at least one second semiconductor layer contains germanium, such as... Figure 4 (1) and (2)

[0102] As shown in the diagram, the second semiconductor substrate 6 may further include a second strain buffer layer 8 located between the semiconductor substrate 7 and at least one second semiconductor layer 9. The beneficial effects of this second strain buffer layer 8 can be referenced in the description of the first strain buffer layer above.

[0103] The beneficial effects of the second strain buffer layer are analyzed here, but will not be elaborated further. The material and thickness of the second strain buffer layer 8 can be set according to the actual application scenario, and are not specifically limited here. Wherein, in the case where a second strain buffer layer is formed on the surface of the semiconductor substrate, the above-mentioned removal of the semiconductor substrate includes the following steps: Figure 6 As shown in parts (1) and (2) of the document, dry...

[0104] Processes such as etching or wet etching are used to remove the semiconductor substrate and the second strain buffer layer to expose the second semiconductor layer 9, which is the closest to the semiconductor substrate, or the fourth semiconductor layer 10, which is the closest to the semiconductor substrate.

[0105] Next, as Figure 11 As shown in parts (1) and (2), at least one first semiconductor layer 3, a bonding layer 12, and at least one second semiconductor layer 9 are patterned to form a fin structure 18 on the first semiconductor substrate 1. Figure 11 As shown in parts (1) and (2), along the length direction of the fin structure 18, the fin structure 18 includes a first region 19, a second region 20, and a third region 21 located between the first region 19 and the second region 20.

[0106] Specifically, the object of the above patterning process can be determined based on the specific composition of the bonding structure. The specific morphology of the formed fin structure can be determined based on the semiconductor device being manufactured. Specifically, when the width of the channel region in a junctionless gate-around transistor and the channel region in an enhancement-mode junction-around-gate transistor are the same, such as... Figure 11 As shown in section (1), the membrane layers comprising the fin structure 18 are self-aligned. Alternatively, as... Figure 23 As shown, when the width of the channel region 29 included in the junctionless gate ring transistor 33 is greater than the width of the channel region 29 included in the enhancement-mode junction gate ring transistor 34, as Figure 11 As shown in part (2), the fin structure 18 includes a first fin 15 and a second fin 17. The first fin 15 is formed in the second fin 17. The width of the second fin 17 is greater than the width of the first fin 15. The first fin 15 includes at least one patterned second semiconductor layer and a bonding layer. The second fin 17 includes at least one patterned first semiconductor layer 3.

[0107] In practical applications, such as Figure 11 As shown in part (1), if the films included in the fin structure 18 are self-aligned, photolithography and etching processes can be used to etch downwards from the top of the second semiconductor layer (in the bonding structure, if the top film layer is the fourth semiconductor layer, it should be from the top of the fourth semiconductor layer) down to a portion of the first semiconductor substrate 1. Then, as Figure 7 As shown, the patterned mask layer is removed. Finally, as... Figure 11 As shown in part (1), a shallow trench isolation structure 22 can be formed on the first semiconductor substrate 1 using processes such as deposition and etching. The fin structure 18 is exposed outside the shallow trench isolation structure 22.

[0108] like Figure 23 As shown, when the width of the channel region 29 included in the junctionless gate ring transistor 33 is greater than the width of the channel region 29 included in the enhancement-mode junction gate ring transistor 34, as Figure 8 As shown, photolithography and etching processes can be used, and under the masking effect of the first mask layer 14, at least one second semiconductor layer and a bonding layer are patterned sequentially to form the first fin 15. The first mask layer 14 covers a portion of the at least one second semiconductor layer. The material of the first mask layer 14 can be photoresist or silicon nitride, etc. Next, as... Figure 9 As shown, photolithography and etching processes can be used to form a second mask layer 16 on at least both sides of the first fin 15 along its width direction. The material of the second mask layer 16 can be set according to actual needs and is not specifically limited here. Along the width direction of the first fin 15, the thickness of the second mask layer 16 is the width difference between the channel regions included in the junctionless gate ring transistor and the enhancement-mode junction gate ring transistor. Then, as... Figure 10 As shown, dry etching and wet etching processes are employed, and under the masking effect of the first mask layer 14 and the second mask layer 16, at least one first semiconductor layer 3 is patterned to form a second fin 17. The fin structure 18 includes the second fin 17 and the first fin 15. Finally, as... Figure 11 As shown in section (2), the first and second mask layers are removed. A shallow trench isolation structure 22 can be formed on the first semiconductor substrate 1 using processes such as deposition and etching. The fin structure 18 is exposed outside the shallow trench isolation structure 22.

[0109] Specifically, when forming the first fin and the second fin, the object of the patterning process can be determined based on the membrane layers included in the first fin and the second fin, which will not be elaborated here.

[0110] Finally, as Figures 19 to 23 As shown, a junctionless gate ring transistor 33 is formed based on at least one patterned first semiconductor layer 3, and an enhancement-type gate ring transistor 34 is formed based on at least one patterned second semiconductor layer.

[0111] In practical applications, such as Figure 12As shown, a sacrificial gate 23 and a gate sidewall 24 spanning the portion of the fin structure 18 corresponding to the third region 21 can be formed using processes such as deposition and etching. The gate sidewall 24 is formed at least on both sides of the sacrificial gate 23 along its length. Then, under the masking effect of the sacrificial gate 23, the sidewalls, and the corresponding mask layers, the exposed portion of the fin structure can be directly doped using processes such as ion implantation to form the source and drain regions included in the enhancement-type junction-gate-around transistor. The top of the aforementioned corresponding mask layer is higher than the bottom height of the bonding layer and lower than the top height of the bonding layer. Finally, as... Figure 13 As shown in section (1), the corresponding mask layer is removed.

[0112] Alternatively, the exposed portion of the fin structure can be removed using dry or wet etching processes, under the masking effect of the sacrificial gate, sidewalls, and corresponding mask layers. The top of the aforementioned mask layers is higher than the bottom height of the bonding layer but lower than the top height of the bonding layer. Then, epitaxial growth or other processes are used to form the source and drain regions of the enhancement-type junction-ring gate transistor on the patterned bonding layer. Finally, as... Figure 13 As shown in section (1), the corresponding mask layer is removed.

[0113] Next, as Figure 14 As shown, a dielectric layer 27 can be formed over the existing structure using processes such as deposition and chemical mechanical polishing. The top of this dielectric layer 27 is flush with the top of the sacrificial gate 23. Then, as... Figure 15 As shown, dry etching or wet etching processes can be used to remove at least the sacrificial gate and the portion of the bonding layer located in the third region. When the bonding structure also includes a corresponding sacrificial layer (which includes at least one of the aforementioned third semiconductor layer, fourth semiconductor layer, or first strain buffer layer), it is also necessary to remove the portion of the corresponding sacrificial layer located in the third region to release the channel region included in the junctionless gate-around transistor and the enhancement-junction gate-around transistor. Finally, as... Figures 20 to 23 As shown, a gate stack structure 32 is formed around the outer periphery of the channel region 29 using processes such as atomic layer deposition.

[0114] It should be noted that, as mentioned above, when the channel region of the enhancement-mode junction-gate-around transistor includes a first material portion and a second material portion, the above-described formation of the enhancement-mode junction-gate-around transistor based on at least one patterned second semiconductor layer may include the following steps:

[0115] like Figure 16 and Figure 17As shown, under the masking effect of the third mask layer 28, the portion of at least one second semiconductor layer corresponding to the third region is thinned. The third mask layer 28 covers the portion of at least one first semiconductor layer 3 corresponding to the third region, and the top height of the third mask layer 28 is greater than the top height of the first semiconductor layer 3 located at the top layer, and less than the bottom height of the second semiconductor layer located at the bottom layer. Each second semiconductor layer after the thinning process forms a corresponding first material portion 30.

[0116] In practical applications, such as Figure 16 As shown, after removing the portion of the sacrificial gate and corresponding sacrificial layer located in the third region, a third mask layer 28 can be formed in the partial gate formation region using processes such as deposition and etching. The specific height of this third mask layer 28 can be set according to actual needs, as long as it can protect at least one portion of the first semiconductor layer 3 located in the third region. Figure 17 As shown, the above-mentioned thinning process can be performed by sacrificial oxidation or similar methods. Specifically, when sacrificial oxidation is used, the portion of at least one second semiconductor layer corresponding to the third region can be oxidized and the oxide layer removed, thereby achieving the thinning of at least one second semiconductor layer and obtaining the first material portion 30.

[0117] like Figure 18 As shown, a second material portion 31 can be formed on the outer periphery of each first material portion 30 using processes such as epitaxial growth. The channel region 29 of the enhancement-mode junction-gate-around transistor includes both the first material portion 30 and the second material portion 31. The material of the second material portion 31 is different from the material of the first material portion 30. The material of the first material portion 30 is the same as the material of the channel region 29 of the junctionless gate-around transistor.

[0118] Specifically, the materials for the second materials department can be found in the previous text, and will not be repeated here.

[0119] Finally, as Figure 19 As shown, the third mask layer can be removed using processes such as dry etching or wet etching. The gate stack structure 32 comprising the enhanced junction-type gate-around transistor 34 and the junctionless gate-around transistor 33 can be formed using the methods described above.

[0120] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the semiconductor device described above, and will not be repeated here.

[0121] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0122] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: First semiconductor substrate, A junctionless gate-around transistor is formed on the first semiconductor substrate; An enhancement-mode junction-gate-around transistor is formed above and spaced apart from the junctionless gate-around transistor; the enhancement-mode junction-gate-around transistor has the opposite conductivity type to the junctionless gate-around transistor. The enhanced junction gate-around transistor includes a channel region comprising a first material portion and a second material portion surrounding the outer periphery of the first material portion; the material of the second material portion is different from the material of the first material portion; the material of the first material portion is the same as the material of the channel region included in the junctionless gate-around transistor.

2. The semiconductor device according to claim 1, characterized in that, The channel region of the junctionless gate-around transistor is made of a different material than the channel region of the enhancement-mode junction gate-around transistor.

3. The semiconductor device according to claim 1, characterized in that, When the conductivity type of the enhancement-mode junction-to-gate-around transistor is P-type, the material of the first material portion is silicon, and the material of the second material portion is a high-mobility channel material; or, When the conductivity type of the enhanced junction ring gate transistor is N-type, the material of the first material part is a high-mobility channel material, and the material of the second material part is silicon.

4. The semiconductor device according to claim 1, characterized in that, The channel region of the junctionless gate ring transistor has a different crystal orientation than the channel region of the enhancement-mode junction gate ring transistor.

5. The semiconductor device according to claim 4, characterized in that, The channel region of either the junctionless gate ring transistor or the enhancement-type gate ring transistor with a P-type conductivity has a crystal orientation of [110].

6. The semiconductor device according to claim 4, characterized in that, When the material of the channel region of either the junctionless gate ring transistor or the enhancement-type junction ring transistor (GMT-N) is silicon, the crystal orientation of the channel region of either the junctionless gate ring transistor or the enhancement-type GMT-N is [100]; or, When the channel region of the junctionless gate ring transistor and the enhancement-type gate ring transistor with an N-type conductivity type is made of a high-mobility channel material, the crystal orientation of the channel region of the junctionless gate ring transistor and the enhancement-type gate ring transistor with an N-type conductivity type is [111] crystal orientation.

7. The semiconductor device according to claim 1, characterized in that, The width of the channel region included in the junctionless gate-around transistor is greater than the width of the channel region included in the enhancement-mode junction-around-around transistor; and / or, The thickness of the channel region included in the junctionless gate ring transistor is greater than the thickness of the channel region included in the enhancement-mode junction gate ring transistor.

8. A method for manufacturing a semiconductor device, characterized in that, include: Provide a first semiconductor substrate; A junctionless gate-around transistor is formed on the first semiconductor substrate; and an enhancement-type junction-around transistor is formed above the junctionless gate-around transistor and spaced apart from it; the enhancement-type junction-around transistor has the opposite conductivity type to the junctionless gate-around transistor; the channel region of the enhancement-type junction-around transistor includes a first material portion and a second material portion surrounding the outer periphery of the first material portion; the material of the second material portion is different from the material of the first material portion; the material of the first material portion is the same as the material of the channel region of the junctionless gate-around transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The step of forming a junctionless gate-around transistor on the first semiconductor substrate and forming an enhancement-mode junction-around transistor spaced apart from the junctionless gate-around transistor above it includes: A bonding structure is formed; the bonding structure includes a first semiconductor substrate, at least one first semiconductor layer, a bonding layer, and at least one second semiconductor layer; along the thickness direction of the first semiconductor substrate, the at least one first semiconductor layer, the bonding layer, and the at least one second semiconductor layer are sequentially stacked on the first semiconductor substrate; At least the at least one first semiconductor layer, the bonding layer, and the at least one second semiconductor layer are patterned to form a fin structure on the first semiconductor substrate; The junctionless gate-around transistor is formed based on the at least one patterned first semiconductor layer, and the enhancement-mode gate-around transistor is formed based on the at least one patterned second semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, In the case where the channel region of the junctionless gate-ring transistor comprises at least two nanowires or sheets, the bonding structure comprises at least two first semiconductor layers, and the bonding structure further comprises at least one third semiconductor layer; each third semiconductor layer is located between two adjacent first semiconductor layers, or between the bottom first semiconductor layer and the first semiconductor substrate; the third semiconductor layer and the first semiconductor layer are made of different materials; and / or, In the case where the channel region of the enhanced junction gate-around transistor includes at least two nanowires or sheets, the bonding structure includes at least two second semiconductor layers, and the bonding structure further includes at least one fourth semiconductor layer; each of the fourth semiconductor layers is located between two adjacent second semiconductor layers, or on the top second semiconductor layer; the fourth semiconductor layer and the second semiconductor layer are made of different materials.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, When the material of the at least one first semiconductor layer contains germanium, the bonding structure further includes a first strain buffer layer located between the first semiconductor substrate and the at least one first semiconductor layer.

12. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of the bonding structure includes: Along the thickness direction of the first semiconductor substrate, at least one first semiconductor layer and a first bonding layer located on the at least one first semiconductor layer are sequentially formed on the first semiconductor substrate. A second semiconductor substrate is formed; the second semiconductor substrate includes a semiconductor substrate, at least one second semiconductor layer formed on the semiconductor substrate, and a second bonding layer formed on the at least one second semiconductor layer; The second semiconductor substrate is bonded to the first bonding sublayer on the side of the second bonding sublayer facing away from the semiconductor substrate; The semiconductor substrate is removed at least to obtain the bonding structure; wherein the bonding layer includes the first bonding sublayer and the second bonding sublayer.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, When the material of the at least one second semiconductor layer contains germanium, the second semiconductor substrate further includes a second strain buffer layer located between the semiconductor substrate and the at least one second semiconductor layer; The removal of at least the semiconductor substrate includes: removing the semiconductor substrate and the second strain buffer layer.

14. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The width of the channel region included in the junctionless gate ring transistor is greater than the width of the channel region included in the enhancement-mode junction gate ring transistor; The step of patterning at least the at least one first semiconductor layer, the bonding layer, and the at least one second semiconductor layer to form a fin-like structure on the first semiconductor substrate includes: Under the masking effect of the first mask layer, the at least one second semiconductor layer and the bonding layer are patterned sequentially to form a first fin; the first mask layer covers a portion of the at least one second semiconductor layer. A second mask layer is formed on at least both sides of the first fin along the width direction; Under the masking effect of the first mask layer and the second mask layer, at least one first semiconductor layer is patterned to form a second fin; the fin structure includes the second fin and the first fin; Remove the first mask layer and the second mask layer.

15. The method for manufacturing a semiconductor device according to claim 9, characterized in that, Along the length of the fin-like structure, the fin-like structure includes a first region, a second region, and a third region located between the first region and the second region; The formation of the enhancement junction gate-around transistor based on the at least one patterned second semiconductor layer includes: Under the masking effect of the third mask layer, the portion of the at least one second semiconductor layer corresponding to the third region is thinned; the third mask layer covers the portion of the at least one first semiconductor layer corresponding to the third region, and the top height of the third mask layer is greater than the top height of the first semiconductor layer at the top layer and less than the bottom height of the second semiconductor layer at the bottom layer; each second semiconductor layer after thinning forms a corresponding first material portion; A second material portion is formed on the outer periphery of the first material portion in each layer; wherein the channel region of the enhancement-type junction-gate-around transistor includes the first material portion and the second material portion; the material of the second material portion is different from the material of the first material portion; the material of the first material portion is the same as the material of the channel region of the junctionless gate-around transistor; Remove the third mask layer.

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