A semiconductor device and a method of fabricating the same

Abstract

Embodiments of the present application disclose a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor substrate of a first conductive type; a plurality of gate structures located in the semiconductor substrate of the first conductive type; and a floating region of a second conductive type located between two adjacent gate structures; wherein the first conductive type is opposite to the second conductive type; and in the floating region of the second conductive type, a doping concentration of a portion close to the gate structure is less than a doping concentration of a portion far from the gate structure.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In power devices, insulated-gate bipolar transistors (IGBTs) have gained increasingly widespread use due to their advantages such as high input impedance, low on-state voltage drop, and high frequency characteristics. They have become one of the core components in modern power electronic circuits and are widely used in transportation, energy, industry, and home appliances. However, current IGBT devices struggle to balance electromagnetic interference (EMI) with turn-on losses. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor device and a method for fabricating the same.

[0004] According to a first aspect of the embodiments of this application, a semiconductor device is provided, comprising:

[0005] Semiconductor substrate of the first conductivity type;

[0006] Multiple gate structures are located within a semiconductor substrate of the first conductivity type;

[0007] The floating region of the second conductivity type is located between two adjacent gate structures; wherein the first conductivity type is opposite to the second conductivity type.

[0008] Within the floating region of the second conductivity type, the doping concentration of the portion closer to the gate structure is less than the doping concentration of the portion farther from the gate structure.

[0009] In some embodiments, it also includes:

[0010] An insulating dielectric layer is located on the gate structure and the floating region of the second conductivity type;

[0011] The gate structure and the floating region of the second conductivity type are insulated and isolated from the emitter of the semiconductor device by an insulating dielectric layer.

[0012] In some embodiments, along the direction from the middle position of the floating region toward the gate structure, the floating region of the second conductivity type includes a first floating region and a second floating region; wherein the doping concentration of the first floating region and the second floating region decreases in a gradient.

[0013] In some embodiments, the doping concentration range of the first floating region is 1*102 17 cm -3 ~1*10 19 cm -3The doping concentration range of the second floating region is 1*10. 12 cm -3 ~1*10 14 cm -3 .

[0014] In some embodiments, along the direction from the middle position of the floating region toward the gate structure, the floating region of the second conductivity type includes a first floating region, a second floating region, and a third floating region; wherein the doping concentration of the first floating region, the second floating region, and the third floating region decreases in a gradient.

[0015] In some embodiments, the doping concentration range of the first floating region is 1*102 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region is 1*10. 14 cm -3 ~1*10 17 cm -3 The doping concentration range of the third floating region is 1*10. 12 cm -3 ~1*10 14 cm -3 .

[0016] In some embodiments, the system further includes: a collector metal layer, a collector layer of a second conductivity type, and a buffer layer of a first conductivity type, sequentially stacked beneath a semiconductor substrate of the first conductivity type; wherein...

[0017] The current collector metal layer is in ohmic contact with the current collector layer of the second conductivity type.

[0018] In some embodiments, it also includes:

[0019] The base region of the second conductivity type is located on the side of the gate structure away from the floating region of the second conductivity type;

[0020] The emitter region of the first conductivity type is located in the upper part of the base region of the second conductivity type and is in contact with the sidewall of the gate structure;

[0021] An emitter metal layer is located on a base region of the second conductivity type and an emitter region of the first conductivity type; wherein the base region of the second conductivity type and the emitter region of the first conductivity type are in ohmic contact with the emitter metal layer.

[0022] According to a second aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided, comprising:

[0023] Provide a semiconductor substrate of a first conductivity type;

[0024] Multiple gate structures are formed within a semiconductor substrate of the first conductivity type;

[0025] A floating region of a second conductivity type is formed between two adjacent gate structures; wherein the first conductivity type is opposite to the second conductivity type;

[0026] Within the floating region of the second conductivity type, the doping concentration of the portion closer to the gate structure is less than the doping concentration of the portion farther from the gate structure.

[0027] In some embodiments, it also includes:

[0028] After forming the floating region of the second conductivity type, an insulating dielectric layer is formed on the gate structure and the floating region of the second conductivity type.

[0029] The gate structure and the floating region of the second conductivity type are insulated and isolated from the emitter of the semiconductor device by an insulating dielectric layer.

[0030] In this embodiment, by setting the doping concentration of the floating region to be less in the part closer to the gate structure than in the part farther from the gate structure, i.e., the doping concentration of the floating region decreases from the middle to both sides, the accumulated holes can be discharged, so that the holes are far away from the capacitance between the floating region and the gate structure, thereby reducing the charging process, thereby reducing the displacement current and enhancing the gate structure's control over EMI and turn-on losses. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a conventional IGBT device.

[0032] Figure 2 Schematic diagram of semiconductor device structure provided for related technologies;

[0033] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0035] Figure 5 A schematic diagram of the energy levels of the floating region of a semiconductor device provided in an embodiment of this application;

[0036] Figure 6 A schematic flowchart illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0037] Figures 7a to 7e This is a schematic diagram of the semiconductor device provided in the embodiment of this application during the fabrication process.

[0038] Explanation of reference numerals in the attached figures:

[0039] 10 - Semiconductor substrate of the first conductivity type; 11 - Current collector layer of the second conductivity type; 12 - Buffer layer of the first conductivity type;

[0040] 20 - Gate structure; 21 - Gate oxide layer; 22 - Polysilicon gate;

[0041] 30 - Second type of floating region; 31 - First floating region; 32 - Second floating region; 33 - Third floating region;

[0042] 40 - Insulating dielectric layer; 50 - Base region of second conductivity type; 60 - Emitter region of first conductivity type; 70 - Emitter metal layer; 80 - Collector metal layer. Detailed Implementation

[0043] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0045] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0050] Figure 1 This is a schematic diagram of a conventional IGBT device. Conventional IGBT devices have a high on-state voltage drop and insufficient withstand voltage. To improve the short-circuit withstand capability, the channel density needs to be reduced; therefore, a floating p-base region is incorporated. Specifically, as shown... Figure 2 As shown, the floating P-type region 20' will collect more holes, causing its potential to rise. Therefore, a large displacement current will be formed between the floating P-type region 20' and the gate structure 30', which will cause the gate structure to be uncontrolled by the applied voltage, and the relationship between EMI and turn-on loss will also become very poor.

[0051] Based on this, embodiments of this application provide a semiconductor device. Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0052] See Figure 3 The semiconductor device includes: a semiconductor substrate 10 of a first conductivity type; a plurality of gate structures 20 located within the semiconductor substrate 10 of the first conductivity type; and a floating region 30 of a second conductivity type located between two adjacent gate structures 20; wherein the first conductivity type is opposite to the second conductivity type; and within the floating region 30 of the second conductivity type, the doping concentration of the portion closer to the gate structure 20 is less than the doping concentration of the portion farther away from the gate structure 20.

[0053] In this embodiment, by setting the doping concentration of the floating region to be less in the part closer to the gate structure than in the part farther from the gate structure, for example, the doping concentration of the floating region decreases from the middle to both sides, the accumulated holes can be discharged, so that the holes are far away from the capacitance between the floating region and the gate structure, thereby reducing the charging process, thereby reducing the displacement current and enhancing the gate structure's control over EMI and turn-on losses.

[0054] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type. This application uses an example where the first conductivity type is N-type and the second conductivity type is P-type for illustration.

[0055] The first type of conductive semiconductor substrate 10 can be a single semiconductor material substrate (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., germanium silicon (SiGe) substrate, etc.), or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

[0056] In one embodiment, the semiconductor substrate 10 of the first conductivity type is a drift layer of the first conductivity type; the gate structure 20 and the floating region 30 of the second conductivity type are located within the drift layer of the first conductivity type.

[0057] The semiconductor device further includes: a collector metal layer 80, a collector layer 11 of a second conductivity type, and a buffer layer 12 of a first conductivity type, sequentially stacked under a semiconductor substrate of the first conductivity type; wherein the collector metal layer 80 is in ohmic contact with the collector layer 11 of the second conductivity type. In a specific implementation, the collector C of the semiconductor device can be formed through the collector layer 11 of the second conductivity type and the collector metal layer 80.

[0058] Specifically, the current collector layer 11 of the second conductivity type can be a P+ current collector layer. The buffer layer 12 of the first conductivity type is located on the current collector layer 11 of the second conductivity type; the buffer layer 12 of the first conductivity type can be an N+ buffer layer. The drift layer of the first conductivity type is located on the buffer layer 12 of the first conductivity type; the drift layer of the first conductivity type can be an N- drift layer. The thickness of the drift layer of the first conductivity type is greater than that of the buffer layer 12 of the first conductivity type, and the doping concentration of the drift layer of the first conductivity type is less than that of the buffer layer 12 of the first conductivity type.

[0059] The gate structure 20 is a trench gate, including a gate oxide layer 21 and a polycrystalline gate 22, with the polycrystalline gate 22 located within the gate oxide layer 21. The gate electrode G is connected to the polycrystalline gate 22.

[0060] In one embodiment, such as Figure 3 As shown, along the direction from the middle position of the floating region 30 toward the gate structure 20, the second conductivity type of floating region 30 includes a first floating region 31 and a second floating region 32; wherein, the doping concentration of the first floating region 31 and the second floating region 32 decreases in a gradient.

[0061] Specifically, the first floating region 31 is a P+ floating region, and the second floating region is a P- floating region. The doping concentration range of the first floating region 31 is 1*10⁻⁶. 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region 32 is 1*10.12 cm -3 ~1*10 14 cm -3 .

[0062] In another embodiment, such as Figure 4 As shown, along the direction from the middle position of the floating region 30 toward the gate structure 20, the second conductivity type of floating region 30 includes a first floating region 31, a second floating region 32 and a third floating region 33; wherein, the doping concentration of the first floating region 31, the second floating region 32 and the third floating region 33 decreases in a gradient.

[0063] Specifically, the first floating region 31 is a P+ floating region, the second floating region is a P-type floating region, and the third floating region is a P- floating region. 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region 32 is 1*10. 14 cm -3 ~1*10 17 cm -3 The doping concentration range of the third floating region 33 is 1*10. 12 cm -3 ~1*10 14 cm -3 .

[0064] Understandably, in Figure 3 and Figure 4 In the embodiments shown, the floating area 30 is divided into 3-layer and 5-layer structures, which is only a subordinate and feasible specific implementation method in this application and does not constitute a limitation on this application. The floating area 30 can also be divided into other multi-layer structures.

[0065] In such Figure 3 and Figure 4 In the illustrated embodiment, the doping concentration of the floating region 30 of the second conductivity type decreases gradually along the direction from the middle position of the floating region 30 toward the gate structure 20; in other embodiments, the doping concentration of the floating region 30 of the second conductivity type may gradually decrease along the direction from the middle position of the floating region 30 toward the gate structure 20.

[0066] Figure 5 This is a schematic diagram of the energy levels in the floating region of a semiconductor device provided in an embodiment of this application. In the figure, E... C E represents the conductor band. F Represents the Fermi level, E V Representative price band.

[0067] by Figure 3 Taking the floating region 30 of the second conductivity type as an example, when the majority carriers in the floating region are holes, since the doping concentration of the P+ floating region is greater than that of the P- floating region, the Fermi level E of the P+ floating region is higher. F With the P+ floating zone, the guide band E C The distance between them is greater than the Fermi level E in the P-floating region. F With the P-floating zone's guide band E C The distance between them.

[0068] Located in the P+ floating zone price band E V The potential energy of nearby holes is lower than that of the valence band E in the P-float region. V The potential energy of nearby holes. Due to their location in the valence band E of the P+ floating region. V The nearby vacancy and the valence band E located in the P-float region V There is a potential energy difference between the holes in the vicinity. Therefore, on the one hand, it can promote the movement of more holes in the P- floating region to the P+ floating region, and on the other hand, it can hinder the movement of holes in the P+ floating region to the P- floating region. This is conducive to the accumulation of holes in the region with higher P doping concentration, so that the holes are far away from the capacitance between the floating region and the gate structure, thereby reducing the charging process, reducing the displacement current, and enhancing the gate structure's control over EMI and turn-on losses.

[0069] In one embodiment, the semiconductor device further includes an insulating dielectric layer 40 located on the gate structure 20 and the floating region 30 of the second conductivity type; the gate structure 20 and the floating region 30 of the second conductivity type are insulated and isolated from the emitter E of the semiconductor device through the insulating dielectric layer 40.

[0070] In one embodiment, the semiconductor device further includes: a base region 50 of a second conductivity type, located on the side of the gate structure 20 away from the floating region 20 of the second conductivity type; an emitter region 60 of a first conductivity type, located in the upper part of the base region 50 of the second conductivity type and in contact with the sidewall of the gate structure 20; and an emitter metal layer 70 located on the base region 50 of the second conductivity type and the emitter region 60 of the first conductivity type; wherein the base region 50 of the second conductivity type and the emitter region 60 of the first conductivity type are in ohmic contact with the emitter metal layer 70. After the emitter region 60 of the first conductivity type is in ohmic contact with the emitter metal layer 70, it forms the emitter E of the semiconductor device through the emitter metal layer 70.

[0071] The emitter metal layer 70 is located not only on the base region 50 of the second conductivity type and the emitter region 60 of the first conductivity type, but also on the insulating dielectric layer 40.

[0072] Specifically, the base region 50 of the second conductivity type is a P-type base region, and the emitter region 60 of the first conductivity type is an N+ emitter region.

[0073] In one embodiment, the semiconductor device may be a field-stop IGBT device; in another embodiment, the semiconductor device may be a through-type IGBT device, a non-through-type IGBT device, or a MOSFET device.

[0074] This application also provides a method for fabricating a semiconductor device, please refer to the appendix for details. Figure 6 As shown in the figure, the method includes the following steps:

[0075] Step 601: Provide a semiconductor substrate of a first conductivity type;

[0076] Step 602: Form a plurality of gate structures in a semiconductor substrate of the first conductivity type;

[0077] Step 603: Form a floating region of a second conductivity type between two adjacent gate structures; wherein the first conductivity type is opposite to the second conductivity type; in the floating region of the second conductivity type, the doping concentration of the portion closer to the gate structure is less than the doping concentration of the portion farther from the gate structure.

[0078] The method for fabricating the semiconductor device provided in this application will be further described in detail below with reference to specific embodiments.

[0079] Figures 7a to 7e This is a schematic diagram of the semiconductor device provided in the embodiment of this application during the fabrication process.

[0080] It should be explained that, in some embodiments, during the fabrication of the semiconductor device, a gate structure 20 and a floating region 30 of the second conductivity type are first formed in the semiconductor substrate 10 of the first conductivity type, and then a collector metal layer 80, a collector layer 11 of the second conductivity type, and a buffer layer 12 of the first conductivity type are sequentially stacked on the back side of the semiconductor substrate 10. In other embodiments, during the fabrication of the semiconductor device, a collector metal layer 80, a collector layer 11 of the second conductivity type, and a buffer layer 12 of the first conductivity type are first formed on the back side of the semiconductor substrate 10; then a gate structure 20 and a floating region 30 of the second conductivity type are formed in the semiconductor substrate 10.

[0081] In the embodiments of this application, such as Figures 7a to 7e As shown, the following example illustrates the process of first forming a gate structure 20 and a floating region 30 of the second conductivity type, and then forming a collector metal layer 80, a collector layer 11 of the second conductivity type, and a buffer layer 12 of the first conductivity type.

[0082] First, see Figure 7a Step 601 is performed, providing a semiconductor substrate 10 of a first conductivity type.

[0083] The first type of conductive semiconductor substrate 10 can be a single semiconductor material substrate (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., germanium silicon (SiGe) substrate, etc.), or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

[0084] In one embodiment, the semiconductor substrate 10 of the first conductivity type is a drift layer of the first conductivity type, and the drift layer of the first conductivity type can be an N-drift layer.

[0085] Next, see Figure 7b Step 602 is performed to form a plurality of gate structures 20 in the semiconductor substrate 10 of the first conductivity type.

[0086] The gate structure 20 is a trench gate, including a gate oxide layer 21 and a polycrystalline gate 22, with the polycrystalline gate 22 located within the gate oxide layer 21. The gate electrode G is connected to the polycrystalline gate 22.

[0087] Next, see Figure 7c Step 603 is executed to form a floating region 30 of a second conductivity type between two adjacent gate structures 20; wherein the first conductivity type is opposite to the second conductivity type; within the floating region 30 of the second conductivity type, the doping concentration of the portion closer to the gate structure 20 is less than the doping concentration of the portion farther away from the gate structure 20.

[0088] Specifically, different doses of ions, such as boron ions, are injected into the floating region 30 of the second conductivity type to divide the floating region 30 into portions with different doping concentrations.

[0089] In one embodiment, see Figure 7c In the floating region 30 near the gate structure 20, a dose of 1*10 is injected. 12 cm -2 ~1*10 13 cm -2 Boron ions are implanted at a dose of 1*10 in the portion away from the gate structure 20. 14 cm -2 ~1*10 15 cm -2Boron ions are used to divide the floating region 30 into a first floating region 31 and a second floating region 32 in a direction from the middle position of the floating region 30 toward the gate structure 20; wherein the doping concentration of the first floating region 31 and the second floating region 32 decreases in a gradient.

[0090] Specifically, the first floating region 31 is a P+ floating region, and the second floating region is a P- floating region. The doping concentration range of the first floating region 31 is 1*10⁻⁶. 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region 32 is 1*10. 12 cm -3 ~1*10 14 cm -3 .

[0091] In another embodiment, such as Figure 4 As shown, along the direction from the middle position of the floating region 30 toward the gate structure 20, the second conductivity type of floating region 30 includes a first floating region 31, a second floating region 32 and a third floating region 33; wherein, the doping concentration of the first floating region 31, the second floating region 32 and the third floating region 33 decreases in a gradient.

[0092] Specifically, the first floating region 31 is a P+ floating region, the second floating region is a P-type floating region, and the third floating region is a P- floating region. 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region 32 is 1*10. 14 cm -3 ~1*10 17 cm -3 The doping concentration range of the third floating region 33 is 1*10. 12 cm -3 ~1*10 14 cm -3 .

[0093] Understandably, in Figure 7c and Figure 4 In the embodiments shown, the floating area 30 is divided into 3-layer and 5-layer structures, which is only a subordinate and feasible specific implementation method in this application and does not constitute a limitation on this application. The floating area 30 can also be divided into other multi-layer structures.

[0094] In such Figure 7c and Figure 4In the illustrated embodiment, the doping concentration of the floating region 30 of the second conductivity type decreases gradually along the direction from the middle position of the floating region 30 toward the gate structure 20; in other embodiments, the doping concentration of the floating region 30 of the second conductivity type may gradually decrease along the direction from the middle position of the floating region 30 toward the gate structure 20.

[0095] Next, see [link / reference] Figure 7c In the same step of forming the floating region 30 of the second conductivity type, the method further includes: forming a base region 50 of the second conductivity type and an emitter region 60 of the first conductivity type; the base region 50 of the second conductivity type is located on the side of the gate structure 20 away from the floating region 20 of the second conductivity type; the emitter region 60 of the first conductivity type is located in the upper part of the base region 50 of the second conductivity type and is in contact with the sidewall of the gate structure 20.

[0096] Next, see Figure 7d After forming the floating region 30 of the second conductivity type, an insulating dielectric layer 40 is formed on the gate structure 20 and the floating region 30 of the second conductivity type; the gate structure 20 and the floating region 30 of the second conductivity type are insulated and isolated from the emitter E of the semiconductor device through the insulating dielectric layer 40.

[0097] Next, see [link / reference] Figure 7d After forming the insulating dielectric layer 40, an emitter metal layer 70 is formed on the insulating dielectric layer 40, the base region 50 of the second conductivity type, and the emitter region 60 of the first conductivity type. The base region 50 of the second conductivity type and the emitter region 60 of the first conductivity type are in ohmic contact with the emitter metal layer 70. After the emitter region 60 of the first conductivity type is in ohmic contact with the emitter metal layer 70, it forms the emitter E of the semiconductor device through the emitter metal layer 70.

[0098] Next, see Figure 7e A collector metal layer 80, a collector layer 11 of a second conductivity type, and a buffer layer 12 of a first conductivity type are sequentially stacked on the back side of the semiconductor substrate 10 of the first conductivity type.

[0099] Specifically, a buffer layer 12 of a first conductivity type is formed on the back side of the semiconductor substrate 10 of the first conductivity type. The buffer layer 12 of the first conductivity type can be an N+ buffer layer. A collector layer 11 of a second conductivity type is formed on the back side of the buffer layer 12 of the first conductivity type. The collector layer 11 of the second conductivity type can be a P+ collector layer. A collector metal layer 80 is formed on the back side of the collector layer 11 of the second conductivity type. The thickness of the semiconductor substrate 10 of the first conductivity type is greater than that of the buffer layer 12 of the first conductivity type, and the doping concentration of the semiconductor substrate 10 of the first conductivity type is less than that of the buffer layer 12 of the first conductivity type.

[0100] The collector metal layer 80 is in ohmic contact with the collector layer 11 of the second conductivity type. In a specific implementation, the collector C of the semiconductor device can be formed by the collector layer 11 of the second conductivity type and the collector metal layer 80.

[0101] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

[0102] In some embodiments, the gate structure 20 may not overlap with the floating region 30, which can further alleviate the large accumulation of holes on the trench sidewalls, thereby reducing the displacement current and further enhancing the gate structure's control over EMI and turn-on losses.

[0103] In some embodiments, the gate structure 20 may further include a first gate structure and a second gate structure, wherein the first gate structure is located above the second gate structure, the first gate structure and the second gate structure are separated by a dielectric layer, and the width of the first gate structure is smaller than the width of the second gate structure. The floating region 30 overlaps with the second gate structure but does not overlap with the first gate structure. By setting the floating region 30 to not overlap with the first gate structure, the accumulation of large amounts of holes on the sidewalls of the gate structure can be further alleviated, and the gate structure's control over EMI and turn-on losses can be further enhanced. On the other hand, the overlap of the floating region 30 with the wider second gate structure can effectively reduce the electric field peak at the corner of the gate structure and improve the withstand voltage.

[0104] Furthermore, in some embodiments, the doping concentration of the upper part of the floating region 30 may be lower than the doping concentration of the lower part. In some specific embodiments, for example, the first floating region includes an overlapping first upper floating region and a first lower floating region, wherein the doping concentration of the first upper floating region is lower than that of the first lower floating region; and / or, the second floating region includes an overlapping second upper floating region and a second lower floating region, wherein the doping concentration of the second upper floating region is lower than that of the second lower floating region; and / or, the third floating region includes an overlapping third upper floating region and a third lower floating region, wherein the doping concentration of the third upper floating region is lower than that of the third lower floating region. Since electric field peaks are easily generated at the corners of the gate structure, this embodiment sets the doping concentration of the lower part of the floating region 30 near the corner of the gate structure to be greater than that of the upper part, which can effectively reduce the electric field peaks at the corners of the gate structure. At the same time, the lower doping concentration at the upper part can also improve hole accumulation at the sidewalls of the gate structure 20, thereby simultaneously alleviating the problems of hole accumulation and electric field peaks at the gate corners.

[0105] In a specific embodiment, the doping concentration of the second upper floating region can be, for example, 0.1-0.35 times the doping concentration of the second lower floating region, such as 0.2, 0.25, or 0.3, and the vertical height of the second lower floating region is 0.25-0.4 times the vertical height of the second upper floating region, such as 0.3 or 0.35. The first and third floating regions can also adopt the parameter range of the second floating region described above. By setting the ratio of concentration to height within the above range, this embodiment can obtain an optimal solution to the problems of gate corner electric field peak and hole accumulation on the gate structure sidewalls.

[0106] Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate of the first conductivity type; Multiple gate structures are located within a semiconductor substrate of the first conductivity type; The floating region of the second conductivity type is located between two adjacent gate structures; wherein the first conductivity type is opposite to the second conductivity type. Within the floating region of the second conductivity type, the doping concentration of the portion closer to the gate structure is less than the doping concentration of the portion farther from the gate structure; the floating region of the second conductivity type includes an upper floating region and a lower floating region that overlap, and the doping concentration of the upper floating region is less than the doping concentration of the lower floating region.

2. The semiconductor device according to claim 1, characterized in that, Also includes: An insulating dielectric layer is located on the gate structure and the floating region of the second conductivity type; The gate structure and the floating region of the second conductivity type are insulated and isolated from the emitter of the semiconductor device by an insulating dielectric layer.

3. The semiconductor device according to claim 1, characterized in that, Along the direction from the middle of the floating region toward the gate structure, the floating region of the second conductivity type includes a first floating region and a second floating region; wherein the doping concentration of the first floating region and the second floating region decreases in a gradient.

4. The semiconductor device according to claim 3, characterized in that, The doping concentration range of the first floating region is 1*10. 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region is 1*10. 12 cm -3 ~1*10 14 cm -3 .

5. The semiconductor device according to claim 1, characterized in that, Along the direction from the middle of the floating region toward the gate structure, the floating region of the second conductivity type includes a first floating region, a second floating region, and a third floating region; wherein the doping concentration of the first floating region, the second floating region, and the third floating region decreases in a gradient.

6. The semiconductor device according to claim 5, characterized in that, The doping concentration range of the first floating region is 1*10. 17 cm -3 ~1*10 19 cm -3 The doping concentration range of the second floating region is 1*10. 14 cm -3 ~1*10 17 cm -3 The doping concentration range of the third floating region is 1*10. 12 cm -3 ~1*10 14 cm -3 .

7. The semiconductor device according to claim 1, characterized in that, Also includes: A collector metal layer, a collector layer of a second conductivity type, and a buffer layer of the first conductivity type are sequentially stacked beneath a semiconductor substrate of the first conductivity type; wherein... The current collector metal layer is in ohmic contact with the current collector layer of the second conductivity type.

8. The semiconductor device according to claim 1, characterized in that, Also includes: The base region of the second conductivity type is located on the side of the gate structure away from the floating region of the second conductivity type; The emitter region of the first conductivity type is located in the upper part of the base region of the second conductivity type and is in contact with the sidewall of the gate structure; An emitter metal layer is located on a base region of the second conductivity type and an emitter region of the first conductivity type; wherein the base region of the second conductivity type and the emitter region of the first conductivity type are in ohmic contact with the emitter metal layer.

9. A method for fabricating a semiconductor device, characterized in that, include: Provide a semiconductor substrate of a first conductivity type; Multiple gate structures are formed within a semiconductor substrate of the first conductivity type; A floating region of a second conductivity type is formed between two adjacent gate structures; wherein the first conductivity type is opposite to the second conductivity type; Within the floating region of the second conductivity type, the doping concentration of the portion closer to the gate structure is less than the doping concentration of the portion farther from the gate structure; the floating region of the second conductivity type includes an upper floating region and a lower floating region that overlap, and the doping concentration of the upper floating region is less than the doping concentration of the lower floating region.

10. The method according to claim 9, characterized in that, Also includes: After forming the floating region of the second conductivity type, an insulating dielectric layer is formed on the gate structure and the floating region of the second conductivity type. The gate structure and the floating region of the second conductivity type are insulated and isolated from the emitter of the semiconductor device by an insulating dielectric layer.

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