System and method for unified data packet recycling

Abstract

The present application relates to a system and method for unified packet recirculation. An apparatus includes an ingress data buffer, an ingress processor, an egress processor, and a recirculation data buffer. The apparatus is configured to provide unified packet recirculation via the recirculation data buffer and a single recirculation port on the ingress data buffer. The apparatus may be a switch, a router, or other network device.

Description

Technical Field

[0001] The present disclosure relates generally to systems and methods for communicating data in a network environment, and more particularly, to systems and methods for reintroducing, looping back, or otherwise recycling data packets, frames, or other data units. Background Art

[0002] The communications industry is rapidly changing to adapt to emerging technologies and growing customer demands. The demand for new network applications and higher performance requires communications networks to operate at faster speeds (e.g., higher bandwidth). Many communications providers are using packet switching technology to achieve these goals. Storage, communications, entertainment, and computer systems utilize switches, such as routers, packet switching systems, and other network data processing devices, to communicate packets, frames, or other data units.

[0003] A switch is a hardware component of a network that controls the distribution of messages or packets, frames, or other data units based on the address information contained in each packet. The term packet, as used herein, is not limited to a specific protocol or format for a data unit or frame. A switch may receive a packet at an ingress port, process the packet in the ingress pipeline, process the packet in the egress pipeline, and copy the packet to the appropriate egress port. Recycling is a technique a switch uses to allow a packet to re-enter packet processing. Packet recyclering may involve repeating ingress and egress processing of a packet after it has already traversed the egress pipeline. Summary of the Invention

[0004] In one aspect, the present application relates to a network device comprising: an ingress pipeline; an egress pipeline; an ingress data buffer comprising a recirculation port; and a recirculation data buffer coupled to the recirculation port, wherein the egress pipeline and the ingress pipeline are configured to mark data packets for recirculation, wherein the data packets are provided to the recirculation data buffer to be provided to the recirculation port, wherein the ingress data buffer is configured to provide the data packets to the ingress pipeline.

[0005] In another aspect, the present application relates to a method for recycling data packets, the method comprising: marking a first data packet for recycling in an ingress pipeline; providing the first data packet to an egress pipeline; providing the first data packet from the egress pipeline to an egress data buffer and providing a copy of the first data packet at the recycling data buffer; and providing the copy of the first data packet from the recycling data buffer to an ingress data buffer.

[0006] In another aspect, the present application relates to an apparatus comprising: an ingress data buffer; an ingress processor; an egress processor; and a recirculating data buffer, wherein the apparatus is configured to provide unified packet recirculation via the recirculating data buffer and a single recirculation port on the ingress data buffer.

[0007] In another aspect, the present application relates to an apparatus comprising: an ingress data buffer; an ingress processor; an egress processor; and a recirculating data buffer, wherein the recirculating buffer is configured to copy or edit a data packet and provide the copied or edited data packet to a recirculating port on the ingress data buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0009] Figure 1 is a general block diagram depicting network devices within a network according to some embodiments;

[0010] Figure 2 According to some embodiments Figure 1 A more detailed block diagram of a portion of an inlet pipeline and an outlet pipeline of a network device described in;

[0011] Figure 3 According to some embodiments, Figure 1 A more detailed block diagram of the recirculating data buffer of the network device described in ; and

[0012] Figure 4 According to some embodiments Figure 3 A more detailed block diagram of packets processed in portions of the ingress and egress pipelines illustrated in FIG.

[0013] The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0014] In some embodiments, a network device, such as a switch, provides unified recirculation egress decision making (e.g., egress pipeline recirculation (EPRC)) and recirculation ingress decision making (e.g., loopback port decision making). In some embodiments, the unified approach advantageously reduces complexity while requiring a smaller area (e.g., 3.5 square millimeters (mm)) than a non-unified approach. 2 ) compared to 27mm 2In some embodiments, additional and separate ports for loopback and egress recirculation are not required. In a non-uniform packet recirculation architecture, loopback and EPRC features, configurations, programming models, formats, ports, scheduling, etc. are separate. In some embodiments, the same programming model makes decisions for packet recirculation in both the ingress and egress pipelines at a fraction of the cost, without the complexity of a non-uniform model, while enabling new features. As used herein, the terms recirculate and recirculate may refer to egress and ingress recirculation, reinsertion, loopback, reintroduction, and other forms of re-entering a data unit (e.g., a frame, packet, etc.) into the ingress or egress pipeline.

[0015] In a non-uniform packet recirculation architecture, the decision to route a packet is made in the ingress pipeline, and the egress pipeline cannot make decisions to reroute a packet after it is dequeued from the memory manager. This can be a significant limitation for some features, as some information is only available after dequeuing. In some embodiments, the unified approach can support additional features that are not supported in the non-uniform approach.

[0016] In some applications, data centers use recycling for visibility / debugging and instrumentation / telemetry features. In some embodiments, unified packet recycling systems and methods not only unify and simplify recycling for these and other applications, but also enable many new features at a fraction of the cost of improved bandwidth and optimize many other legacy features. For example, conventional loopback recycling cannot support multiple copies. If multiple copies are required, the memory manager needs to be updated for multiple copies, at the expense of critical path bandwidth and introducing additional passes for the packet, which increases latency, adds complexity to the programming model, and places additional strain on the central processing unit.

[0017] In some embodiments, systems and methods make decisions for packet recirculation in ingress and egress pipelines. In some embodiments, the systems and methods provide a unified and consistent programming model for looping and recirculation, as well as a unified and consistent format for looping and recirculation. Recirculation triggered by the ingress pipeline can have multiple copies and different classes of service in a redirection buffer (RDB) for buffering and scheduling. In some embodiments, multiple copies of the same packet can be triggered simultaneously by the ingress and egress pipelines without any out-of-order processing. Unified packet recirculation can be efficiently used to generate and reinsert additional copies with any number of metadata bytes and custom headers for metering / telemetry applications. In some embodiments, a guaranteed improved bandwidth (BW) of 13.5 Gigabits per second (Gbps) can be achieved, compared to 2.7 Gbps for conventional packet recirculation schemes.

[0018] Some embodiments relate to a network device comprising: an ingress pipeline; an egress pipeline; an ingress data buffer having a recirculation port; and a recirculation data buffer coupled to the recirculation port. The egress pipeline and the ingress pipeline are configured to mark data packets for recirculation. The data packets are provided to the recirculation data buffer to be provided to the recirculation port, and the ingress data buffer is configured to provide the data packets to the ingress pipeline.

[0019] Some embodiments relate to a method for recirculating data packets. The method includes marking a first data packet for recirculation in an ingress pipeline; providing the first data packet to an egress pipeline; and providing the first data packet from the egress pipeline to an egress data buffer and providing a copy of the first data packet in the recirculating data buffer. The method also includes providing the copy of the first data packet from the recirculating data buffer to an ingress data buffer.

[0020] Some embodiments relate to an apparatus comprising: an ingress data buffer; an ingress processor; an egress processor; and a recirculation data buffer. The apparatus is configured to provide unified packet recirculation via the recirculation data buffer and a single recirculation port on the ingress data buffer.

[0021] Some embodiments relate to an apparatus comprising: an ingress data buffer; an ingress processor; an egress processor; and a recirculation data buffer. The recirculation buffer is configured to copy or edit a data packet and provide the copied or edited data packet to a recirculation port on the ingress data buffer.

[0022] In some embodiments, the egress pipeline is configured to provide edit instructions to the recirculating buffer. In some embodiments, the edit instructions include offset, update, data, or action instructions. In some embodiments, the recirculating data buffer is configured to form more than two copies of the data packet.

[0023] Network devices

[0024] refer to Figure 1 , an exemplary configuration of network 8 includes a network device 10. Network device 10 may be a hardware-based device, such as a network switch for moving data packets within network 8 based on address information contained within the data packets themselves. In some embodiments, network device 10 may additionally and / or alternatively perform the functions of a router and be configured to move data packets within and across a network, or generally be any other device configured to move data within or across a network. Additionally, although the present disclosure may sometimes refer to a "switch" and a "switch" for purposes of this description, the terms "switch" and "switch" may include both switching and routing.

[0025] In some embodiments, network device 10 is a network switch functionally connected to a central processing unit (CPU) 12 and other external devices 14. External devices 14 may be other external processors, external memory, other network devices (e.g., servers, routers, or computers), and / or other network switches, access points, and routers used to expand switching capabilities. CPU 12 may be used to program network device 10 based on desired rules or protocols for packet processing.

[0026] Data received at ports 24 from network devices 16, 18, 20, and 22 can be processed by network device 10 independently of CPU 12 based on programmed instructions. Based on programmed packet processing rules, the processed data is redistributed across ports 24 to the appropriate network devices 16, 18, 20, and 22. Network device 10 can be an integrated, modular, single-chip solution. In some embodiments, network device 10 includes an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a communications processor, or any other type and form of dedicated silicon logic or processing circuitry capable of processing and switching packets or other data units, configured according to packet processing rules. Additionally and / or alternatively, network device 10 can be multiple individual components on a circuit board, or implemented in software on a general-purpose device or multiple general-purpose devices.

[0027] Although the word "packet" is used, it should be understood that the disclosed processes can work with other types of data, including cells, frames, datagrams, bridge protocol data unit packets, packet data, etc. Packet processing can include reading, modifying, and classifying packets, changing packet forwarding behavior, removing and / or appending information to packets, mirroring packets to another port, storing packets in a buffer, reordering packets within a series of packets, sending packets to a service queue, recycling or looping back packets, or changing the type of packets. For example, network device 10 may replicate a packet and select a particular port among ports 24 as an egress port, which can then forward the packet to network device 10 or other devices 16, 18, 20, and 22 or networks. The egress port and ultimate network device destination are determined by the data contained in the packet. Forwarding a packet may involve switching the packet within network 8 to one or more egress ports of network device 10 (e.g., port 24). When forwarding, the packet may be replicated and sent to multiple destinations on a single egress port or across multiple egress ports. In some embodiments, the final data packet destination is a sequential network device, and the data packet is forwarded from network device 10 through a series of network devices before reaching the final destination.

[0028] The data packet contains information for duplicating the data packet and forwarding the data packet to the appropriate destination on the network. The data packet is initially received on a source port marked by network device 10, and the data packet can then be duplicated and forwarded to the same port or one or more other ports belonging to the multicast group indicated by the information contained in the data packet. In multicast, data packets marked as belonging to a multicast group are sent to the pre-determined destinations that have indicated to network device 10 that they belong to the multicast group. A single data packet can be duplicated and forwarded to multiple destinations without flooding the network, so that only a single data packet is transmitted to each destination.

[0029] Network device 10 includes an ingress pipeline 32, an egress pipeline 34, a unified recirculation module or circuit 36, and port 24. Ingress pipeline 32 processes packets received on port 24, and egress pipeline 34 processes packets for transmission from port 24. Unified recirculation circuit 36 provides recirculation decisions and processing for network device 10. Advantageously, unified recirculation circuit 36 can interact with and be part of both ingress pipeline 32 and egress pipeline 34 when reintroducing or recirculating packets. In some embodiments, packets can be reintroduced at ingress pipeline 32 based on decisions made at either ingress pipeline 32 or egress pipeline 34.

[0030] In some embodiments, unified recirculation circuitry 36 uses a unified and consistent programming model for loopback and egress recirculation, eliminating the need for additional, separate ports required for loopback and recirculation. Network device 10 supports multiple copies of recirculation for ingress pipeline triggering, as well as different classes of services for buffering and scheduling. In some embodiments, multiple copies of the same packet can be triggered simultaneously by ingress pipeline 32 and egress pipeline 34 without out-of-order processing issues. In some embodiments, if a flow does not use loopback logic and queues, the loopback logic and queues can be eliminated entirely. Ingress pipeline 32 can direct mirroring decisions to egress pipeline 34, which handles recirculation and mirroring operations.

[0031] refer to Figure 2 , portion 200 of network device 10 includes ingress pipeline 32, egress pipeline 34, memory management unit 204, ingress data buffer 250, egress data buffer 260, and redirection or recycling data buffer 270. In some embodiments, port 24 ( Figure 1) or a subset of the ports to provide portion 200. Portion 200 may include additional ingress data buffers (e.g., 1 or more) similar to ingress data buffer 250 and additional egress data buffers (e.g., 1 or more) similar to egress data buffer 260. In some embodiments, network device 10 includes 16 portions 200, each including one additional ingress buffer and one additional egress buffer. In some embodiments, ingress data buffer 250 and egress data buffer 260 each include connections to 10 front panel ports and one auxiliary or recirculation / loopback port. Five of the 32 ingress data buffers may include auxiliary ports for CPU 12 and management, while the remaining 26 ingress data buffers do not include auxiliary ports. Similarly, four of the 32 egress data buffers may include auxiliary ports for CPU 12 and management (e.g., Figure 4 436 in the output data buffers), while the 27 remaining output data buffers do not include the auxiliary port.

[0032] The ingress pipeline 32 includes a multiplexer 210, an ingress processing pipeline 212, and a multiplexer 214. The egress pipeline 34 includes a multiplexer 230, an egress processing pipeline 232, and a multiplexer 234. The ingress processing pipeline 212 is configured to perform packet processing before processing by the memory management unit 204, and the egress processing pipeline 232 is configured to perform packet processing after processing by the memory management unit 204. In some embodiments, the ingress packet processing operation includes determining where to send the packet from the network device 10 (to which ports 24 ( Figure 1 )).

[0033] Ingress port 292 is coupled to a first input of multiplexer 210, and ingress data buffer 250 is coupled to a second input of multiplexer 210 at ingress port 294. Ingress port 292 is coupled to a first output of multiplexer 214, and ingress port 294 is coupled to a second output of multiplexer 214. Egress port 286 is coupled to a first input of multiplexer 230 at an egress data processing output (EDPO), and egress port 288 is coupled to a second input of multiplexer 230 at an egress data processing output. Egress port 286 is coupled to a first output of multiplexer 234, and egress data buffer 260 is coupled to a second output of multiplexer 234 at egress port 288. Multiplexers 210, 214, 230, and 234 may be used to form paths through and around ingress processing pipeline 212 and egress processing pipeline 232.

[0034] Ingress port 294 is coupled to ingress data buffer 250, and port 288 is coupled to egress data buffer 260 and recycling data buffer 270. Port 286 is coupled to recycling data buffer 270. Port 292 may be coupled to one of the additional ingress data buffers, and port 286 may be coupled to one of the additional ingress data buffers.

[0035] The ingress data buffer 250 includes a queue or cell assembly unit 252. The recirculating data buffer 270 includes a recirculating queue 272 and a scheduler 276. The recirculating data buffer 270 includes a loopback queue 274. In some embodiments, the loopback queue 274 may be included in the recirculating queue 272, or the recirculating queue 272 may replace the loopback queue 274. The recirculating data buffer 270 is coupled to a recirculation port 282 and a credit signal line 284 of the ingress data buffer 250. The recirculating data buffer 270 is coupled to the recirculation port 282 of the ingress data buffer 250 and a credit signal line 284 between the recirculating data buffer 270 and the ingress data buffer 250. The recirculating data buffer 270 is coupled to the memory management unit 204 via a credit signal line 287. The recirculating data buffer 270 returns credits with a unit length from the egress processing pipeline 232 for dropped / truncated packets at the enqueue of the recirculating data buffer 270 and enqueued packets at the dequeue of the recirculating data buffer 270 .

[0036] The memory management unit 204 includes queue buffers 236 (e.g., eight egress queues). In some embodiments, the memory management unit 204 manages the transmission of data at line rate and handles congestion under varying and adverse traffic conditions without dropping packets. In some embodiments, the queue buffers 236 are used to track dequeue operations of the loopback queue 274 via credit lines 287. The memory management unit 204 performs network address translation (NAT), which redirects communication requests from one address and port number combination to another as packets traverse the network device 10. In some embodiments, the memory management unit 204 is configured to perform per-port thresholding.

[0037] After the ingress processing pipeline 212 completes performing ingress processing operations, the data packet is sent to the memory management unit 204 for packet buffering and from the memory management unit 204 to the egress processing pipeline 232 for egress processing. The ingress processing pipeline 212 and the egress processing pipeline 232 may include hardware components, memory devices, and processors for performing ingress and egress processing. The ingress processing pipeline 212 and the egress processing pipeline 232 may share processors and other components for performing ingress and egress processing operations, or may have different hardware and processor components. The egress processing operation may include forwarding the data packet out of the determined egress port of the network device 10.

[0038] The ingress processing pipeline 212 is configured to examine metadata associated with a data packet. In some embodiments, the ingress processing pipeline 212 stores a set of rules, each of which specifies a pattern and a set of actions. When examining a data packet, if a rule in the set of rules has a pattern that matches the metadata, then the set of actions specified in the rule has a matching pattern. The ingress processing pipeline 212 is configured to generate a system header (i.e., metadata) associated with the data packet. For example, the ingress header manager may generate a set of system headers for the data packet and append them to the data packet. Thus, these system headers are separate from the original data packet (i.e., the system headers are not included in the original data packet).

[0039] The egress processing pipeline 232 is configured to inspect metadata associated with a data packet. In some embodiments, the egress processing pipeline 232 stores a set of rules, each of which specifies a pattern and a set of actions. During inspection of a data packet, if a rule in the set of rules has a pattern that matches the metadata, then the set of actions specified in the rule has a matching pattern. The egress processing pipeline 232 is responsible for managing system headers associated with a data packet. For example, in some examples, the egress processing pipeline 232 may determine which system headers (if any) associated with a data packet will be preserved before sending the data packet out of the egress processing pipeline 232.

[0040] Portion 200 is configured for unified packet recirculation. In some embodiments, the microarchitecture for unified packet recirculation provides a 128B unit buffer per data path and seamless bandwidth sharing with recirculation port 282 (e.g., 13.3 Gigabits per second (Gbps) to 170.99 Gbps bandwidth for 64B packets and 64.35 Gbps to 316.7 Gbps bandwidth for packets greater than 294B). The microarchitecture for unified packet recirculation is configured such that portion 200 creates and reinserts the extra copies into ingress data buffer 250 via a single port (e.g., port 282). The extra copies may include any number of metadata bytes and / or custom headers. In some embodiments, the extra copies required for instrumentation, visibility, or debugging do not have to be generated by memory management unit 204 and do not have to be generated by CPU 12 ( Figure 1 ) back into the ingress pipeline 32. This aspect of some embodiments reduces the logic, processing, and bandwidth overhead of the memory management unit 204 and CPU 12 when generating, receiving, and reinserting the extra copies. In some embodiments, operations do not mix the critical path (for the memory management unit 204) with the slower path for the CPU 12, which causes significant latency. Unified packet recycling provides a non-critical path through hardware without the slow path latency and software processing overhead. Packets are not restricted by the standard CPU header format and do not have to adhere to the standard CPU header format to carry data from the egress pipeline 34 to the ingress pipeline 32. In some embodiments, since the packets do not pass through processing by the CPU 12, the custom header can have any number of metadata bytes.

[0041] In some embodiments, the egress processing pipeline 232 is configured to make recirculation decisions for both ingress and egress scheduled recirculation using the same or similar hardware in some embodiments. For example, packets for loopback may be marked by the ingress processing pipeline 212, and the egress processing pipeline 232 may provide such packets to the recirculation data buffer 270 in response to the marking. The marking may be a field in metadata or other information. If a packet needs to be mirrored or reprocessed by the ingress processing pipeline 212, the packet may be marked for recirculation. The egress processing pipeline 232 may similarly select packets for recirculation.

[0042] In some embodiments, the egress processing pipeline 232 may use the EPRC-Loopback header for flows that require a second pass in the ingress pipeline 32. Flows that do not require second-pass processing in the ingress pipeline 32 may use the Egress Pipeline Recycled Ingress Pipeline (EPRC-IP)-Byte Stream Model Header (SOBMH). In such examples, the ingress pipeline 32 treats the packet as a SOBMH without making any updates to the legacy SOBMH logic. The ingress switch state (Isw) copies the EPRC-IP-SOBMH header bytes to the bus that directly connects the ingress pipeline 32 to the egress pipeline 34 for use by the egress pipeline 34 in the second pass. In some embodiments, the loopback header is updated to map the new EPRC flow to it and to align it with the SOBMH / CPU-TX header. In some embodiments, this technique is less intrusive because the actual variable-length headers for the different flows are generated and consumed within the ingress pipeline 32 and egress pipeline 34 and are not exposed to the egress datapath output, ingress datapath input, software, or user by keeping the SOBMH / CPU-Tx headers the same or updating the loopback header (and all its EPRC-related subtypes) to be consistent. In some embodiments, the egress processing pipeline 232 continues to support the shaping interface for the loopback port (e.g., port 282). In some embodiments, port 282 never receives packets with an in-band flow analyzer entry. In some embodiments, this ensures that the shaping interface does not need to handle special cases.

[0043] A straight-through high-speed path can be provided from the egress packet modification stage in the egress pipeline 34. This saves another 302B+ control interface from the egress pipeline 34 to each datapath pair (e.g., 16 of them), thereby saving space and power in some embodiments. Only 64 bytes more need to pass through the 302B interface to the datapath, which does not need to be accessed by the egress field processor subsystem or access control logic.

[0044] In some embodiments, the recirculating data buffer 270 is configured to perform egress pipeline-specific packet modifications instead of the egress pipeline 34. By performing such modifications in the recirculating data buffer 270, a 302-byte bus across the egress pipeline 34 and across the data path is not required, thereby saving area / power. In some embodiments, the recirculating data buffer 270 performs any required modifications after dequeuing from the recirculating data buffer 270, thereby operating on a much smaller data width to reduce multiplexing / pipeline costs, and each recirculating data buffer 270 has only one logic instance instead of two (e.g., one for ingress and one for egress recirculation, thereby saving area and power). The recirculating data buffer 270 uses credit lines 284 and 287 to perform credit loop operations for dequeuing. In some embodiments, lines 284 and 287 are single conductors.

[0045] In some embodiments, the recirculating data buffer 270 always receives a tail timestamp, as it does for swap copies, and receives a maximum transmission unit (MTU) failure error indication on the control bus, which the recirculating data buffer 270 chooses to ignore or honor based on the control signal from the egress processing pipeline 232. In some embodiments, the recirculating data buffer 270 never has to fill a packet back to 64B, and inputs and outputs pre-stream analyzer entries. The start of a new packet occurs after dequeuing and modifying in the recirculating data buffer 270. In some embodiments, except for the first 16B of the loopback header, all other bytes, including the bytes of the extension header, are considered packet data.

[0046] In some embodiments, no interchange between the egress data buffer 260 and the recirculating data buffer 270 is required, and no changes are required to the packet shaping loop with the memory management unit 204. The egress data buffer 260 does not implement a credit recycling interface for loopback operations with the memory management unit 204, and advantageously does not require buffers / queues implemented for loopback operations as conventionally used.

[0047] The recirculating data buffer 270 uses a scheduler 276 to reserve space for loopback packets based on the credits used between the recirculating data buffer 270 and the memory management unit 204. The recirculating queue 272 is configured to perform programmable bandwidth allocation across EPRC packets and loopback packets. The scheduler 276 supports port 24 ( Figure 1 ) and sharing between EPRC and loopback flows. In some embodiments, multiple copies of each enqueued packet are supported (independently truncated at 1 unit, 2 units), or the entire packet is sent. In some embodiments, errors occurring on any unit are propagated to the start of packet (SOP) to facilitate fast reading and are discarded on dequeue, thereby preserving bandwidth. In some embodiments, the recirculation queue 272 supports configurable ignoring of maximum transmission unit (MTU) failures for each copy and provides service class support for input buffering and scheduling of the scheduler 276.

[0048] refer to Figure 3, a packet 302 received from port 286 is stored in a unit buffer 308, and a copy 304 from port 288 is stored in a unit buffer 318. The copy 304 is marked as reserved for loopback or recirculation. Copy logic 374 forms the copy 304 in the recirculation data buffer 270. In some embodiments, packet editing is performed using a packet editor 332. (See, for example, Table 1 below). The recirculation queue 272 includes a queue 322 and a queue 324 for storing pointer structures, grant context, packet counters, and head-of-line packet information. A scheduler 374 prioritizes and schedules transmissions (e.g., loopback, recirculation, and other contexts).

[0049] refer to Figure 4 , two packets 402 are provided for recirculation to the ingress data buffer 250 at port 282. In some embodiments, the ingress data buffer 250 includes a single cell queue and a cell assembly unit 252. All packets incoming on port 282 as loopback packets are stored in the ingress data buffer 250 according to the loopback scheme.

[0050] In some embodiments, the ingress data buffer 250 sees the 16B loopback header 408, and the variable-length header 410 is visible only to the ingress pipeline 32. The packet portion 420 is reconstructed by the recirculating data buffer 270 using instructions from the egress pipeline 34 (e.g., reconstructing the packet according to the meter protocol terms). Egress data processing output bytes greater than 190B and the end-of-packet (EOP) timestamp are carried intact (e.g., in portion 422). In some embodiments, the recirculating data buffer 270 ignores MTU check failures from the egress data processing output if indicated by the egress pipeline 34 based on a copy.

[0051] At port 286, packet 404 includes packet data 452 provided to egress data buffer 260. The packet from the egress data processing output is different from the packet in egress data buffer 260. The SOP and subsequent MOP / EOP unit copies at the egress data processing output are different from those at the recirculating data buffer 270. Packet 404 also includes portion 454, which includes additional data from the egress data processing output. The additional data includes data at the egress data processing input that was subjected to IFA deletion and not sent through the egress processing pipeline 232. IFA refers to the Instrumentation Protocol. Packet 404 includes portion 456, which includes the EOP timestamp added by the egress data processing output. Portion 458 of packet 404 includes the IFA MDATA header extracted from the packet at termination, which is not required by the egress data processing output or the egress data buffer 260. Portion 460 of data packet 404 contains the new 64MDATA from egress pipeline 34 for recirculating data buffer 270 to carry the header, copy / modify instructions.

[0052] At the ingress data buffer 250, the packet header uses one bit to indicate loopback or CPU transmission. The most significant byte of the internal header can be used to distinguish between SOBMH, CPU transmission, loopback, etc. At the output of the multiplexer 210, if the header is greater than 16B, it is overlaid on the data model header extending into the most significant bit.

[0053] According to some embodiments, portion 200 provides modifications as discussed below in Table 1. Unified Recirculation Circuit 36 ( Figure 1 ) or the egress processing pipeline 232, the scheduler 276, and the egress data buffer 260 may process the rules to implement the operations of Table 1 below. SEOP refers to the start and end of a packet, SOP refers to the start of a packet, EOP refers to the end of a packet, and MOP refers to the middle of a packet. CRC refers to a cyclic redundancy check. L1, L2, L3, and L4 refer to layers.

[0054] Table I - Unit Lengths and Modifications

[0055]

[0056]

[0057] The network device 10 may also include other components not shown. For example, the network device 10 may include an Ethernet port interface controller, a Gigabit port interface controller, an Internet port interface controller, and additional buffers.

[0058] Configuration of the exemplary embodiment

[0059] The construction and arrangement of the system and method as shown in various exemplary embodiments are only illustrative. Although only several embodiments are described in detail in the present disclosure, many modifications are possible (for example, changes in the method, parameter value, arrangement, etc. of port or destination number, data type, reinsertion, reintroduction, etc.). For example, the position of the element can be reversed or otherwise changed, and the connection between the elements can be direct or indirect so that there can be one or more intermediate elements connected between them, and the property or quantity of the discrete element or position can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present disclosure. According to alternative embodiments, the order or sequence of any process or method step can be changed or reordered. Without departing from the scope of the present disclosure, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments. For example, the embodiments of the present disclosure can be implemented by a single device and / or system, or implemented by a combination of independent devices and / or systems.

[0060] The present disclosure contemplates methods, systems, and program products for completing various operations on any machine-readable medium. The embodiments of the present disclosure may be implemented using existing computer processors, or implemented by a dedicated computer processor for an appropriate system incorporated for this purpose or another purpose, or implemented by a hard-wired system. Embodiments within the scope of the present disclosure include program products, which include machine-readable media for carrying machine-executable instructions or data structures or storing machine-executable instructions or data structures thereon. This machine-readable medium may be any available medium that can be accessed by a general-purpose or special-purpose computer or other machine with a processor. As an example, this machine-readable medium may include RAM, ROM, EPROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices, or any other media that can be used to carry or store desired program code in the form of machine-executable instructions or data structures and can be accessed by a general-purpose or special-purpose computer (i.e., ASIC or FPGA) or any other machine with a processor. Combinations of the foregoing are also included within the scope of machine-readable media. Machine-executable instructions include, for example, instructions and data that cause a general-purpose computer, a special-purpose computer, or a dedicated processing machine to perform a certain function or a group of functions.

[0061] Although the figures show a specific order of method steps, the order of the steps may vary from that depicted. Furthermore, two or more steps may be performed simultaneously or partially simultaneously. This variation will depend on the software and hardware systems selected and the designer's choice. All such variations are within the scope of this disclosure. Similarly, software implementations may be accomplished using standard programming techniques with rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps, and decision steps.

Claims

1. A network device comprising: Inlet pipeline; export pipelines; an ingress data buffer including a recirculation port; as well as a recirculation data buffer coupled to the recirculation port, wherein the egress pipeline and the ingress pipeline are configured to mark a data packet for recirculation, wherein the data packet is provided to the recirculation data buffer, wherein the recirculation data buffer is configured to simultaneously generate multiple copies of the data packet for different classes of service and provide the multiple copies of the data packet to the recirculation port, wherein the ingress data buffer is configured to provide the multiple copies of the data packet to the ingress pipeline.

2. The network device of claim 1, wherein the recirculation port is a single recirculation port for the ingress data buffer. The network device of claim 1 , wherein the network device is an integrated circuit device. The network device of claim 1 , wherein the recycling data buffer comprises a scheduler and a recycling queue. The network device of claim 4 , wherein the recycling data buffer comprises a loopback queue.

6. The network device according to claim 1, further comprising: An egress data buffer is coupled to the egress pipeline and the recirculation data buffer, the egress data buffer including a single auxiliary port.

7. The network device according to claim 1, further comprising: a memory management unit placed between the ingress pipeline and the egress pipeline and coupled to the recirculating data buffer through a second credit line, wherein the recirculating data buffer returns a credit of a unit length for a dropped / truncated packet at an enqueue of the recirculating data buffer and an enqueued packet at a dequeue of the recirculating data buffer.

8. The network device according to claim 1, further comprising: An additional ingress data buffer is coupled to the ingress pipeline, wherein the additional ingress data buffer does not include a recirculation port.

9. The network device according to claim 8, further comprising: an egress data buffer coupled to the egress pipeline and the recirculating data buffer, the egress data buffer comprising a single auxiliary port; and An additional egress data buffer is coupled to the egress pipeline, wherein the additional egress data buffer does not include an auxiliary port.

10. A method for recycling a data packet, the method comprising: marking a first data packet for recirculation in an ingress pipeline; providing the first data packet to an egress pipeline; providing the first data packet from the egress pipeline to an egress data buffer and providing a copy of the first data packet to a recycling data buffer; Generating, by the recirculating data buffer, a plurality of copies of the first data packet for different classes of services simultaneously; as well as The multiple copies of the first data packet are provided from the recirculation data buffer to a recirculation port of an ingress data buffer, the ingress data buffer coupled to the ingress pipeline.

11. The method of claim 10, wherein the ingress data buffer comprises a single recirculation port, and the multiple copies of the first data packet are provided on the single recirculation port.

12. The method according to claim 10, further comprising: marking a second data packet for recirculation in the outlet line; providing the second data packet from the egress pipeline to the egress data buffer and providing a copy of the second data packet to the recirculation data buffer; and The copy of the second data packet is provided from the recycling data buffer to the ingress data buffer.

13. The method of claim 12, wherein the ingress data buffer comprises a single recirculation port, and the copy of the second data packet is provided on the single recirculation port.

14. The method of claim 13, wherein the recycling data buffer comprises a scheduler and a recycling queue for the second data packet.

15. The method of claim 14, wherein the recycling data buffer comprises a loopback queue for the first data packet.

16. An apparatus comprising: Ingress data buffer; Entry handler; export processors; as well as A recirculating data buffer is provided, wherein the recirculating data buffer is configured to simultaneously generate multiple copies of a data packet for different classes of service and provide the multiple copies of the data packet to a single recirculating port on the ingress data buffer.

17. The apparatus of claim 16, wherein the ingress processor, the egress processor, the recirculating data buffer, and the ingress data buffer are placed on a single integrated circuit.

18. The apparatus of claim 16, further comprising: Unified packet recycling software comprising instructions stored on a non-transitory medium for configuring the device to provide the unified packet recycling.

19. The apparatus of claim 18, further comprising a memory management unit between the egress processor and the ingress processor, wherein the instructions reserve space for recycled data packets based on credits used between the memory management unit and the recycled data buffer.

20. The apparatus of claim 16, wherein the recycling data buffer comprises a scheduler configured to schedule the multiple copies of the data packet for different classes of service.

21. An apparatus comprising: Ingress data buffer; Entry handler; export processors; as well as A recirculating data buffer is configured to simultaneously generate multiple copies of a data packet for different classes of service and provide the multiple copies of the data packet to a recirculating port on the ingress data buffer.

22. The apparatus of claim 21, wherein the egress processor is configured to provide edit instructions to the recirculating data buffer.

23. The apparatus of claim 22, wherein the edit instructions comprise offset, update, data, or action instructions.

24. The apparatus of claim 21, wherein the recycling data buffer is configured to form more than two copies of the data packet.

Images