Method for preparing semiconductor structure

Abstract

The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure. The method for preparing the semiconductor structure includes the following steps: providing a semiconductor substrate; etching a plurality of first grooves spaced apart along a first direction in the semiconductor substrate, and etching a plurality of second grooves spaced apart along a second direction obliquely intersecting the first direction in the semiconductor substrate, wherein the plurality of first grooves and the plurality of second grooves separate a plurality of active columns arranged in an array in the semiconductor substrate, and the axial direction of the active columns is along a third direction; preparing bit lines and capacitors at opposite ends of the active columns, respectively; and preparing word lines on the side walls of the active columns. The preparation method can increase the arrangement density of the capacitors, or, if it is necessary to prepare the densest hexagonally arranged capacitors, it can also reduce the offset of the capacitors, thereby reducing the process difficulty and improving the yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is mostly used to temporarily store data. Currently, a storage unit in a dynamic random access memory generally includes a transistor and a capacitor controlled by the transistor.

[0003] Vertical channel array transistor (VCAT) can effectively improve the arrangement density of transistors, thereby improving the storage density of dynamic random access memory. However, when preparing capacitors on vertical channel array transistors, there is still a problem of low arrangement density. If the arrangement density of capacitors is to be increased, there will be problems of high difficulty in the preparation process and low yield. Summary of the invention

[0004] Based on this, in order to solve the problems in the above background technology and to improve the arrangement density of capacitors while reducing the manufacturing difficulty and improving the device yield, it is necessary to provide a method for preparing a semiconductor structure.

[0005] According to some embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, comprising the following steps:

[0006] providing a semiconductor substrate;

[0007] Etching a plurality of first grooves spaced apart from each other in a first direction in the semiconductor substrate, and etching a plurality of second grooves spaced apart from each other in a second direction obliquely intersecting the first direction in the semiconductor substrate, wherein the plurality of first grooves and the plurality of second grooves space a plurality of active pillars arranged in an array in the semiconductor substrate, wherein the axial direction of the active pillars is along a third direction, and both the first direction and the second direction are perpendicular to the third direction;

[0008] A bit line and a capacitor are respectively prepared at opposite ends of the active pillar, and the bit line and the capacitor are both electrically connected to the active pillar; and,

[0009] Word lines are formed on sidewalls of the active pillars.

[0010] In some embodiments of the present disclosure, the acute angle defined by the first direction and the second direction is 45° to 75°.

[0011] In some embodiments of the present disclosure, the plurality of active pillars include a plurality of first active pillar groups and a plurality of second active pillar groups, the active pillars in the first active pillar group and the active pillars in the second active pillar group are sequentially arranged along the second direction, and the first active pillar group and the second active pillar group are alternately arranged in a fourth direction perpendicular to the second direction;

[0012] Adjacent active pillars in the first active pillar group have a first central axis along the fourth direction, and adjacent active pillars in the second active pillar group have a second central axis along the fourth direction, and the first central axis does not overlap with the second central axis.

[0013] In some embodiments of the present disclosure, the capacitors are arranged in a hexagonal pattern.

[0014] In some embodiments of the present disclosure, the prepared bit lines include a first bit line group and a second bit line group, the bit lines in the first bit line group and the bit lines in the second bit line group are alternately arranged, the bit lines in the first bit line group are electrically connected to the active pillars in the first active pillar group, and the second bit line group is electrically connected to the active pillars in the second active pillar group.

[0015] In some embodiments of the present disclosure, each of the prepared bit lines extends along the fourth direction.

[0016] In some embodiments of the present disclosure, a bit line isolation layer is further disposed between adjacent bit lines.

[0017] In some embodiments of the present disclosure, the second trench etched includes first isolation trenches and second isolation trenches that are alternately arranged, the word line includes a gate structure, and at least a portion of the gate structure is prepared in the first isolation trench.

[0018] In some embodiments of the present disclosure, before preparing the gate structure, the first isolation trench is etched in the semiconductor substrate, and the steps of preparing the gate structure include:

[0019] filling a gate material layer in the first isolation trench;

[0020] The gate material layer in the first isolation groove is etched to form a gate material isolation groove penetrating the gate material layer, wherein the gate material isolation groove isolates the gate material layer into the gate structure.

[0021] In some of the embodiments of the present disclosure, the method further includes: preparing a first insulating dielectric layer and a second insulating dielectric layer in the first isolation trench;

[0022] The gate material layer is prepared between the first insulating dielectric layer and the second insulating dielectric layer.

[0023] In some embodiments of the present disclosure, after forming the gate material spacing groove, the method further includes: preparing a third insulating dielectric layer in the gate material spacing groove.

[0024] In some embodiments of the present disclosure, the step of etching the first trench is performed before filling the gate material layer, and in the step of filling the gate material layer in the first isolation trench, the gate material layer is also filled in the first trench;

[0025] After the gate material layer is filled in the first isolation trench, the method further includes: etching the second isolation trench in the semiconductor substrate.

[0026] In some embodiments of the present disclosure, the capacitor includes a lower electrode, a dielectric layer and an upper electrode, the lower electrode is electrically connected to the active column, the upper electrode is opposite to the lower electrode and is spaced apart from the lower electrode, and the dielectric layer is disposed between the upper electrode and the lower electrode.

[0027] In some embodiments of the present disclosure, before preparing the bit line, the method further includes: preparing a bit line contact on one end of the active pillar for connecting the bit line; and / or,

[0028] Before preparing the capacitor, the method further includes: preparing a capacitor contact on one end of the active pillar for connecting the bit line.

[0029] In some embodiments of the present disclosure, the step of preparing the bit line contact includes: preparing a first metal layer on the active pillar, sintering a portion of the first metal layer and a portion of the active pillar to form a first metal compound layer, the bit line contact including the first metal compound layer and a portion of the first metal layer;

[0030] The step of preparing the capacitor contact includes: preparing a second metal layer on the active column, sintering part of the second metal layer and part of the active column to form a second metal compound layer, and the capacitor contact includes the second metal compound layer and part of the second metal layer.

[0031] On the other hand, according to some embodiments of the present disclosure, a semiconductor structure is further provided, wherein the semiconductor structure is prepared by the method for preparing the semiconductor structure described in any of the above embodiments.

[0032] In traditional technology, for vertical channel array transistors, capacitors are usually arranged in a square on them, that is, the four capacitors determined by two adjacent word lines and two adjacent bit lines occupy the four vertices of the square respectively. However, this arrangement is not the densest arrangement. The cross-sectional area of ​​the capacitors arranged in this way needs to be further improved, and correspondingly, their capacitance also needs to be further improved. If the capacitors are arranged in a hexagonal close-packed manner, it will inevitably cause the capacitors to shift to both sides relative to the corresponding active area. However, when the capacitors are offset relative to the active area, not only will the process difficulty increase significantly, but it will also lead to a decrease in product yield.

[0033] The present disclosure adopts the concept of directly changing the arrangement of active pillars to solve the above-mentioned problems. Specifically, by etching the first groove and the second groove in the first direction and the second direction that are obliquely intersecting, respectively, the active pillars prepared in this way are arranged in an array in the two obliquely intersecting directions. When preparing capacitors on the active pillars, if the capacitors are prepared according to the arrangement of the active pillars, the arrangement density of the capacitors can be increased relative to the tetragonal arrangement. If it is necessary to prepare the densest hexagonal arrangement of capacitors, the offset of the capacitors can also be reduced, thereby reducing the process difficulty and improving the yield. More importantly, the present disclosure can obtain the required active pillars only by etching in two intersecting directions, which greatly simplifies the difficulty of preparing active pillars that are not arranged tetragonally.

[0034] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of the steps of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0037] Figure 2 A semiconductor substrate is shown in which a plurality of first trenches spaced apart from each other are etched;

[0038] Figure 3 Shows Figure 2 A schematic cross-sectional view of the structure shown along the AA' direction;

[0039] Figure 4 Shown in Figure 2A first isolation groove structure is further etched on the basis of the structure shown;

[0040] Figure 5 Shows Figure 4 A schematic cross-sectional view of the structure shown along the AA' direction;

[0041] Figure 6 Shown in Figure 4 A structure of filling a gate material layer based on the structure shown;

[0042] Figure 7 Shows Figure 6 A schematic cross-sectional view of the structure shown along the AA' direction;

[0043] Figure 8 Shown in Figure 6 On the basis of the structure shown, a gate material layer is etched and a second isolation groove structure is formed;

[0044] Fig. 9 Shows Figure 8 A schematic cross-sectional view of the structure shown along the AA' direction;

[0045] Fig.10 Shown in Figure 8 A structure of a third insulating dielectric layer is prepared based on the structure shown;

[0046] Fig.11 Shows Fig.10 A schematic cross-sectional view of the structure shown along the AA' direction;

[0047] Fig.12 Shown in Fig.10 A schematic diagram of a structure for preparing a bit line based on the structure shown;

[0048] Fig.13 Shown in Fig.12 A schematic diagram of a capacitor structure prepared based on the structure shown;

[0049] Fig.14 Shows Fig.13 a top view of the structure shown;

[0050] The reference numerals and their meanings are as follows:

[0051] 110, semiconductor substrate; 101, first trench; 1021, first isolation trench; 1022, second isolation trench; 111, active pillar; 1111, first active pillar group; 1112, second active pillar group; 120, gate material layer; 121, gate structure; 1201, gate material spacing groove; 131, first insulating dielectric layer; 132, second insulating dielectric layer; 133, third insulating dielectric layer; 140, bit line; 150, bit line contact; 160, bit line isolation layer; 170, capacitor; 171, lower electrode; 172, dielectric layer; 173, upper electrode. DETAILED DESCRIPTION

[0052] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0054] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. The manner of electrical connection is used to indicate that current can be conducted between multiple electrically connected elements, and the specific manner may be that one element directly contacts another element, or that one element is connected to another element through other conductive elements. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0055] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] In conventional technology, for vertical channel array transistors, capacitors are usually arranged in a square on them, that is, four capacitors determined by two adjacent word lines and two adjacent bit lines occupy the four vertices of the square respectively. However, this arrangement is not the densest arrangement. The cross-sectional area of ​​the capacitors arranged in this way needs to be further improved, and correspondingly, their capacitance also needs to be further improved.

[0058] On this basis, the densest hexagonal arrangement can be achieved by offsetting the capacitors to both sides relative to the corresponding active areas. However, when the capacitors are offset relative to the active areas, not only will the process difficulty increase significantly, but also the product yield will decrease.

[0059] In order to solve the above problem, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which comprises the following steps:

[0060] providing a semiconductor substrate;

[0061] Etching a plurality of first trenches spaced apart from each other in a first direction in a semiconductor substrate, and etching a plurality of second trenches spaced apart from each other in a second direction obliquely intersecting the first direction in the semiconductor substrate, wherein the plurality of first trenches and the plurality of second trenches separate a plurality of active pillars arranged in an array in the semiconductor substrate, wherein the active pillars extend along a third direction, and both the first direction and the second direction are perpendicular to the third direction;

[0062] preparing a bit line and a capacitor at opposite ends of the active pillar, respectively, the bit line and the capacitor are both electrically connected to the active pillar; and,

[0063] Word lines are formed on sidewalls of the active pillars.

[0064] The present disclosure adopts the concept of directly changing the arrangement of active pillars to solve the above-mentioned problems. Specifically, by respectively etching a first groove and a second groove in a first direction and a second direction that are obliquely intersecting, the active pillars prepared in this way are arranged in an array in two obliquely intersecting directions. When preparing capacitors on the active pillars, if the capacitors are prepared according to the arrangement of the active pillars, the arrangement density of the capacitors can be increased relative to the square arrangement. If the capacitors are arranged in a hexagonal close-packed manner, it is inevitable that the capacitors will be offset to both sides relative to the corresponding active area. However, when the capacitors are offset relative to the active area, not only will the process difficulty be significantly increased, but the product yield will also be reduced.

[0065] It is understood that the specific formation timing of the first trench, the second trench, the word line, the bit line and the capacitor in the method for preparing the semiconductor structure disclosed in the present invention may be different from the order described, and the technicians may reasonably arrange the specific preparation order in combination with the prior art. For example, the word line may be prepared first, and then the bit line and the capacitor may be prepared. For another example, the word line may also be formed during the process of etching the first trench and the second trench.

[0066] In order to facilitate understanding of the method for preparing the semiconductor structure in the above embodiment, Figure 1 A schematic diagram of one of the preparation steps of the preparation method of the semiconductor structure is also provided. Figure 1 As shown, the method for preparing the semiconductor structure includes steps S1 to S5.

[0067] Step S1, providing a semiconductor substrate, etching a plurality of first trenches spaced apart from each other along a first direction, and etching a plurality of first isolation trenches spaced apart from each other along a second direction.

[0068] Figure 2 FIG. 1 shows a semiconductor substrate 110 having a plurality of first trenches 101 spaced apart from each other. Figure 2 In the directions shown in , the y direction is the second direction, the z direction is the third direction, and the x direction is the fourth direction. The second direction, the third direction, and the fourth direction are perpendicular to each other.

[0069] In some examples of this embodiment, the material of the semiconductor substrate 110 may include one or more of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide. In this embodiment, the material of the semiconductor substrate 110 includes silicon. The semiconductor substrate 110 is used to prepare the subsequent active pillar 111. Therefore, the semiconductor substrate 110 may also contain a semiconductor doped with a specific type. The doping type may be N-type and P-type, and optionally, the N-type doping element may be one or more of nitrogen, phosphorus, and arsenic. The P-type doping element may be one or more of boron, aluminum, and gallium. Doping may be completed before etching the semiconductor substrate 110.

[0070] Reference Figure 2 As shown, the plurality of first grooves 101 all extend along the first direction, so the plurality of first grooves 101 are arranged in parallel. The plane defined by the second direction and the fourth direction is parallel to the first direction. The extension direction of the first groove 101 refers to the extension direction of the cross section of the first groove 101, and the cross section of the first groove 101 is perpendicular to the direction from the notch to the bottom of the groove. In this embodiment, the direction from the notch to the bottom of the groove is the third direction. It can be understood that the arrangement direction of the plurality of first grooves 101 is perpendicular to the first direction and the third direction.

[0071] Figure 3 Shows Figure 2 A schematic cross-sectional view of the structure shown along the AA' direction. Figure 3 As shown, the first direction is the w direction. The first direction and the second direction are obliquely intersected, and adjacent first trenches 101 are spaced apart by the semiconductor substrate 110 .

[0072] Among them, "oblique intersection" means that the acute angle determined by the first direction and the second direction is greater than 0 degrees and less than 90 degrees. In some examples of this embodiment, the acute angle determined by the first direction and the second direction is greater than 30° and less than 90°. The acute angle determined by the first direction and the second direction is 45° to 75°. Further optionally, the acute angle determined by the first direction and the second direction is 60°. When the acute angle determined by the first direction and the second direction is 60°, the subsequently formed active column 111 array can be directly arranged in a hexagonal manner, thereby minimizing the offset required for the capacitor 170 to be hexagonally closely packed.

[0073] In some examples of this embodiment, the first trench 101 may be etched by dry etching using plasma.

[0074] In some examples of this embodiment, the widths of the first trenches 101 are equal, and the intervals between adjacent first trenches 101 are also equal.

[0075] Figure 4 Shown in Figure 2 The structure of the first isolation groove 1021 is further etched on the basis of the structure shown. Figure 4 As shown, the first isolation groove 1021 extends along the second direction, the direction from the groove opening to the groove bottom of the first isolation groove 1021 is also the third direction, and the arrangement direction of the plurality of first isolation grooves 1021 is perpendicular to the second direction and the third direction. For example, the plurality of first isolation grooves 1021 are arranged in sequence in the fourth direction.

[0076] Figure 5 Shows Figure 4 A schematic cross-sectional view of the structure shown along the AA' direction. Figure 5 As shown, the first isolation trench 1021 is arranged to intersect with the first trench 101. The angle between the first isolation trench 1021 and the first trench 101 is the angle between the first direction and the second direction.

[0077] In some examples of this embodiment, the widths of the first isolation trenches 1021 are equal, and the intervals between adjacent first isolation trenches 1021 are also equal.

[0078] Step S2 , filling the first isolation trench 1021 with a gate material layer 120 .

[0079] Figure 6 Shown in Figure 4 The structure shown in FIG. 1 is a structure filled with a gate material layer 120. Figure 6 As shown, the gate material layer 120 is filled in each first isolation trench 1021. Moreover, in some examples of this embodiment, the gate material layer 120 is also filled in each first trench 101. It can be understood that the first trench 101 is used to separate the active pillar 111, and the gate material layer 120 is used to prepare the gate structure 121. Therefore, filling the gate material layer 120 in the first trench 101 is conducive to forming the gate structure 121 on the sidewall of the active pillar 111 close to the first trench 101 prepared later, and is also conducive to expanding the area of ​​the channel region.

[0080] Optionally, the gate material layer 120 may include a conductive material, for example, the gate material layer 120 may include one or more of titanium, silver, gold, and tungsten.

[0081] In some examples of this embodiment, before filling the gate material layer 120, the process may further include: etching the semiconductor substrate 110 exposed in the first trench 101 and the first isolation trench 1021. Etching the exposed semiconductor substrate 110 can make the corners of the semiconductor substrate 110 smoother.

[0082] In some examples of this embodiment, before filling the gate material layer 120, the step of preparing a gate dielectric layer (not shown) on the semiconductor substrate 110 may be further included. Optionally, the material of the gate dielectric layer may be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer may be formed by depositing the material of the gate dielectric layer on the surface of the semiconductor substrate 110, or by oxidizing the semiconductor substrate 110 to obtain the material of the gate dielectric layer.

[0083] In some examples of this embodiment, the gate material layer 120 may be formed only in a portion of the first isolation trench 1021. Figure 6 As shown, before preparing the gate material layer 120, it also includes: a step of preparing a first insulating dielectric layer 131 in the first isolation groove 1021, and after preparing the gate material layer 120, it also includes: a step of preparing a second insulating dielectric layer 132 in the first isolation groove 1021 on the gate material layer 120. It can be understood that the first insulating dielectric layer 131 is located below the gate material layer 120, and the second insulating dielectric layer 132 is located above the gate material layer 120. In some examples of this embodiment, the second insulating dielectric layer 132 is flush with the notch of the first isolation groove 1021. Further, in some examples of this embodiment, the steps of preparing the first insulating dielectric layer 131 and preparing the second insulating dielectric layer 132 are also performed in the first trench 101.

[0084] Optionally, the first insulating dielectric layer 131 and the second insulating dielectric layer 132 are each independently selected from one or more of silicon nitride, silicon oxide and silicon oxynitride. The first insulating dielectric layer 131 and the second insulating dielectric layer 132 may be made of the same material.

[0085] Figure 7 Shows Figure 6 A schematic cross-sectional view of the structure shown along the AA' direction. Figure 7 As shown, the gate material layer 120 fills up the first trench 101 and the first isolation trench 1021 in the width direction.

[0086] Step S3 , etching the gate material layer 120 in the first isolation trench 1021 , and etching out the second isolation trench 1022 .

[0087] Figure 8 Shown in Figure 6 Based on the structure shown in FIG. 1 , the gate material layer 120 is etched to form a structure of a second isolation trench 1022. Figure 8As shown, the gate material layer 120 in the first isolation trench 1021 is etched from the top of the gate material layer 120 to the bottom of the gate material layer 120 to form a gate material spacing trench 1201 penetrating the gate material layer. The gate material spacing trench 1201 separates the gate material layer 120 in the first isolation trench 1021 into gate structures 121 that contact the semiconductor substrate 110 on both sides of the first isolation trench 1021.

[0088] In this embodiment, the step of etching the second isolation trench 1022 between adjacent first isolation trenches 1021 along the second direction is also included. Figure 8 As shown, a second isolation groove 1022 is also formed, and the etched first isolation groove 1021 and the second isolation groove 1022 are alternately arranged, and the first isolation groove 1021 and the second isolation groove 1022 are parallel to each other, and the first isolation groove 1021 and the second isolation groove 1022 together constitute a second groove. The first groove 101 and the second groove separate a plurality of active pillars 111 arranged in an array in the semiconductor substrate 110. The axial direction of the active pillar 111 is along the third direction.

[0089] It can be understood that the active pillar 111 has source and drain regions at both ends and a channel region between the source and drain regions.

[0090] In some examples of this embodiment, etching the second isolation trench 1022 may be performed simultaneously with etching the gate material layer 120 , or may be performed before or after the step of etching the gate material layer 120 .

[0091] In this embodiment, the gate material layer 120 is formed first and then the second isolation groove 1022 is etched, so that the gate material layer 120 filled in the first trench 101 can be cut off while the active pillar 111 is formed to obtain spaced word lines.

[0092] In some examples of this embodiment, the widths of the second isolation trenches 1022 are equal, and the distances between adjacent second isolation trenches 1022 are also equal.

[0093] Fig. 9 Shows Figure 8 A schematic cross-sectional view of the structure shown along the AA' direction. Fig. 9 As shown, the second isolation trench 1022 does not have a gate structure 121 . The gate structure 121 is located on the sidewall of the active pillar 111 close to the first isolation trench 1021 , and the gate structure 121 is also located on the sidewall of the active pillar 111 close to the first trench 101 .

[0094] Reference Fig. 9As shown, in some examples of this embodiment, the plurality of active pillars 111 include a plurality of first active pillar groups 1111 and a plurality of second active pillar groups 1112, the active pillars 111 in the first active pillar group 1111 and the active pillars 111 in the second active pillar group 1112 are sequentially arranged along the second direction, and the first active pillar group 1111 and the second active pillar group 1112 are alternately arranged in a fourth direction perpendicular to the second direction. Fig. 9 It can be understood that the first active pillar group 1111 has the first isolation trench 1021 and the second isolation trench 1022 on both sides, and the second active pillar group 1112 also has the first isolation trench 1021 and the second isolation trench 1022 on both sides.

[0095] Among them, there is a first central axis L1 between two adjacent active columns 111 in the first active column group 1111, and there is a second central axis L2 between two adjacent active columns 111 in the second active column group 1112, and the first central axis L1 does not overlap with the second central axis L2. Further optionally, the first central axis L1 passes through the active column 111 in the second active column group 1112, and the second central axis L2 passes through the active column 111 in the first active column group 1111. It can be understood that since the first central axis L1 and the second central axis L2 do not overlap, the offset required to form a hexagonal close-packed capacitor can also be reduced accordingly. Optionally, the first central axis L1 is located in the middle between adjacent second central axes L2, and the second central axis L2 is also located in the middle of the adjacent first central axis L1.

[0096] In some examples of this embodiment, the active pillars 111 array is arranged in a hexagonal pattern. Fig. 9 As shown, a central active pillar 111 is adjacent to six active pillars 111, and the central active pillar 111 occupies the center of a regular hexagon, and the six adjacent active pillars 111 occupy the six vertices of the regular hexagon respectively. By directly arranging the active pillars 111 in a hexagonal pattern, the capacitor 170 can be arranged in the densest hexagonal pattern without offsetting, which significantly reduces the process difficulty.

[0097] It can be understood that through step S3, the active pillar 111 and the gate structure 121 disposed on the sidewall of the active pillar 111 can be formed. In addition, the gate structures 121 adjacent to each other in the second direction are interconnected, and the interconnected gate structures 121 as a whole can be used as word lines, or a conductive material connecting the gate structures 121 in the second direction can be further prepared to form a word line together with the prepared gate structures 121.

[0098] In conventional technology, each word line is usually prepared separately. Since the size of a single word line is small, the process difficulty of exposure is also high. In steps S2 to S3 of this embodiment, the gate material layer 120 is first filled in the first isolation groove 1021, and then the gate material layer 120 is separated into gate structures 121 located on both sides, which can greatly simplify the process difficulty of the gate structure 121.

[0099] In some examples of this embodiment, after forming the second isolation trench 1022 , the process further includes: filling the second isolation trench 1022 with a third insulating dielectric layer 133 . Fig.10 Shown in Figure 8 The structure of the third insulating dielectric layer 133 is prepared on the basis of the structure shown. Fig.11 Shows Fig.10 Schematic diagram of the cross section along the AA' direction of the structure shown.

[0100] Reference Fig.10 and Fig.11 As shown, the third insulating dielectric layer 133 is filled in the second isolation trench 1022. The third insulating dielectric layer 133 in the second isolation trench 1022 separates adjacent active pillars 111 to form a transistor with a single-sided channel structure, which is beneficial to improving the leakage of the transistor.

[0101] Optionally, the third insulating dielectric layer 133 is also filled in the gate material spacing groove 1201 to insulate and space the gate structures 121 on both sides of the gate material spacing groove 1201 .

[0102] The material of the third insulating dielectric layer 133 may be the same as or different from the material of the first insulating dielectric layer 131. In this embodiment, the material of the third insulating dielectric layer 133 includes silicon oxide.

[0103] Step S4 , preparing a bit line 140 at one end of the active pillar 111 .

[0104] Fig.12 Shown in Fig.10 A schematic diagram of the structure of preparing the bit line 140 based on the structure shown in FIG. Fig.12 As shown, the bit line 140 may be formed at the bottom end of the active pillar 111 , and the bit line 140 is electrically connected to the active pillar 111 .

[0105] Optionally, the step of preparing the bit line 140 includes: preparing a bit line 140 barrier layer and a bit line 140 conductive layer stacked in sequence in a direction away from the active pillar 111. The material of the bit line 140 barrier layer may include one or more of titanium and titanium nitride. The material of the bit line 140 conductive layer may include a metal, such as one or more of silver, gold and tungsten.

[0106] In some examples of this embodiment, the prepared bit line 140 includes a first bit line group and a second bit line group. The first bit line group is electrically connected to the active pillars 111 in the first active pillar group 1111, and the second bit line group is electrically connected to the active pillars 111 in the second active pillar group 1112. Fig.12 As shown, a row of active pillars 111 arranged along the second direction and exposed on the front side is a first active pillar group 1111, and a row of active pillars 111 arranged along the second direction and not exposed after the first active pillar group 1111 is a second active pillar group 1112. A first bit line group is electrically connected to the active pillars 111 in the exposed first active pillar group 1111, and a second bit line group is electrically connected to the active pillars 111 in the unexposed second active pillar group 1112. The bit lines 140 of the first bit line group and the bit lines 140 of the second bit line group are alternately arranged.

[0107] Reference Fig.12 As shown, in some examples of this embodiment, the second bit line group is in a straight line shape extending along the fourth direction.

[0108] Reference Fig.12 As shown, a bit line contact 150 is also prepared between the bit line 140 and the active pillar 111. In some examples of this embodiment, before preparing the bit line 140, the step of preparing the bit line contact 150 on one end of the active pillar 111 for connecting the bit line 140 is also included.

[0109] In some examples of this embodiment, the step of preparing the bit line contact 150 includes: preparing a first metal layer on the active pillar 111, sintering part of the first metal layer and part of the active pillar 111 to form a first metal compound layer, and the bit line contact 150 includes the first metal compound layer and part of the first metal layer.

[0110] Optionally, the first metal layer may include one or more of nickel, cobalt and titanium. Correspondingly, the first metal compound layer may also include one or more of nickel silicide, cobalt silicide and titanium silicide.

[0111] Reference Fig.12 As shown, a bit line isolation layer 160 is also prepared between adjacent bit lines 140. The bit line isolation layer 160 is used to insulate and space adjacent bit lines 140 to prevent signal crosstalk. Optionally, the material of the bit line isolation layer 160 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the bit line isolation layer 160 is silicon nitride.

[0112] Furthermore, the bit line isolation layer 160 is also disposed on a side of the bit line 140 away from the active pillar 111 .

[0113] In step S5 , a capacitor 170 is prepared at the other end of the active pillar 111 .

[0114] Fig.13 Shown in Fig.12 The structure diagram of the capacitor 170 is prepared based on the structure shown in FIG. Fig.13 As shown, the capacitor 170 is prepared at the top of the active pillar 111. It can be understood that the capacitor 170 corresponds to the active pillar 111 one by one, and each active pillar 111 is prepared with a corresponding capacitor 170 electrically connected thereto.

[0115] In some examples of this embodiment, capacitor 170 includes lower electrode 171, dielectric layer 172 and upper electrode 173. Lower electrode 171 is electrically connected to active pillar 111, upper electrode 173 is opposite to lower electrode 171 and spaced apart, and dielectric layer 172 is disposed between upper electrode 173 and lower electrode 171.

[0116] The material of the lower electrode 171 and the upper electrode 173 may be a conductive material. Optionally, the material of the upper electrode 173 and the lower electrode 171 are independently selected from one or more of copper, aluminum, silver, gold, titanium and tungsten.

[0117] The dielectric layer 172 insulates and separates the upper electrode 173 and the lower electrode 171. Optionally, the material of the dielectric layer 172 may be selected from one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0118] In some examples of this embodiment, the upper electrodes 173 of the plurality of capacitors 170 may be interconnected so that all the upper electrodes 173 have the same potential. In actual operation, it is only necessary to control the corresponding lower electrodes 171 to be charged or discharged through the active pillars 111 .

[0119] In some examples of this embodiment, a capacitor contact (not shown) may be provided between the active pillar 111 and the capacitor 170 . The capacitor contact is electrically connected to the active pillar 111 and the capacitor 170 to enhance the conductivity and adhesion between the capacitor 170 and the active pillar 111 .

[0120] The step of preparing the capacitor contact may be performed before the step of preparing the capacitor 170. Optionally, the step of preparing the capacitor contact includes: preparing a second metal layer on the active pillar 111, sintering a portion of the second metal layer and a portion of the active pillar 111 to form a second metal compound layer, and the capacitor contact includes the second metal compound layer and a portion of the second metal layer.

[0121] The second metal layer may include one or more of nickel, cobalt and titanium. Correspondingly, the second metal compound layer may also include one or more of nickel silicide, cobalt silicide and titanium silicide.

[0122] Fig.14 Shows Fig.13To facilitate understanding of the relative positions of capacitor 170, active pillar 111, word line and bit line 140 in the structure, Fig.14 Omitted Fig.13 A first insulating dielectric layer 131, a second insulating dielectric layer 132 and a third insulating dielectric layer 133 filled between the active pillars 111, and, Fig.14 Also omitted Fig.13 The bit line contact 150 and the bit line isolation layer 160 are formed in the embodiment of the present invention.

[0123] Reference Fig.14 As shown, the cross-section of capacitor 170 may be circular.

[0124] Reference Fig.14 As shown, in some examples of this embodiment, the capacitors 170 are arranged in a hexagonal pattern. For example, a central capacitor 170 is surrounded by six adjacent capacitors 170, the central capacitor 170 occupies the center of a regular hexagon, and the six adjacent capacitors 170 respectively occupy the six vertices of the regular hexagon. The hexagonal arrangement of the capacitors 170 is the densest arrangement, which can make full use of the limited space on the semiconductor substrate 110 and obtain the highest possible capacitance.

[0125] It can be understood that traditional active columns are usually arranged in an array in two directions perpendicular to each other, that is, a square arrangement. If the capacitor is prepared according to the arrangement of the active columns, the capacitor is arranged in a square, and the arrangement density of this arrangement is low. Although hexagonal capacitors can also be prepared on the square-arranged active columns, this requires a large degree of offset of the center of the capacitor relative to the center of the active column, resulting in a higher process difficulty and a lower yield.

[0126] The preparation method provided by the present disclosure adopts the concept of directly changing the arrangement of active pillars to solve the above-mentioned problems. Specifically, by respectively etching the first groove and the second groove in the first direction and the second direction that are obliquely intersecting, the active pillars prepared in this way are arranged in an array in the two obliquely intersecting directions. When preparing capacitors on the active pillars, if the capacitors are prepared according to the arrangement of the active pillars, the arrangement density of the capacitors can be increased relative to the tetragonal arrangement. If it is necessary to prepare the densest hexagonal arrangement of capacitors, the offset of the capacitors can also be reduced, thereby reducing the process difficulty and improving the yield. More importantly, the present disclosure can obtain the required active pillars only by etching in two intersecting directions, which greatly simplifies the difficulty of preparing active pillars that are not arranged tetragonally.

[0127] It can be understood that the array region of the semiconductor structure can be prepared by the preparation method including the above steps S1 to S5. The array region of the semiconductor structure usually needs to be electrically connected to the peripheral circuit to lead out the signal. Usually, the capacitor and the bit line need to be electrically connected to the peripheral circuit.

[0128] In a semiconductor structure of this embodiment, the bit line can be prepared on the front side or the back side of the semiconductor substrate. Optionally, the prepared bit line can be exposed from the front side or the back side of the semiconductor substrate to reduce the process difficulty of leading out the bit line. Optionally, the peripheral circuit can also be prepared on the front side or the back side of the semiconductor substrate and prepared on the same side as the bit line. For example, if the bit line is prepared on the front side of the semiconductor substrate, the peripheral circuit is also prepared on the front side of the semiconductor substrate; if the bit line is prepared on the back side of the semiconductor substrate, the peripheral circuit is also prepared on the back side of the semiconductor substrate to further reduce the process difficulty of the lead.

[0129] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0130] It should be understood that, unless otherwise clearly stated herein, the execution of the steps of is not strictly limited in order, and these steps may be executed in other orders. Moreover, at least a portion of the steps of may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0131] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: providing a semiconductor substrate; Etching a plurality of first grooves spaced apart from each other in a first direction in the semiconductor substrate, and etching a plurality of second grooves spaced apart from each other in a second direction obliquely intersecting the first direction in the semiconductor substrate, wherein the plurality of first grooves and the plurality of second grooves space a plurality of active pillars arranged in an array in the semiconductor substrate, wherein the axial direction of the active pillars is along a third direction, and both the first direction and the second direction are perpendicular to the third direction; A bit line and a capacitor are respectively prepared at opposite ends of the active pillar, and the bit line and the capacitor are both electrically connected to the active pillar; and, preparing word lines on sidewalls of the active pillars; The plurality of active pillars include a plurality of first active pillar groups and a plurality of second active pillar groups, the active pillars in the first active pillar group and the active pillars in the second active pillar group are sequentially arranged along the second direction, and the first active pillar group and the second active pillar group are alternately arranged in a fourth direction perpendicular to the second direction; Adjacent active pillars in the first active pillar group have a first central axis along the fourth direction, adjacent active pillars in the second active pillar group have a second central axis along the fourth direction, and the first central axis does not overlap with the second central axis; Wherein, the capacitors are arranged in a hexagonal pattern.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The acute angle determined by the first direction and the second direction is 45°~75°.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The prepared bit lines include a first bit line group and a second bit line group, the bit lines in the first bit line group and the bit lines in the second bit line group are alternately arranged, the bit lines in the first bit line group are electrically connected to the active pillars in the first active pillar group, and the second bit line group is electrically connected to the active pillars in the second active pillar group.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: Each of the prepared bit lines extends along the fourth direction.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: A bit line isolation layer is also arranged between adjacent bit lines.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The second etched trenches include first isolation trenches and second isolation trenches that are alternately arranged, and the word line includes a gate structure, at least a portion of the gate structure is prepared in the first isolation trenches.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: Before preparing the gate structure, the first isolation groove is etched in the semiconductor substrate. The steps of preparing the gate structure include: filling a gate material layer in the first isolation trench; The gate material layer in the first isolation groove is etched to form a gate material isolation groove penetrating the gate material layer, wherein the gate material isolation groove isolates the gate material layer into the gate structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Also includes: preparing a first insulating dielectric layer and a second insulating dielectric layer in the first isolation trench; The gate material layer is prepared between the first insulating dielectric layer and the second insulating dielectric layer.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that: After forming the gate material spacing groove, the method further includes: preparing a third insulating dielectric layer in the gate material spacing groove.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that: The step of etching the first trench is performed before filling the gate material layer, and in the step of filling the gate material layer in the first isolation trench, the gate material layer is also filled in the first trench; After the gate material layer is filled in the first isolation trench, the method further includes: etching the second isolation trench in the semiconductor substrate.

11. The method for preparing a semiconductor structure according to any one of claims 1 to 5 and 7 to 10, characterized in that: The capacitor includes a lower electrode, a dielectric layer and an upper electrode. The lower electrode is electrically connected to the active pillar. The upper electrode is opposite to the lower electrode and is spaced apart from the lower electrode. The dielectric layer is disposed between the upper electrode and the lower electrode.

12. The method for preparing a semiconductor structure according to any one of claims 1 to 5 and 7 to 10, characterized in that: Before preparing the bit line, the method further includes: preparing a bit line contact on one end of the active pillar for connecting the bit line; and / or, Before preparing the capacitor, the method further includes: preparing a capacitor contact on one end of the active pillar for connecting the bit line.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The step of preparing the bit line contact comprises: preparing a first metal layer on the active pillar, sintering part of the first metal layer and part of the active pillar to form a first metal compound layer, the bit line contact comprises the first metal compound layer and part of the first metal layer; The step of preparing the capacitor contact includes: preparing a second metal layer on the active column, sintering part of the second metal layer and part of the active column to form a second metal compound layer, and the capacitor contact includes the second metal compound layer and part of the second metal layer.

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