Mim capacitor and method of manufacturing the same

Abstract

The application provides a MIM capacitor and a manufacturing method thereof, and is applied to the technical field of semiconductors. Specifically, a metal layer serving as upper and lower plates of the MIM capacitor is formed first, then a three-dimensional multilevel concentric structure type channel which is arranged concentrically with the center as the axis and whose length increases from inside to outside is formed in the metal layer by using a one-step etching process, then a dielectric layer serving as the MIM capacitor is formed in the three-dimensional multilevel concentric structure type channel by using a one-step film deposition process, so that a new three-dimensional concentric full-surrounding type MIM capacitor structure is provided, the manufacturing process steps of the three-dimensional concentric full-surrounding type MIM capacitor are simplified, i.e., the three-step film process in the prior art is reduced to two steps, and the manufacturing time of the device is shortened and the manufacturing cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a metal-insulator-metal (MIM) capacitor and its manufacturing method. Background Technology

[0002] MIM capacitors (Metal-Insulator-Metal capacitors) based on advanced process platforms are currently the mainstream capacitors used in chip manufacturing. They are widely used in energy storage, signal filtering, and high-frequency tuning, and are often applied in CIS chips, decoupling and bypassing, information storage, and other fields.

[0003] In existing processes, the conventional method for forming a MIM capacitor, which includes a top plate electrode, a bottom plate electrode, and a dielectric layer between them, is to complete the construction of the MIM capacitor structure using three deposition process steps, namely, to sequentially deposit the first bottom electrode metal layer, the second intermediate dielectric layer, and the third top electrode metal layer.

[0004] Clearly, existing technologies for forming MIM capacitors typically require a three-step thin-film deposition process, which is time-consuming and significantly increases manufacturing costs. Furthermore, the MIM capacitors formed using this three-step process are only two-dimensional planar structures, resulting in low utilization of silicon wafer area. Summary of the Invention

[0005] The purpose of this invention is to provide a MIM capacitor and its manufacturing method, so as to solve the problems of complicated process steps, long time consumption, high device manufacturing cost and low unit area utilization of silicon wafers caused by the use of a three-step thin film deposition process to form MIM capacitors in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a MIM capacitor, comprising:

[0007] A semiconductor substrate is provided, wherein a metal interconnect layer, an insulating dielectric layer and an etch stop layer are formed sequentially from bottom to top on the surface of the semiconductor substrate;

[0008] The etching stop layer and the insulating dielectric layer are etched to form at least one trench in the insulating dielectric layer and the trench is filled with a metal material layer;

[0009] The metal material layer is etched to form a three-dimensional multi-layer concentric structure channel in the trench, and the remaining metal material layer on both sides of each channel in the three-dimensional multi-layer concentric structure channel is used as the upper and lower plates of the MIM capacitor. The three-dimensional multi-layer concentric structure channel is a plurality of polygonal annular prisms or circular prisms with the center as the concentric axis along the direction parallel to the semiconductor substrate surface, and the diameter length increases from the inside to the outside.

[0010] A capacitor dielectric material layer is filled in the three-dimensional multi-layer concentric channel structure to form the dielectric layer of the MIM capacitor.

[0011] Furthermore, the shape of the concentric structure in the three-dimensional multi-layered concentric structure channel may include a polygonal annular prism or a circular annular prism.

[0012] Furthermore, the width of the trench can be 0.09 μm to 10 μm, and the aspect ratio of the trench in the direction perpendicular to the surface of the semiconductor substrate can be 1:1 to 10:1.

[0013] Furthermore, the width of the three-dimensional multi-layer concentric channel or the dielectric layer in the direction parallel to the semiconductor substrate surface can be 0.045μm to 3μm, and the aspect ratio of the three-dimensional multi-layer concentric channel in the direction perpendicular to the semiconductor substrate surface can be 1:1 to 10:1.

[0014] Furthermore, when multiple trenches are formed in the insulating dielectric layer, after forming the dielectric layer in each trench, the manufacturing method provided by the present invention may further include:

[0015] An insulating isolation layer is formed on the surface of the semiconductor substrate;

[0016] The insulating isolation layer is selectively etched to form metal plugs in the insulating isolation layer covering the top surface of the semiconductor substrate corresponding to each trench, which are metal material layers for leading out the upper and lower plates of the MIM capacitor in the trench.

[0017] Electrically connect at least two metal plugs corresponding to the metal material layers of the upper and lower plates of the MIM capacitors in one or more of the trenches to connect at least two MIM capacitors located in one or more trenches in parallel.

[0018] Furthermore, after the step of forming the dielectric layer, or after the step of connecting at least two MIM capacitors in parallel, the preparation method provided by the present invention may further include:

[0019] A bonding semiconductor substrate is provided, the bonding semiconductor substrate including a first surface and a second surface disposed opposite to each other;

[0020] Based on the manufacturing method of the MIM capacitor as described above, a MIM capacitor composed of a metal material layer and the capacitor dielectric material layer is formed on the first surface of the bonded semiconductor substrate, at least located in one of the trenches.

[0021] The bonding semiconductor substrate is flipped so that the second surface faces upward, and the flipped bonding semiconductor substrate is bonded to the semiconductor substrate.

[0022] Furthermore, the material of the etching stop layer may include silicon nitride or silicon carbide, and the material of the insulating dielectric layer may include at least one of silicon oxide, ultra-low dielectric material or low dielectric material, and the materials of the insulating dielectric layer and the insulating isolation layer may be the same.

[0023] Furthermore, the material of the metal material layer may include at least one of metal, conductive metal oxide, conductive metal nitride, conductive metal carbide, and conductive nonmetal.

[0024] Furthermore, the material of the capacitor dielectric material layer may include a high dielectric constant material, which includes at least one of HfO2, TiO2, HfZrO, Ta2O5, ZrO2, ZrSiO2 or Al2O3.

[0025] Based on the manufacturing method of the MIM capacitor described above, the present invention also provides a MIM capacitor; specifically, the MIM capacitor provided by the present invention may include:

[0026] A semiconductor substrate, wherein a metal interconnect layer and an insulating dielectric layer are formed sequentially from bottom to top on the surface of the semiconductor substrate, and at least one trench is formed in the insulating dielectric layer;

[0027] The upper and lower electrode plates are located in the trench and are composed of metal material layers on both sides of the three-dimensional multi-layer concentric structure channel filled in the trench. The three-dimensional multi-layer concentric structure channel is a plurality of polygonal annular prisms or circular prisms distributed in a direction parallel to the surface of the semiconductor substrate with the center as the concentric axis and the diameter length increasing from the inside to the outside.

[0028] A dielectric layer is located in a three-dimensional, multi-layered, concentric channel between adjacent metal material layers that serve as the upper and lower plates of the MIM capacitor, and the three-dimensional, multi-layered, concentric channel is filled with a capacitor dielectric material layer.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] 1. This invention provides a method for manufacturing a MIM capacitor. First, a metal layer is formed to serve as the upper and lower plates of the MIM capacitor. Then, a three-dimensional, multi-layered concentric channel is formed in the metal layer using a one-step etching process. This channel has a concentric axis parallel to the surface of the semiconductor substrate, with the diameter increasing sequentially from the inside to the outside. Next, a dielectric layer for the MIM capacitor is formed in the three-dimensional, multi-layered concentric channel using a one-step thin-film deposition process. This method simplifies the manufacturing process of the three-dimensional concentric, fully encircling MIM capacitor while providing a novel structure. Specifically, it reduces the three-step thin-film process in the prior art to two steps, thereby shortening the device manufacturing time and reducing manufacturing costs.

[0031] 2. Compared with the two-dimensional planar MIM capacitors formed by existing technologies, the three-dimensional multi-layer concentric channel structure provided by the present invention can maximize the area of ​​the upper and lower plates of the MIM capacitor by increasing the depth of the channel in the semiconductor substrate, while saving the area of ​​the silicon wafer. This avoids the problem of low unit area utilization of silicon wafers in two-dimensional planar MIM capacitors, that is, it improves the unit area utilization of silicon wafers.

[0032] 3. The present invention also proposes to expand the application scenarios of three-dimensional concentric all-around MIM capacitors by bonding three-dimensional concentric all-around MIM capacitors formed on two different semiconductor substrates with silicon wafers. That is, the MIM capacitors formed after bonding can be further applied to the field of three-dimensional integrated circuit manufacturing.

[0033] 4. The present invention also proposes to connect the upper plates of any two three-dimensional concentric fully encircling MIM capacitors formed on the same semiconductor substrate or different semiconductor substrates to the upper plate and the lower plate to the lower plate, thereby achieving the purpose of increasing the capacitance value by connecting MIM capacitors in parallel. Attached Figure Description

[0034] Figure 1 This is a schematic flowchart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention.

[0035] Figures 2a-2e As shown in one embodiment of the present invention Figure 1 A schematic cross-sectional view of a method for manufacturing a MIM capacitor, taken along a direction perpendicular to the surface of the semiconductor substrate (referred to as the Z-plane), during its fabrication process.

[0036] Figures 3a-3eThis is a top view of two three-dimensional multi-layered concentric channel 102 in an embodiment of the present invention, consisting of multiple annular pillars composed of concentric circles, along a direction parallel to the surface of the semiconductor substrate (XY plane).

[0037] Figure 4 In one embodiment of the present invention, two utilizations are provided. Figure 1 The diagram shows a three-dimensional concentric fully encircling MIM capacitor fabricated by the manufacturing method of the MIM capacitor shown, which is then bonded to form a structural schematic of an MIM capacitor suitable for the field of three-dimensional integrated circuits.

[0038] The accompanying figure is labeled as follows:

[0039] 100 - Semiconductor substrate; 110 - Silicon dioxide pad layer;

[0040] 120 - Metal interconnect layer; 130 - Insulating dielectric layer;

[0041] 140 - Etching stop layer; 150 - Metal material layer;

[0042] 160 - Capacitor dielectric material layer; 170 - Insulating layer;

[0043] 180 - Metal plug; 101 - Groove;

[0044] 102 - Three-dimensional multi-layered concentric structure channel;

[0045] 200 - Bonded semiconductor substrate; A - First surface;

[0046] B - Second surface. Detailed Implementation

[0047] As described in the background section, MIM capacitors (Metal-Insulator-Metal capacitors) based on advanced process platforms are currently the mainstream capacitors used in chip manufacturing. They are widely used in energy storage, signal filtering, and high-frequency tuning, and are often applied in CIS chips, decoupling and bypassing, information storage, and other fields.

[0048] In existing processes, the conventional method for forming a MIM capacitor, which includes a top plate electrode, a bottom plate electrode, and a dielectric layer between them, is to complete the construction of the MIM capacitor structure using three deposition process steps, namely, to sequentially deposit the first bottom electrode metal layer, the second intermediate dielectric layer, and the third top electrode metal layer.

[0049] Clearly, existing technologies for forming MIM capacitors typically require a three-step thin-film deposition process, which is time-consuming and significantly increases manufacturing costs. Furthermore, the MIM capacitors formed using this three-step process are only two-dimensional planar structures, resulting in low utilization of silicon wafer area.

[0050] Therefore, the present invention provides a MIM capacitor and its manufacturing method to solve the problems of cumbersome process steps, long time consumption, high device manufacturing cost and low unit area utilization of silicon wafers caused by the three-step thin film deposition process used in the prior art to form MIM capacitors.

[0051] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a MIM capacitor and its manufacturing method according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Many specific details are set forth in the following description to provide a thorough understanding of the present invention; however, the present invention may be practiced in other ways different from those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

[0052] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0053] refer to Figure 1 , Figure 1 This invention provides a method for manufacturing a MIM capacitor in one embodiment. Figure 1 As shown, the manufacturing method of the MIM capacitor proposed in this invention may include at least the following steps:

[0054] Step S100: A semiconductor substrate is provided, wherein a metal interconnect layer, an insulating dielectric layer and an etch stop layer are sequentially formed from bottom to top on the surface of the semiconductor substrate.

[0055] Step S200: Etch the etch stop layer and the insulating dielectric layer to form at least one trench in the insulating dielectric layer and fill the trench with a metal material layer.

[0056] Step S300: Etch the metal material layer and use the remaining metal material layers on both sides of each channel in the three-dimensional multi-layer concentric structure channel as the upper and lower plates of the MIM capacitor; wherein, the three-dimensional multi-layer concentric structure channel is a plurality of polygonal annular prisms or circular prisms distributed in a direction parallel to the surface of the semiconductor substrate with the center as the concentric axis, and the diameter length increases from the inside to the outside.

[0057] Step S400: Fill the three-dimensional multi-layer concentric channel with a capacitor dielectric material layer to form the dielectric layer of the MIM capacitor.

[0058] The following will combine Figures 2a-2e To explain the above in detail Figure 1 The method for manufacturing the MIM capacitor, wherein, Figures 2a-2e This is a schematic diagram of the manufacturing process of a MIM capacitor according to an embodiment of the present invention.

[0059] It should be noted that in the following embodiments, there are multiple directions described, such as the direction parallel to the surface of the semiconductor substrate, the direction perpendicular to the surface of the semiconductor substrate, etc. Therefore, in order to simplify the description, in the following embodiments, the direction parallel to the surface of the semiconductor substrate is uniformly referred to as the XY plane direction, and the direction perpendicular to the surface of the semiconductor substrate is referred to as the Z plane direction.

[0060] In step S100, please refer to the following for details. Figure 2a As shown, a semiconductor substrate 100 is provided, wherein a metal interconnect layer 120, an insulating dielectric layer 130, and an etch stop layer 140 are sequentially formed from bottom to top on the surface of the semiconductor substrate 100. The metal interconnect layer 120 can be one or more layers of metal interconnect structures, each layer containing multiple metal wires made of copper or aluminum. The gaps between adjacent metal wires in each layer are filled with an insulating material, which can be silicon dioxide, silicon nitride, ultra-low dielectric material, or low dielectric material. The semiconductor substrate 100 can be made of materials well known to those skilled in the art, such as silicon, germanium, silicon-germanium, or silicon carbide, or silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials, such as gallium arsenide or other Group III or V compounds. For example, in this embodiment of the invention, the semiconductor substrate 100 is a silicon substrate.

[0061] In this embodiment, an insulating dielectric layer 130, an etch stop layer 140, and a buffer layer (not shown) can be sequentially deposited on the surface of the semiconductor substrate 100, on which the metal interconnect layer 120 has been formed using back-end processing technology. Exemplarily, the deposition process for each film layer can be chemical vapor deposition or physical vapor deposition. The insulating dielectric layer 130 can be made of at least one of silicon oxide, an ultra-low dielectric material, or a low dielectric material. The etch stop layer 140 can be made of silicon nitride or silicon carbide, and the buffer layer can be made of silicon dioxide.

[0062] It is understood that before forming the metal interconnect layer 120 on the surface of the semiconductor substrate 100, a silicon dioxide pad layer 110 may be formed on the surface of the semiconductor substrate 100, and after forming the etch stop layer 140, a buffer layer (not shown) that plays a buffering role in the photoresist etching process may be formed on the surface of the etch stop layer 140.

[0063] In step S200, please refer to the following for details. Figure 2b As shown, the etching stop layer 140 and the insulating dielectric layer 130 are etched to form at least one trench 101 in the insulating dielectric layer 130, and the trench is filled with a metal material layer 150.

[0064] The metal material layer 150 can be made of a metal, such as TiN, TaN, Ti, or Ta, or at least one of a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a conductive nonmetal. This is prior art, and the present invention will not describe this in detail. The width of the trench 101 can be 0.09 μm to 10 μm, that is, the width of the trench 101 can be an integer such as 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. The value can be any decimal between 0.09 and 10, such as 0.09μm, 0.091μm, 0.11μm, 0.112μm, 1.1μm, 1.2μm, 4.5μm, etc., or any range of any two of the above numbers. The aspect ratio of the trench 101 in the direction perpendicular to the surface of the semiconductor substrate 100 is specifically 1:1 to 10:1, that is, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, or any decimal between 1 and 10, such as 1.1, 1.12, 1.123, etc.

[0065] It should be noted that the reference appendix of this invention... Figures 2a-2e as well as Figures 3a-3eThese examples merely illustrate the case where only two MIM capacitors are integrated on the same semiconductor substrate. In other embodiments, one or more MIM capacitors may be formed on the semiconductor substrate 100.

[0066] In this embodiment, the film layer formed on the semiconductor substrate 100 can be etched using either dry etching or wet etching to remove a portion of the etching stop layer 140 and the insulating dielectric layer 130 along a direction perpendicular to the semiconductor substrate 100, thereby forming two independent trenches 101 in the insulating dielectric layer 130. Subsequently, the metal material layer 150 is simultaneously filled into the two trenches 101 using a one-step deposition process, and in a subsequent step, a one-step photolithography etching is used to form the upper and lower plates of the MIM capacitor.

[0067] It is understood that after the above steps of forming the metal material layer 150, the etch stop layer 140, the insulating dielectric layer 130 and the silicon dioxide pad layer 110 respectively using the deposition process, the upper surface of each film layer can be planarized and cleaned before forming subsequent film layers.

[0068] In step S300, please refer to the following for details. Figure 2c As shown, the metal material layer 150 is etched to form a three-dimensional multilayer concentric channel 102 in each trench 101, and the remaining metal material layers on both sides of each trench in the three-dimensional multilayer concentric channel serve as the upper and lower plates of the MIM capacitor. The three-dimensional multilayer concentric channel 102 is composed of multiple polygonal annular prisms or circular prisms with increasing diameters from the inside to the outside, along a direction parallel to the semiconductor substrate surface (XY plane direction) with the center of the multilayer concentric MIM structure as the concentric axis.

[0069] The shape of the concentric structure in the three-dimensional multi-layered concentric structure channel 102 can be a circular ring cylinder, or it can be a polygonal ring prism, such as a hexagonal ring prism, an octagonal ring prism, etc.

[0070] In this embodiment, the existing two-dimensional MIM capacitors formed using a three-step deposition process suffer from problems such as numerous process steps, time consumption, high device manufacturing costs, and low utilization of silicon wafer unit area. The inventors of this invention propose extending the two-dimensional MIM capacitor into a three-dimensional MIM capacitor to solve the problem of low silicon wafer unit area utilization. This results in the three-dimensional concentric fully-encircling MIM capacitor proposed in this invention. Furthermore, to reduce the manufacturing cost of the MIM capacitor, the inventors have further simplified the process steps of the three-dimensional concentric fully-encircling MIM capacitor. Specifically, a one-step deposition process is used to form the metal material layers serving as the upper and lower electrodes of the MIM capacitor, followed by a one-step photolithography etching process, and then a one-step deposition process is used to form the dielectric layer of the MIM capacitor.

[0071] As an example, the present invention illustrates, with reference to the accompanying drawings, a schematic diagram showing that the multiple concentric structures in the three-dimensional multi-layered concentric channel 102 are all circular in shape, as shown in the attached drawings. Figure 2c and Figure 3a As shown, where, Figure 2c This is a cross-sectional schematic diagram of a three-dimensional, multi-layered concentric channel structure, where the multiple concentric structures are all circular, along a direction perpendicular to the surface of the semiconductor substrate (referred to as the Z-plane). Figure 3a This is a top view of the three-dimensional, multi-layered concentric channel structure, in which the multiple concentric structures are all circular, along a direction parallel to the surface of the semiconductor substrate (XY plane).

[0072] In this embodiment, an etching process can be used to form multiple concentric circular channels with a center and a diameter that gradually increases from the inside to the outside in each of the trenches 101, that is, the three-dimensional multi-layer concentric structure channel 102. The remaining metal film layer on one side of each of the concentric circular channels is a plate that can serve as the upper or lower plate of a MIM capacitor. Therefore, by using the manufacturing method of the MIM capacitor provided by the present invention, multiple small MIM capacitors can be formed in the same trench 101, which are composed of metal material layers on both sides of any one of the concentric circular channels and the capacitor dielectric material layer filled in the concentric circular channels. Moreover, the structure corresponding to each trench 101 can also be seen as a large MIM capacitor from the overall perspective.

[0073] Specifically, the width of the three-dimensional multi-layered concentric channel 102 in the XY plane can be 0.045μm to 3μm. That is, the value of each concentric circular channel in the XY plane can be an integer such as 1μm, 2μm, 3μm, or any decimal between 0.045μm and 3μm, such as 0.045μm, 0.05μm, 0.055μm, 0.06μm, 0.07μm, 0.08μm, 0.09μm, 0.1μm, 0.15μm, 0.16μm, 0.17μm, 0.18μm, 0.19μm, 0.2μm, 0.3μm, 0.4μm to 1μm, etc., as well as any range formed by any two of the above numbers. Furthermore, the depth-to-width ratio of the three-dimensional multi-layered concentric structure channel 102 (each of the concentric circular channels) along the Z plane can be specifically 1:1 to 10:1, that is, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, or any decimal between 1 and 10, such as 2.1, 3.12, 5.645, etc.

[0074] In step S400, please refer to the following for details. Figure 2d and Figure 3b As shown, a capacitor dielectric material layer 160 is filled in the three-dimensional multi-layer concentric channel 102 to form the dielectric layer of the MIM capacitor.

[0075] In this embodiment, the dielectric material layer 160 of the capacitor comprises a high dielectric constant material, which includes at least one selected from HfO2, TiO2, HfZrO, Ta2O5, ZrO2, ZrSiO2, or Al2O3. Figure 2d This is a schematic cross-sectional view on the Z-plane when the shape of the concentric structure in the three-dimensional multi-layered concentric channel 102 is circular. Figure 3b This is a top view of the three-dimensional multi-layered concentric channel 102 in a direction parallel to the surface of the semiconductor substrate (XY plane) when the shape of the concentric structure of the concentric structure is circular.

[0076] Clearly, according to steps S100 to S400 as described above, the invention has completed the process of forming a single MIM capacitor in each trench 101, which is a whole and contains multiple smaller MIM capacitors. After step S400, the manufacturing method provided by this invention can further perform CMP mechanical polishing, cleaning, and deposition of the polished insulating dielectric layer on the top surface corresponding to the multi-layered concentric structure.

[0077] Furthermore, the inventors of this invention have proposed several implementation methods to increase the capacitance value of MIM capacitors by interconnecting the upper and lower electrode plates of multiple MIM capacitors, thereby increasing the area of ​​the upper and lower electrode plates and the dielectric layer. The specific implementation methods are as follows.

[0078] Method 1: Reference Figure 3c As shown, the upper plates of multiple small MIM capacitors located in a trench 101 can be interconnected with each other, and the lower plates can be interconnected with each other.

[0079] Method 2: Reference Figure 3d As shown, all the small MIM capacitors in each trench 101 can be used as a large MIM capacitor. Then, the upper plates of the two large MIM capacitors formed in the two trenches 101 are interconnected with each other, and the lower plates are interconnected with each other.

[0080] Method 3: Reference Figure 3e As shown, the upper plates of a plurality of small MIM capacitors in one trench 101 and the lower plates of a plurality of small MIM capacitors in another one or more trenches 101 can be interconnected.

[0081] Regardless of whether it's Method 1, Method 2, or Method 3, the method of interconnecting the upper and lower electrode plates of two or more MIM capacitors is the same: that is, the upper electrode plates are interconnected with each other, and the lower electrode plates are interconnected with each other, using metal plugs. Based on this, the present invention proposes a specific step for connecting multiple MIM capacitors in parallel, as follows:

[0082] Step S500, refer to Figure 2e As shown, an insulating isolation layer 170 is formed on the surface of the semiconductor substrate 100;

[0083] Step S600, continue to refer to Figure 2e As shown, the insulating isolation layer 170 is selectively etched to form metal plugs 180 in the insulating isolation layer 170 covering the top surface of the semiconductor substrate corresponding to each trench, which are metal material layers for leading out the upper and lower plates of the MIM capacitor in the trench.

[0084] Step S700, refer to Figures 3c to 3e As shown, metal plugs 180 corresponding to at least the metal material layers serving as the upper and lower plates of a MIM capacitor in one or more of the trenches 101 are electrically connected to connect at least two MIM capacitors located in one or more trenches 101 in parallel.

[0085] Furthermore, regardless of whether one or more three-dimensional concentric fully-encircling MIM capacitors are formed on a semiconductor substrate using the above steps, or whether three-dimensional concentric fully-encircling MIM capacitors formed on one or more semiconductor substrates are connected in parallel, the resulting three-dimensional concentric fully-encircling MIM capacitors can only be applied to the field of two-dimensional integrated circuits. In order to expand the application scenarios of the three-dimensional concentric fully-encircling MIM capacitors proposed in this invention, this invention also proposes that three-dimensional concentric fully-encircling MIM capacitors formed on two different semiconductor substrates can be bonded to silicon wafers, so that the MIM capacitors formed after bonding can be further applied to the field of three-dimensional integrated circuit manufacturing.

[0086] refer to Figure 4 , Figure 4 In one embodiment of the present invention, two utilizations are provided. Figure 1 The diagram shows a three-dimensional concentric fully encircling MIM capacitor fabricated by the manufacturing method of the MIM capacitor shown, which is then bonded to form a structural schematic of an MIM capacitor suitable for the field of three-dimensional integrated circuits.

[0087] Specifically, after forming the dielectric layer in step S400, or after connecting at least two MIM capacitors in parallel in step S700, the preparation method provided by the present invention may further include the following steps:

[0088] Step S800: A bonding semiconductor substrate 200 is provided, the bonding semiconductor substrate 200 including a first surface A and a second surface B disposed opposite to each other.

[0089] Step S900: Based on the manufacturing method of the MIM capacitor as described above, a MIM capacitor composed of the metal material layer and the capacitor dielectric material layer is formed on the first surface A of the bonding semiconductor substrate 200, which is located in at least one of the trenches.

[0090] Step S1000: Flip the bonding semiconductor substrate 200 so that the second surface B faces upward, and bond the flipped bonding semiconductor substrate 200 to the semiconductor substrate 100.

[0091] In this embodiment, after the bonding semiconductor substrate 200 is flipped in step S1000, or after the three-dimensional concentric fully encircling MIM capacitor is formed on the semiconductor substrate 100 in step S400, semiconductor manufacturing processes such as grinding and thinning processes and cleaning processes can be performed to remove excess substrate or other film layers.

[0092] It should be noted that, in the present invention provided Figures 2a-2e , Figures 3a-3e as well as Figure 4In the examples, each metal plug 180 for external connection of each plate in a three-dimensional concentric fully encircling MIM capacitor formed in one or more of the trenches 101 is shown in partial or full cross-sectional views to meet the requirements of two-dimensional graphic representation.

[0093] Furthermore, based on the manufacturing method of the MIM capacitor described above, the present invention also provides a MIM capacitor manufactured based on the manufacturing method of the MIM capacitor described above, which specifically includes:

[0094] A semiconductor substrate, wherein a metal interconnect layer and an insulating dielectric layer are formed sequentially from bottom to top on the surface of the semiconductor substrate, and at least one trench is formed in the insulating dielectric layer;

[0095] The upper and lower electrode plates are located in the trench and are composed of metal material layers on both sides of the three-dimensional multi-layer concentric structure channel filled in the trench. The three-dimensional multi-layer concentric structure channel is a plurality of polygonal annular prisms or circular prisms distributed in a direction parallel to the surface of the semiconductor substrate with the center as the concentric axis and the diameter length increasing from the inside to the outside.

[0096] A dielectric layer is located in a three-dimensional, multi-layered, concentric channel between adjacent metal material layers that serve as the upper and lower plates of the MIM capacitor, and the three-dimensional, multi-layered, concentric channel is filled with a capacitor dielectric material layer.

[0097] In summary, this invention provides a method for manufacturing a MIM capacitor. First, a metal layer is formed to serve as the upper and lower plates of the MIM capacitor. Then, a three-dimensional, multi-layered concentric channel is formed in the metal layer using a one-step etching process. This channel has a concentric axis parallel to the surface of the semiconductor substrate, with the diameter increasing sequentially from the inside to the outside. Next, a dielectric layer for the MIM capacitor is formed in the three-dimensional, multi-layered concentric channel using a one-step thin-film deposition process. This method not only presents a novel three-dimensional concentric fully encircling MIM capacitor structure but also simplifies the manufacturing process steps, reducing the existing three-step thin-film process to two steps, thereby shortening the device manufacturing time and reducing manufacturing costs.

[0098] Furthermore, compared to the two-dimensional planar MIM capacitors formed by existing technologies, the three-dimensional multi-layer concentric channel structure provided by this invention can maximize the area of ​​the upper and lower plates of the MIM capacitor while saving the area of ​​the silicon wafer by increasing the depth of the channel within the semiconductor substrate. This avoids the problem of low unit area utilization of the silicon wafer in two-dimensional planar MIM capacitors, thus improving the unit area utilization of the silicon wafer.

[0099] Furthermore, this invention proposes to expand the application scenarios of three-dimensional concentric all-around MIM capacitors by bonding three-dimensional concentric all-around MIM capacitors formed on two different semiconductor substrates with silicon wafers. That is, the MIM capacitors formed after bonding can be further applied to the field of three-dimensional integrated circuit manufacturing.

[0100] Furthermore, the present invention proposes to connect the upper plates of any two three-dimensional concentric fully encircling MIM capacitors formed on the same semiconductor substrate or different semiconductor substrates to the upper plate and the lower plate to the lower plate, thereby achieving the purpose of increasing the capacitance value by connecting MIM capacitors in parallel.

[0101] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0102] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0103] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein a metal interconnect layer, an insulating dielectric layer and an etch stop layer are formed sequentially from bottom to top on the surface of the semiconductor substrate; The etching stop layer and the insulating dielectric layer are etched to form at least one trench in the insulating dielectric layer and the trench is filled with a metal material layer; The metal material layer is etched to form a three-dimensional multi-layered concentric channel in the trench, and the remaining metal material layer on both sides of each channel in the three-dimensional multi-layered concentric channel serves as the upper and lower plates of the MIM capacitor; wherein, the three-dimensional multi-layered concentric channel is a plurality of polygonal annular prisms or circular prisms; the plurality of polygonal annular prisms or circular prisms are concentric with their central axis along a direction parallel to the surface of the semiconductor substrate, and their diameters increase sequentially from the inside to the outside starting from the concentric axis; A capacitor dielectric material layer is filled in the three-dimensional multi-layer concentric channel structure to form the dielectric layer of the MIM capacitor.

2. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The shape of the concentric structure in the three-dimensional multi-layered concentric structure channel includes a polygonal annular prism or a circular annular prism.

3. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The width of the trench is 0.09µm to 10µm, and the aspect ratio of the trench in the direction perpendicular to the surface of the semiconductor substrate is 1:1 to 10:

1.

4. The method for manufacturing a MIM capacitor as described in claim 2, characterized in that, The width of the three-dimensional multi-layer concentric channel or the dielectric layer in the direction parallel to the surface of the semiconductor substrate is 0.045µm to 3µm, and the aspect ratio of the three-dimensional multi-layer concentric channel in the direction perpendicular to the surface of the semiconductor substrate is 1:1 to 10:

1.

5. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, When multiple trenches are formed in the insulating dielectric layer, after forming the dielectric layer in each trench, the manufacturing method further includes: An insulating isolation layer is formed on the surface of the semiconductor substrate; The insulating isolation layer is selectively etched to form metal plugs in the insulating isolation layer covering the top surface of the semiconductor substrate corresponding to each trench, which are metal material layers for leading out the upper and lower plates of the MIM capacitor in the trench. Electrically connect at least two metal plugs corresponding to the metal material layers of the upper and lower plates of the MIM capacitors in one or more of the trenches to connect at least two MIM capacitors located in one or more trenches in parallel.

6. The method for manufacturing a MIM capacitor as described in claim 5, characterized in that, After the step of forming the dielectric layer, or after the step of connecting at least two MIM capacitors in parallel, the manufacturing method further includes: A bonding semiconductor substrate is provided, the bonding semiconductor substrate including a first surface and a second surface disposed opposite to each other; According to the manufacturing method of the MIM capacitor based on any one of claims 1-4, a MIM capacitor composed of the metal material layer and the capacitor dielectric material layer is formed on the first surface of the bonded semiconductor substrate, which is located in at least one of the trenches; The bonding semiconductor substrate is flipped so that the second surface faces upward, and the flipped bonding semiconductor substrate is bonded to the semiconductor substrate.

7. The method for manufacturing a MIM capacitor as described in claim 5, characterized in that, The etching stop layer is made of silicon nitride or silicon carbide, and the insulating dielectric layer is made of at least one of silicon oxide or a low dielectric material, and the insulating dielectric layer is made of the same material as the insulating isolation layer.

8. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The material of the metal material layer includes at least one of metal, conductive metal oxide, conductive metal nitride, conductive metal carbide, and conductive nonmetal.

9. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The dielectric material layer of the capacitor includes a high dielectric constant material, which includes at least one of HfO2, TiO2, HfZrO, Ta2O5, ZrO2, ZrSiO2 or Al2O3.

10. A MIM capacitor manufactured according to the manufacturing method of a MIM capacitor as described in any one of claims 1 to 9, characterized in that, include: A semiconductor substrate, wherein a metal interconnect layer and an insulating dielectric layer are formed sequentially from bottom to top on the surface of the semiconductor substrate, and at least one trench is formed in the insulating dielectric layer; The upper and lower electrode plates are located in the trench and are composed of metal material layers on both sides of a three-dimensional multi-layered concentric channel filled in the trench. The three-dimensional multi-layered concentric channel is a plurality of polygonal annular prisms or circular prisms. The plurality of polygonal annular prisms or circular prisms are concentric with a central axis in a direction parallel to the surface of the semiconductor substrate, and their diameters are distributed in an increasing order from the inside to the outside starting from the concentric axis. A dielectric layer is located in a three-dimensional, multi-layered, concentric channel between adjacent metal material layers that serve as the upper and lower plates of the MIM capacitor, and the three-dimensional, multi-layered, concentric channel is filled with a capacitor dielectric material layer.

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