Pulse-echo location cable detector and method of detecting weak pulse signals

Abstract

The present application relates to a kind of impulse echo positioning cable detector, it includes: integral circuit array, each integral circuit unit of integral circuit array includes an integral capacitor;Switch array is used to select the single integral circuit unit in integral circuit array;Test control module is used to divide echo detection period into multiple time slices, and each time slice is associated with a specific integral circuit unit, then each integral circuit unit is selected in turn according to time sequence, and the echo signal of the same time slice of multiple rounds of echo detection period is introduced into the same integral circuit unit to accumulate;Sampling module is used to read out the signal value cached by each integral circuit unit, and the time sequence waveform of echo signal is recovered;And data processing module is used to determine the arrival time of echo pulse.The present application also provides a corresponding weak pulse signal detection method.The present application can detect extremely weak echo signal, so that transmission impedance uneven point can be detected in super long distance.

Description

Technical Field

[0001] This invention relates to the field of weak signal detection technology, and more specifically, to a pulse echo positioning cable detector and a corresponding weak pulse signal detection method. Background Technology

[0002] In existing technologies, cable detectors are mainly used for cable fault detection, such as to meet the cable inspection needs in mines or shafts. The pulse-echo method (i.e., pulse echo localization method) is a common method for cable fault testing. Generally speaking, the pulse-echo method can be used to directly test cables and detect various types of faults such as short circuits and open circuits. Its basic principle is as follows: When measuring cable faults, the cable is considered as a uniformly distributed transmission line. A pulse voltage is applied to one end of the cable. This pulse propagates along the line at a certain speed (determined by the inductance and capacitance per unit length of the cable). When the pulse encounters a fault point (or a point of non-uniform impedance), it is reflected. The cable detector records the transmission time ΔT between the transmitted pulse and the reflected pulse (i.e., the time delay between the arrival time of the echo pulse and the main transmitted pulse). The distance Lx of the fault point can then be calculated based on the known transmission speed V, i.e., Lx = V·ΔT / 2.

[0003] However, cable testers face unique environmental conditions when operating in mines. For example, high-voltage pulse methods may not be suitable for testing coal mine cables. Furthermore, in other types of mines, the use of high-voltage instruments could pose safety hazards or electromagnetic compatibility issues, making high-voltage pulse testing difficult. Consequently, when the cable fault point is far away, the reflected pulse signal may be extremely weak, making it difficult for existing cable testers to detect the fault.

[0004] Specifically, for detecting weak pulse signals, the typical sampling and integration method involves first digitally sampling and then successively summing to recover the signal. The advantage of this approach is its ability to accurately detect the arrival time of the echo pulse. However, this method also suffers from the limitation that the strength of the weakest signal is constrained by the accuracy of the analog-to-digital converter (ADC), which is typically V. full / 2 n V full This represents the full-scale voltage value, where 'n' indicates that the analog-to-digital converter (ADC) has n digits. For example, a 1-volt full-scale, 16-bit ADC (often simply called an AD converter) corresponds to a minimum capture signal of 1 / 2... 16This is approximately 15.3 microvolts. When performing fault testing with a cable detector, if the reflected echo signal is weaker than the weakest detectable signal (e.g., 15.3 microvolts), it will be difficult to detect. On the other hand, if weak pulse signals are detected using analog circuits (e.g., analog integrators), the circuit essentially sums the continuous echo signals over a single capacitor, failing to reveal the details of pulse changes in the resulting signal, especially the precise timing of the pulse occurrence. For example, the time delay between the arrival time of the echo pulse and the main transmitted pulse (i.e., the transmission time ΔT between the transmitted and reflected pulses, as mentioned earlier), which is crucial for ranging, cannot be identified.

[0005] Therefore, there is an urgent need for a cable detector and a solution for weak pulse signal detection that can detect weaker pulse signals and more accurately capture the arrival time of echo pulses. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a cable detector and a solution for weak pulse signal detection that can detect weaker pulse signals and more accurately capture the arrival time of echo pulses.

[0007] To address the aforementioned technical problems, this invention provides a pulse echo positioning cable detector, comprising: an integrating circuit array including multiple integrating circuit units, each integrating circuit unit including an integrating capacitor for receiving weak pulse signals, wherein the weak pulse signal is a pulse signal with a signal strength below the weakest captureable signal of the analog-to-digital converter; a switch array for selecting individual integrating circuit units in the integrating circuit array; and a test control module for controlling multiple rounds of repeated testing of the cable, wherein in each round of testing a probe pulse is applied to the cable under test and an echo signal is received during a set echo detection period; the echo detection period is divided into multiple time slices, and each time slice is associated with a specific... An integrating circuit unit controls the switch array to sequentially select each integrating circuit unit according to a timing sequence, and imports the echo signals of the same time slice in multiple echo detection periods into the same integrating circuit unit for accumulation; a sampling module is used to read the signal value cached by each integrating circuit unit after completing multiple rounds of testing, and then recover the timing waveform of the echo signal for the entire echo detection period according to the time slice associated with each integrating circuit unit; and a data processing module is used to determine the arrival time of the echo pulse based on the timing waveform of the echo signal for the entire echo detection period, and then determine whether the cable under test has a fault and the location of the fault based on the time delay between the arrival time of the echo pulse and the emission time of the detection pulse.

[0008] The test control module is further configured to: connect the integrator array to the cable under test via test lines during each test to receive the echo signal of the probe pulse; wherein, during the time period corresponding to each time slice, control the switch array to select the integrator unit associated with that time slice, so that the echo signal is introduced into different integrator units according to the time slice; and, after the end of the previous round of testing, directly enter the next round of testing while maintaining the accumulated charge of each integrator unit, so that the echo signals of the same time slice in multiple rounds of echo detection are introduced into the same integrator unit for accumulation.

[0009] The test control module is further configured to: disconnect the test line after completing multiple rounds of testing, and simultaneously connect the sampling module to the integrator array via the sampling line; then control the switch array to select each of the integrator units one by one, and then have the sampling module read out the signal buffered by each of the integrator units one by one via the sampling line.

[0010] Each integrating circuit unit includes an integrating capacitor, an operational amplifier, and a measurement control switch. One end of the integrating capacitor is connected to the negative input terminal of the operational amplifier, and the other end is connected to the output terminal of the operational amplifier. The positive input terminal of the operational amplifier is grounded. The negative input terminal of the operational amplifier is connected to the test line to receive the echo signal. One end of the measurement control switch is grounded through a grounding capacitor, and the other end can switch between three terminals: a signal receiving terminal, a signal holding terminal, and a signal output terminal. The signal receiving terminal is connected to the output terminal of the operational amplifier, and the signal output terminal is connected to the sampling line.

[0011] The integrating circuit also includes a reset switch. When a reset control signal is received, the reset switch turns on both ends of the integrating capacitor. When no reset control signal is received, the integrating reset switch disconnects the connection between the two ends of the integrating capacitor.

[0012] Each of the integrator circuit units further includes a comparator and a counter. The comparator includes a signal input terminal, a reference input terminal, and an output terminal. The signal input terminal of the comparator is connected to the signal output terminal of the measurement control switch, and the output terminal of the comparator is connected to the counter. The voltage of the reference input terminal is configured to a constant threshold. When the voltage of the signal input terminal is greater than the voltage of the reference input terminal, the output terminal of the comparator outputs a control signal to the counter, incrementing the counter by 1. The output terminal of the comparator also outputs a control signal to the reset switch of the integrator circuit, resetting the integrator capacitor to zero. Conversely, when the voltage of the signal input terminal is greater than the voltage of the reference input terminal (i.e., the voltage of the signal input terminal is in the opposite direction to the voltage of the reference input terminal, and their sum is less than zero), the counter is decremented by 1, and the output terminal of the comparator also outputs a control signal to the reset switch of the integrator circuit, resetting the integrator capacitor to zero.

[0013] Specifically, for any one of the integrator circuit units, the sampling module reads the voltage value of the integrator capacitor and the count value of the counter, and then combines them with the threshold value configured at the reference input terminal of the comparator to calculate the signal value buffered by the integrator circuit unit.

[0014] The data processing module is further configured to: after obtaining the timing waveform of the echo signal during the entire echo detection period, select a precise scanning period, which can cover the echo pulse portion of the echo signal and has a duration shorter than the duration of the echo detection period; then divide the precise scanning period into multiple time slices and associate each time slice with a specific integrator circuit unit; the test control module is further configured to: perform multiple rounds of precise scanning on the cable, wherein each round of precise scanning involves applying a probe pulse to the cable under test and receiving the echo signal during the set precise scanning period; control the switch array to sequentially select each integrator circuit unit according to the timing sequence, and import the echo signals of the same time slice from multiple rounds of precise scanning periods into the same integrator circuit unit for accumulation; the sampling module is further configured to: after completing multiple rounds of precise scanning, read the signal value cached by each integrator circuit unit, and then, based on the time slice associated with each integrator circuit unit, recover the timing waveform of the echo pulse during the precise scanning period, thereby obtaining the arrival time of the echo pulse during the precise scan.

[0015] According to another aspect of this application, a method for detecting weak pulse signals is also provided, comprising the following steps: 1) performing multiple rounds of repeated testing on the test object, applying a detection pulse to the test object in each round of testing, and receiving the echo signal using an integrator array during a set echo detection period; wherein the echo detection period is divided into multiple time slices, and each time slice is associated with a specific integrator unit in the integrator array; wherein a control switch array is used to sequentially select each of the integrator units according to the timing sequence, and the echo signals of the same time slice in multiple rounds of echo detection periods are imported into the same integrator unit for accumulation; 2) after completing multiple rounds of testing, reading the signal value cached by each integrator unit, and then recovering the timing waveform of the echo signal of the entire echo detection period according to the time slice associated with each integrator unit; 3) determining the arrival time of the echo pulse based on the timing waveform of the echo signal of the entire echo detection period, and then obtaining the time delay between the arrival time of the echo pulse and the emission time of the detection pulse.

[0016] The weak pulse signal detection method further includes the following steps: 4) After obtaining the timing waveform of the echo signal during the entire echo detection period, a precise scanning period is selected, which can cover the echo pulse portion of the echo signal and its duration is shorter than the duration of the echo detection period; then the precise scanning period is divided into multiple time slices, and each time slice is associated with a specific integration circuit unit; 5) Multiple rounds of precise scanning are performed on the cable, wherein each round of precise scanning involves applying a detection pulse to the cable under test and receiving the echo signal during the set precise scanning period; the switch array is controlled to sequentially select each integration circuit unit according to the timing sequence, and the echo signals of the same time slice of multiple rounds of precise scanning periods are imported into the same integration circuit unit for accumulation; 6) After completing multiple rounds of precise scanning, the signal value buffered by each integration circuit unit is read out, and the timing waveform of the echo pulse during the precise scanning period is recovered according to the time slice associated with each integration circuit unit, thereby obtaining the arrival time of the echo pulse after precise scanning.

[0017] Compared with the prior art, this application has at least one of the following technical effects:

[0018] 1. This application can measure the extremely weak echo signal of a faulty cable based on the pulse reflection method, thereby achieving ultra-long-distance measurement of cable faults (for example, by detecting the location of points of non-uniform transmission impedance in the cable to achieve ultra-long-distance measurement of cable faults). Specifically, this application breaks down the entire echo signal into smaller parts, dividing and conquering the echo times with different delays relative to the main pulse time (i.e., the detection pulse emission time), constructing corresponding integrating capacitor arrays for each, and using switching control logic during repeated measurements to allow each integrating capacitor to accumulate (or sum) the signal at a specific delay time point only, until the weak signal strength received and accumulated by the integrating capacitor significantly exceeds the minimum voltage threshold detectable by the sampling module (also known as the analog-to-digital conversion module, i.e., the AD module), thereby allowing the sampling module to sequentially read the integrating capacitors to achieve the purpose of recovering the complete echo signal.

[0019] 2. In some embodiments of this application, by adding a comparator to the integrating circuit unit, the charge accumulated in the integrating capacitor is kept at a low level (i.e., a low charge quantity), thereby avoiding measurement distortion caused by leakage current. Maintaining a low charge quantity can also prevent measurement distortion caused by a decrease in the response speed of the integrating capacitor after long-term use. For example, after the capacitor response speed decreases, the reduced charging and discharging speed may lead to incomplete charging and discharging within a short time slot, which in turn causes the signal received by the integrating capacitor to deviate from the actual value of the echo pulse.

[0020] 3. In some embodiments of this application, a comparator and a technologist are incorporated into the integrating circuit unit, which effectively combines the advantages of analog capacitors and digital devices, avoiding measurement distortion caused by leakage current or reduced capacitor response speed, and effectively improving the accuracy of weak signal detection. This design is particularly suitable for the integrating capacitor unit in this application that achieves signal detection by intermittently accumulating charge (the intermittent period is usually much longer than the integration period).

[0021] 4. In some embodiments of this application, after multiple rounds of testing are completed during the entire echo detection period, the test parameters can be adaptively and precisely matched according to the echo pulse to achieve precise scanning of the segment near the echo pulse, thereby accurately recovering the waveform of the echo pulse and the time delay of the echo pulse (referring to the time delay of the echo pulse relative to the detection pulse).

[0022] 5. In some embodiments of this application, combining the testing of the entire echo detection period with a precise scan of the echo pulse occurrence period allows for the measurement of echo pulse waveforms and echo pulse delays with higher resolution using a smaller number of integrating circuit units. This enables higher resolution measurements to be achieved with a smaller array of integrating circuits, thereby reducing the manufacturing complexity of the devices (e.g., integrating circuit chips). Attached Figure Description

[0023] Figure 1 A schematic diagram of the cable tester in one embodiment of this application is shown;

[0024] Figure 2 A schematic diagram of the integrator circuit array and its connection relationship in one embodiment of this application is shown;

[0025] Figure 3 A schematic diagram of the circuit structure of a specific example of the switch array and integrator array in this application is shown;

[0026] Figure 4 A circuit diagram of an integrating circuit unit in one embodiment of this application is shown;

[0027] Figure 5 A waveform diagram of the clock signal and the control signal of the integrating circuit unit in one embodiment of this application is shown;

[0028] Figure 6 A schematic diagram of the signal flow of the integrator circuit unit of the comparator and the technician in one embodiment of this application is shown. Detailed Implementation

[0029] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be noted that in this specification, the terms "first," "second," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this application, the first subject discussed below may also be referred to as the second subject.

[0031] In the accompanying drawings, the thickness, size, and shape of the objects have been slightly exaggerated for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0032] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed feature, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0033] As used herein, the terms “basically,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to describe inherent biases in measured or calculated values ​​that will be recognized by those skilled in the art.

[0034] Unless otherwise specified, all terms used herein (including technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0037] According to one embodiment of this application, a weak pulse signal cable detector is provided. The design concept is as follows: the entire echo signal is broken down into smaller parts, and echo times with different delays relative to the main pulse time (i.e., the detection pulse emission time) are divided and conquered, with corresponding integrating capacitor arrays constructed for each. During repeated measurements, switching control logic ensures that each integrating capacitor accumulates (or sums) the signal only at a specific delay time point, until the strength of the weak signal received and accumulated by the integrating capacitors significantly exceeds the minimum voltage threshold detectable by the sampling module (also known as the analog-to-digital conversion module, i.e., the AD module). Then, the sampling module sequentially reads the integrating capacitors, achieving the purpose of recovering the complete echo signal.

[0038] Specifically, refer to Figure 1The cable tester of this embodiment includes: an integrating circuit array, a switch array, a test control module, a sampling module, and a data processing module. The integrating circuit array includes multiple integrating circuit units, each of which includes an integrating capacitor for receiving weak pulse signals. For ease of description, this embodiment defines a weak pulse signal as a pulse signal with a signal strength below the weakest captureable signal of a common analog-to-digital converter (i.e., the analog-to-digital converter used as the sampling module) (e.g., for a 16-bit analog-to-digital converter, the corresponding weakest captureable signal is approximately 15.3 microvolts). In this document, weak pulse signals are sometimes simply referred to as weak pulse signals. The switch array is used to select individual integrating circuit units in the integrating circuit array. The test control module controls multiple rounds of repeated testing of the cable. In each round, a probe pulse is applied to the cable under test, and echo signals are received during a set echo detection period. The echo detection period is divided into multiple time slices, and each time slice is associated with a specific integrating circuit unit. The module controls the switch array to sequentially select each integrating circuit unit according to the timing sequence, and inputs the echo signals from the same time slice of multiple echo detection periods into the same integrating circuit unit for accumulation. After completing multiple rounds of testing, the sampling module reads the signal value buffered by each integrating circuit unit, and then reconstructs the timing waveform of the echo signal for the entire echo detection period based on the time slice associated with each integrating circuit unit. The data processing module determines the arrival time of the echo pulse based on the timing waveform of the echo signal for the entire echo detection period, and then determines whether the cable under test has a fault and the location of the fault based on the time delay between the arrival time of the echo pulse and the emission time of the probe pulse.

[0039] More specifically, Figure 2 A schematic diagram of an integrator circuit array and its connections in one embodiment of this application is shown. (Reference) Figure 2The test control module can disconnect the test line after completing multiple rounds of testing, and simultaneously connect the sampling module to the integrator array via the sampling line. Then, it controls the switch array to select each integrator unit one by one, and the sampling module reads the signal buffered by each integrator unit one by one via the sampling line. In each test, the integrator array can be connected to the cable under test via the test line to receive the echo signal of the probe pulse. Specifically, during each time slot, the switch array is controlled to select the integrator unit associated with that time slot, so that the echo signal is fed into different integrator units according to the time slot. Furthermore, after the previous round of testing ends, the next round of testing is directly entered while maintaining the accumulated charge in each integrator unit (i.e., without resetting each integrator unit to zero), so that the echo signals from the same time slot in multiple rounds of echo detection are fed into the same integrator unit for accumulation. This embodiment can fully utilize the advantages of analog integrator front-end technology and analog-to-digital conversion technology. While retaining the advantages of the sampling integrator, it enhances the signal-to-noise ratio in the analog front-end by repeated testing and time-division integration, thereby pushing the weakest captureable signal into a more sensitive range.

[0040] Furthermore, in some embodiments of this application, the test control module can be implemented by a microcontroller, and the data processing module can be implemented by a PC or other type of host computer. The specific functions of the data processing module can be implemented using measurement software.

[0041] In some embodiments of this application, the switch array can determine which integrator unit in the integrator array is selected using a row gating signal and a column gating signal. For example, the integrator units in the integrator array can be arranged in an m x n array structure, and the switch array can include column gating switches and row gating switches. (See reference...) Figure 3There are m row selector switches arranged vertically and n column selector switches arranged horizontally. Assuming the i-th row selector switch is on and the other row selector switches are off, and the j-th column selector switch is on and the other column selector switches are off, then the integrating circuit unit in the i-th row and j-th column is selected, while the other integrating circuit units are in a waiting state. For ease of description, the integrating circuit unit in the i-th row and j-th column can be denoted as the (i, j)-th integrating circuit unit, where i and j are integers, and 1 ≤ i ≤ m, 1 ≤ j ≤ n. Furthermore, after the (i, j)-th integrating circuit unit is selected, the unit can be controlled by a switch inside the unit (e.g., a measurement control switch or a reset switch) to enter an integrating state, a holding state (i.e., holding the collected charge in the integrating capacitor, waiting for the next round of testing), a reading state, or a reset state. The following sections will further describe the integrating state, holding state, reading state, and reset state of the integrating circuit unit in conjunction with its specific circuit diagram.

[0042] To facilitate understanding, a specific example is provided below. Based on the cable detector of the above embodiment, a test cycle can be completed in 5ms, thus the echo detection period for each test cycle can be 5ms. Each echo detection period is divided into 100 time slices, each time slice lasting approximately 50μs. In practice, the duration of each time slice can also be slightly less than 50μs, for example, 40μs, to allow sufficient time for the switching of the integrating circuit unit. The cable detector can have a clock signal module for generating a clock signal to achieve clock synchronization of the entire cable detector and determine the opening and closing times of each switch in the switch array based on the clock signal, thereby accurately selecting the specific integrating circuit unit associated with it in each time slice. The clock signal module has a main frequency in the MHz range, with each clock cycle being approximately 1μs. The clock signal module can achieve clock synchronization of various modules such as the switch array and the integrating circuit array. Figure 5 The diagram illustrates the waveforms of the clock signal and the control signal of the integrator unit in one embodiment of this application. In this embodiment, the control signal may include a reset signal, an integration signal, and a read signal. The reset signal controls the integrator unit to reset, the integration signal controls the integrator unit to enter the integration state, and the read signal controls the sampling module to read data from the integrator unit.

[0043] It should be noted that in this application, the charge collected by the integrating capacitor is actually achieved through intermittent charge accumulation. For each integrating capacitor, a relatively long waiting time is often required between adjacent test rounds, which differs from the integrating capacitors commonly used in the prior art (which typically accumulate charge within a short, continuous period). When the charge of an integrating capacitor is large and the waiting time is long, leakage current may occur, leading to distortion of the final measurement results. Based on the above analysis, in some embodiments of this application, an improved integrating circuit unit for suppressing leakage current is also designed. Specifically, Figure 4 A circuit diagram of an integrating circuit unit according to one embodiment of this application is shown. (Reference) Figure 4 In some embodiments of this application, each integrating circuit unit includes an integrating capacitor C1, an operational amplifier A, and a measurement control switch S2. One end of the integrating capacitor C1 is connected to the negative input terminal A0 of the operational amplifier A, and the other end is connected to the output terminal of the operational amplifier A. The positive input terminal of the operational amplifier A is grounded. The negative input terminal A0 of the operational amplifier A is connected to the test line to receive the echo signal. One end of the measurement control switch S2 is grounded through a grounding capacitor C2, and the other end can be switched between three terminals: a signal receiving terminal 21, a signal holding terminal 22, and a signal output terminal 23. The signal receiving terminal 21 is connected to the output terminal of the operational amplifier A, and the signal output terminal 23 is connected to the sampling line. In this embodiment, when the measurement control switch S2 is connected to the signal receiving terminal 21, the integrating circuit unit enters the integration state. At this time, the echo signal is applied to the integrating capacitor C1, causing the integrated capacitor C1 to accumulate charge (the accumulated charge can characterize the acquired echo signal). When the measurement control switch S2 is connected to the signal holding terminal 22, the integrating circuit unit enters the holding state. At this time, the connection between the test line and the integrating capacitor C1 is disconnected, and the integrating capacitor C1 retains the collected charge, waiting to enter the next round of testing. Typically, the next round of testing will only begin after all time slices in the echo detection period; therefore, the duration of the holding state is much longer than the duration of the integrating state. Further, when the measurement control switch S2 is connected to the signal output terminal 23, the integrating circuit unit enters the reading state. At this time, the signal output terminal 23 can be connected to the sampling line, and the sampling module can read the accumulated charge of the integrating capacitor through the signal output terminal 23, thereby obtaining the accumulated (or superimposed) echo signal value (e.g., voltage value) after multiple rounds of testing. Since each integrating circuit unit is associated with a specific time slice, the echo signal value of that specific time slice can be obtained. By reading the echo signal values ​​of all integrating circuit units, the echo signal of the entire echo detection period can be recovered.

[0044] Furthermore, still referencing Figure 4 The integrating circuit may further include a reset switch S1. When a reset control signal is received, the reset switch S1 turns on both ends of the integrating capacitor C1 to clear the charge accumulated in the integrating capacitor C1 (i.e., the reset switch S1 is connected to the first terminal S11). When no reset control signal is received, the integrating reset switch disconnects the connection between the two ends of the integrating capacitor C1 (i.e., the reset switch S1 is connected to the second terminal S12).

[0045] Furthermore, Figure 6 A schematic diagram of the signal flow of an integrating circuit unit with an added comparator and technician in one embodiment of this application is shown. (Reference) Figure 6 In some embodiments of this application, each integrating circuit unit may further include a comparator and a counter. The comparator includes a signal input terminal, a reference input terminal, and an output terminal. The signal input terminal of the comparator is connected to the signal output terminal of the measurement control switch, and the output terminal of the comparator is connected to the counter. The voltage of the reference input terminal is configured to a constant threshold. When the voltage of the signal input terminal is greater than the voltage of the reference input terminal, the output terminal of the comparator outputs a control signal to the counter, incrementing the counter by 1. Furthermore, when the voltage of the signal input terminal is greater than the voltage of the reference input terminal, the output terminal of the comparator also outputs a control signal to the reset switch of the integrating circuit, clearing the integrating capacitor to zero. For any integrating circuit unit, the sampling module reads the voltage value of the integrating capacitor and the count value of the counter, and then combines this with the threshold value configured at the reference input terminal of the comparator to calculate the signal value buffered by the integrating circuit unit. In the above embodiments, by adding a comparator to the integrating circuit unit, the charge accumulated by the integrating capacitor is kept at a low level (i.e., a low charge quantity), thereby avoiding measurement distortion caused by leakage current. Maintaining a low charge quantity also avoids the problem of oversaturation of the integrating capacitor, thus preventing measurement distortion caused by a decrease in the response speed of the integrating capacitor after long-term use. For example, after the capacitor response speed decreases, the charging and discharging speed may decrease, resulting in incomplete charging and discharging within a short time slot, which in turn causes the signal received by the integrating capacitor to deviate from the actual value of the echo pulse. In summary, setting a comparator and a comparator in the integrating circuit unit effectively integrates the advantages of analog capacitors and digital devices, avoiding measurement distortion caused by leakage current or a decrease in capacitor response speed, and effectively improving the accuracy of weak signal detection. This design is particularly suitable for the integrating capacitor unit of this application that realizes signal detection by intermittently accumulating charge (the intermittent period is usually much longer than the integration period).

[0046] Because the actual conditions of cable faults can be varied, especially since mining cables are often deployed in extremely complex and harsh environments, the actual waveform and magnitude of the echo signal are often difficult to predict accurately. Before using the cable tester described in this application, the number of test cycles and the length of each time slice are typically set based on experience. However, the actual echo pulse may not match the preset number of test cycles and time slice length. For example, if the number of cycles is set too low, the echo pulse may still be very small after superposition, making it difficult to detect. If the number of cycles is set too high, the pulse signal value after repeated superposition may be too large, leading to distortion. Similarly, if the time slice length is set too low, the echo pulse may also be too small after superposition, making it difficult to detect. If the time slice length is set too high, both the accurate time delay and the waveform of the echo pulse may deviate. Therefore, in some embodiments of this application, the cable tester is further improved. The improved tester can adaptively and accurately match the test parameters according to the echo pulse to achieve accurate scanning (or focused scanning) of the section near the echo pulse, thereby accurately recovering the waveform of the echo pulse and the time delay of the echo pulse (referring to the time delay of the echo pulse relative to the probe pulse).

[0047] Specifically, in one embodiment of this application, the data processing module is further configured to: after obtaining the timing waveform of the echo signal during the entire echo detection period, select a precise scanning period, wherein the precise scanning period can cover the echo pulse portion of the echo signal, and its duration can be much shorter than the duration of the echo detection period; then divide the precise scanning period into multiple time slices, and associate each time slice with a specific integrator circuit unit. The test control module is further configured to: perform multiple rounds of precise scanning on the cable, wherein each round of precise scanning involves applying a probe pulse to the cable under test and receiving the echo signal during the set precise scanning period; control the switch array to sequentially select each of the integrator circuit units according to the timing sequence, and import the echo signals of the same time slice from multiple rounds of precise scanning periods into the same integrator circuit unit for accumulation. The sampling module is further configured to: after completing multiple rounds of precise scanning, read the signal value cached by each integrator circuit unit, and then, based on the time slice associated with each integrator circuit unit, recover the timing waveform of the echo pulse during the precise scanning period, thereby obtaining the arrival time of the echo pulse during the precise scan. Furthermore, in this embodiment, during the precise scanning process, the number of time slices can be from ten to several dozen. This allows for better discontinuous integration of the length of each time slice while also providing high temporal resolution. After the precise scanning, due to the adaptive precise matching of the test parameters, the waveform of the measured echo pulse and the measurement accuracy of the echo pulse's delay relative to the probe pulse are both improved.

[0048] Furthermore, the weak pulse signal detection technology of this application can also be extended to other application scenarios besides cable inspection. For example, underwater search and rescue, atmospheric turbulence monitoring, and laser positioning and ranging.

[0049] Specifically, according to one embodiment of this application, a method for detecting weak pulse signals is provided, which includes the following steps:

[0050] 1) The test object is subjected to multiple rounds of repeated testing. In each round of testing, a probe pulse is applied to the test object, and an integrator circuit array is used to receive the echo signal during a set echo detection period. The echo detection period is divided into multiple time slices, and each time slice is associated with a specific integrator circuit unit in the integrator circuit array. The control switch array sequentially selects each integrator circuit unit according to the timing sequence, and the echo signals of the same time slice in multiple rounds of echo detection are fed into the same integrator circuit unit for accumulation.

[0051] 2) After completing multiple rounds of testing, read out the signal value cached by each integration circuit unit, and then reconstruct the timing waveform of the echo signal during the entire echo detection period based on the time slice associated with each integration circuit unit.

[0052] 3) Determine the arrival time of the echo pulse based on the timing waveform of the echo signal during the entire echo detection period, and then obtain the time delay between the arrival time of the echo pulse and the emission time of the detection pulse.

[0053] Furthermore, in a preferred embodiment, the weak pulse signal detection method may further include the following steps in addition to steps 1)-3):

[0054] 4) After obtaining the timing waveform of the echo signal during the entire echo detection period, a precise scanning period is selected. The precise scanning period can cover the echo pulse portion of the echo signal, and its duration is shorter than the duration of the echo detection period. Then, the precise scanning period is divided into multiple time slices, and each time slice is associated with a specific integration circuit unit.

[0055] 5) Perform multiple rounds of precise scanning on the cable, wherein each round of precise scanning involves applying a probe pulse to the cable under test and receiving the echo signal during the set precise scanning period; control the switch array to sequentially select each of the integrator circuit units according to the timing sequence, and input the echo signals of the same time slice of multiple rounds of precise scanning periods into the same integrator circuit unit for accumulation.

[0056] 6) After completing multiple rounds of precise scanning, read out the signal value cached by each of the integrator circuit units, and then reconstruct the timing waveform of the echo pulse during the precise scanning period based on the time slice associated with each integrator circuit unit, thereby obtaining the arrival time of the echo pulse after precise scanning.

[0057] Besides cable inspection, in applications such as underwater search and rescue, atmospheric turbulence monitoring, and laser positioning and ranging, when the echo pulse signal is extremely weak, for example, when its signal strength is below the weakest capture signal of the analog-to-digital converter (for example, for a 16-bit analog-to-digital converter, the corresponding weakest capture signal is about 15.3 microvolts), the above-mentioned weak pulse signal detection method can help to measure such weak pulse signals and accurately detect the specific time of the pulse signal (i.e., the arrival time of the echo pulse). Then, by detecting the location of the non-uniformity of transmission impedance, the corresponding functions in various application scenarios such as underwater search and rescue, atmospheric turbulence monitoring, and laser positioning and ranging can be realized.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A pulse-echo positioning cable detector, characterized in that, It includes: An integrating circuit array includes multiple integrating circuit units, each integrating circuit unit including an integrating capacitor for receiving weak pulse signals, the weak pulse signals being pulse signals with a signal strength below the weakest capture signal of the analog-to-digital converter. A switch array for selecting individual integrator units in the integrator array; The test control module is used to control the cable to undergo multiple rounds of repeated testing. In each round of testing, a probe pulse is applied to the cable under test and the echo signal is received during a set echo detection period. The echo detection period is divided into multiple time slices, and each time slice is associated with an integrator circuit unit. The module controls the switch array to sequentially select each of the integrator circuit units according to the timing sequence, and inputs the echo signals of the same time slice in multiple rounds of echo detection periods into the same integrator circuit unit for accumulation. The sampling module is used to read the signal value cached by each of the integrator circuit units after completing multiple rounds of testing, and then recover the timing waveform of the echo signal during the entire echo detection period based on the time slice associated with each integrator circuit unit. as well as The data processing module is used to determine the arrival time of the echo pulse based on the timing waveform of the echo signal during the entire echo detection period, and then determine whether the cable under test has a fault and the location of the fault based on the time delay between the arrival time of the echo pulse and the emission time of the detection pulse. Each of the integrator circuit units includes: an integrator capacitor, an operational amplifier, and a measurement control switch; One end of the integrating capacitor is connected to the negative input terminal of the operational amplifier, and the other end is connected to the output terminal of the operational amplifier. The positive input terminal of the operational amplifier is grounded. The negative input terminal of the operational amplifier is connected to a test lead to receive the echo signal. One end of the measurement control switch is grounded through a grounding capacitor, and the other end switches between three terminals: a signal receiving terminal, a signal holding terminal, and a signal output terminal. The signal receiving terminal is connected to the output terminal of the operational amplifier, and the signal output terminal is connected to the sampling line. The integrating circuit also includes a reset switch. When a reset control signal is received, the reset switch turns on both ends of the integrating capacitor. When no reset control signal is received, the reset switch disconnects the connection between the two ends of the integrating capacitor.

2. The pulse echo positioning cable detector according to claim 1, characterized in that, The test control module is further configured to: connect the integrator array to the cable under test via test lines in each test to receive the echo signal of the probe pulse; wherein, during the time period corresponding to each time slice, control the switch array to select the integrator unit associated with that time slice, so that the echo signal is introduced into different integrator units according to the time slice; and, after the end of the previous round of testing, directly enter the next round of testing while maintaining the accumulated charge of each integrator unit, so that the echo signals of the same time slice in multiple rounds of echo detection are introduced into the same integrator unit for accumulation.

3. The pulse echo positioning cable detector according to claim 2, characterized in that, The test control module is also used to: disconnect the test line after completing multiple rounds of testing, and at the same time connect the sampling module to the integrator array through the sampling line; then control the switch array to select each of the integrator units one by one, and then have the sampling module read out the signal buffered by each of the integrator units one by one through the sampling line.

4. The pulse echo positioning cable detector according to claim 1, characterized in that, Each of the integrator circuit units further includes a comparator and a counter. The comparator includes a signal input terminal, a reference input terminal, and an output terminal. The signal input terminal of the comparator is connected to the signal output terminal of the measurement control switch, and the output terminal of the comparator is connected to the counter. The voltage of the reference input terminal is configured to a constant threshold. When the voltage at the signal input terminal is greater than the voltage at the reference input terminal, the output terminal of the comparator outputs a control signal to the counter, incrementing the counter by 1. The output terminal of the comparator also outputs a control signal to the reset switch of the integrator circuit, resetting the integrating capacitor to zero. Conversely, when the voltage at the signal input terminal is greater than the voltage at the reference input terminal, the output terminal of the comparator outputs a control signal to the counter, decrementing the counter by 1. The output terminal of the comparator also outputs a control signal to the reset switch of the integrator circuit, resetting the integrating capacitor to zero.

5. The pulse echo positioning cable detector according to claim 4, characterized in that, For any of the aforementioned integrator circuit units, the sampling module reads the voltage value of the integrating capacitor and the count value of the counter, and then combines them with the threshold value configured at the reference input terminal of the comparator to calculate the signal value buffered by the integrator circuit unit.

6. The pulse echo positioning cable detector according to claim 2, characterized in that, The data processing module is further configured to: after obtaining the timing waveform of the echo signal during the entire echo detection period, select a precise scanning period, the precise scanning period covering the echo pulse portion of the echo signal, and its duration being less than the duration of the echo detection period; then divide the precise scanning period into multiple time slices, and associate each time slice with one of the integrator circuit units; The test control module is also used to: perform multiple rounds of precise scanning on the cable, wherein each round of precise scanning involves applying a probe pulse to the cable under test and receiving an echo signal during the set precise scanning period; control the switch array to sequentially select each of the integrator circuit units according to the timing sequence, and input the echo signals of the same time slice of multiple rounds of precise scanning periods into the same integrator circuit unit for accumulation; The sampling module is also used to: after completing multiple rounds of precise scanning, read out the signal value cached by each of the integral circuit units, and then, based on the time slice associated with each integral circuit unit, recover the timing waveform of the echo pulse during the precise scanning period, thereby obtaining the arrival time of the echo pulse of the precise scan.

7. A method for detecting weak pulse signals based on the pulse echo positioning cable detector according to claim 1, characterized in that, Includes the following steps: 1) The test object is subjected to multiple rounds of repeated testing. In each round of testing, a probe pulse is applied to the test object, and an integrator circuit array is used to receive the echo signal during a set echo detection period. The echo detection period is divided into multiple time slices, and each time slice is associated with an integrator circuit unit in the integrator circuit array. The control switch array sequentially selects each integrator circuit unit according to the timing sequence, and the echo signals of the same time slice in multiple rounds of echo detection are fed into the same integrator circuit unit for accumulation. 2) After completing multiple rounds of testing, read out the signal value cached in each of the integrator circuit units, and then reconstruct the timing waveform of the echo signal for the entire echo detection period based on the time slice associated with each integrator circuit unit. 3) Determine the arrival time of the echo pulse based on the timing waveform of the echo signal during the entire echo detection period, and then obtain the time delay between the arrival time of the echo pulse and the emission time of the detection pulse.

8. The weak pulse signal detection method according to claim 7, characterized in that, It also includes the following steps: 4) After obtaining the timing waveform of the echo signal during the entire echo detection period, a precise scanning period is selected, which covers the echo pulse portion of the echo signal and has a duration shorter than the duration of the echo detection period; then the precise scanning period is divided into multiple time slices, and each time slice is associated with one of the integrator circuit units. 5) Perform multiple rounds of precise scanning on the cable, wherein each round of precise scanning involves applying a probe pulse to the cable under test and receiving the echo signal during the set precise scanning period; control the switch array to sequentially select each of the integrator circuit units according to the timing sequence, and input the echo signals of the same time slice of multiple rounds of precise scanning periods into the same integrator circuit unit for accumulation. 6) After completing multiple rounds of precise scanning, read out the signal value cached by each integration circuit unit, and then recover the timing waveform of the echo pulse during the precise scanning period based on the time slice associated with each integration circuit unit, thereby obtaining the arrival time of the echo pulse after precise scanning.

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