Pulse controller control method, device, computer equipment and storage medium

Abstract

The present application provides a control method, device, computer equipment and storage medium for a pulse controller, wherein the control method comprises: confirming whether a time interruption occurs in the current cycle; if it is confirmed that an interruption occurs in the current cycle, determining whether the position information of the motor's current cycle plan is equal to the position information of the previous cycle; if they are not equal, determining the number of pulses that need to be issued in the current cycle to compensate for the position of the motor based on the position information of the motor's previous cycle and the current cycle. The present application does not require additional external encoder counts. When a cycle interruption is detected, the number of pulses that need to be issued in the current cycle is determined based on the position information of the previous cycle and the current cycle by determining whether the position information of the motor's current cycle plan is equal to the position information of the previous cycle, thereby achieving compensation operation for the position of the motor in the current cycle. The system has high precision and strong stability, and can achieve closed-loop control of the entire system.

Description

Technical Field

[0001] The present application relates to the field of motion control technology, and in particular to a control method, device, computer equipment, and storage medium for a pulse controller. Background Art

[0002] In a PLC (Programmable Logic Controller) motion control system, pulse loss can have a significant impact on the operation of the entire system. Therefore, the motion control system must ensure that no pulse is lost.

[0003] Currently, the logic of the master and slave pulse axes is generally implemented on the FPGA (Field-Programmable Gate Array) side. The master controller is synchronized with the FPGA by an ARM (Advanced RISC Microprocessor), so the periodic interrupt time is a fixed time. However, for the slave expansion axis module, the FPGA needs to be synchronized with the ARM. However, since the master MCU (Microcontroller Unit) has a clock and the slave MCU also has a clock, and the clock domains of the two clocks are different and need to be synchronized, jitter will be generated. For example, the master clock is fast and the slave clock is slow. The slave clock needs to speed up its own clock, but it can never be adjusted to an accurate value, so a jitter of about ±2us will be generated. Therefore, a method is needed to eliminate the problem of lost pulses caused by unstable periodic interruptions. In the prior art, a closed-loop feedback is formed through an external absolute encoder, but its periodic interruption is a stable time, so it has the following defects:

[0004] 1. The periodic interruption time is a fixed value and cannot be applied to scenarios where periodic interruptions are unstable.

[0005] 2. Only for the master station pulse module;

[0006] 3. External encoder counting is required. Summary of the Invention

[0007] The purpose of the embodiments of the present application is to propose a control method, device, computer equipment and storage medium for a pulse controller, which can solve the problem that a closed-loop feedback is formed by an external absolute encoder in the prior art, but its periodic interruption is a stable time and cannot be applied to scenarios where the periodic interruption is unstable.

[0008] In order to solve the above technical problems, an embodiment of the present application provides a control method for a pulse controller, which includes: confirming whether a time interruption occurs in the current cycle; if it is confirmed that an interruption occurs in the current cycle, judging whether the position information planned for the current cycle of the motor is equal to the position information of the previous cycle; if they are not equal, determining the number of pulses that need to be issued in the current cycle based on the position information of the previous cycle and the current cycle of the motor to compensate for the position of the motor.

[0009] Among them, determining the number of pulses that need to be sent in the current cycle to compensate for the position of the motor based on the position information of the motor in the previous cycle and the current cycle includes: determining the number of pulses that need to be corrected in the current cycle based on the position information of the motor in the previous cycle and the position information of the current cycle; and determining the number of pulses that need to be sent in the current cycle of the motor to compensate for the position of the motor based on the number of pulses that need to be corrected.

[0010] Among them, determining the number of pulses that need to be corrected in the current cycle based on the position information of the motor in the previous cycle and the position information of the current cycle includes: obtaining the planned logical position of the motor in the previous cycle and the logical position accumulated by the FPGA; and obtaining the number of pulses that need to be corrected in the current cycle based on the difference between the planned logical position of the motor and the logical position accumulated by the FPGA.

[0011] Among them, the number of pulses corrected as needed determines the number of pulses that need to be sent by the motor in the current cycle to compensate for the position of the motor, including: obtaining the planned logical position of the motor in the current cycle and the planned logical position of the motor in the previous cycle; determining the difference between the planned logical position of the motor in the current cycle and the planned logical position of the previous cycle; and obtaining the number of pulses that need to be sent by the motor in the current cycle to compensate for the position of the motor based on the difference and the number of pulses that need to be corrected in the current cycle.

[0012] If it is determined that the position information of the motor in the current cycle is equal to the position information of the previous cycle, then there is no need to perform position compensation on the motor in the current cycle.

[0013] The position information of the motor in the current cycle is the actual logical position, and the position information of the motor in the previous cycle is the planned logical position.

[0014] The confirmation of whether an interrupt occurs in the current cycle is performed by judging whether a rising edge of a high level is detected in the current cycle.

[0015] In order to solve the above technical problems, an embodiment of the present application also provides a closed-loop control device of a pulse controller, and the closed-loop control device includes: a confirmation module, used to confirm whether a time interruption occurs in the current cycle; a judgment module, used to determine whether the planned position information of the motor in the current cycle and the position information of the previous cycle are equal when confirming that the current cycle is interrupted; a compensation module, used to determine the number of pulses that need to be issued in the current cycle to compensate for the position of the motor based on the position information of the previous cycle and the current cycle when it is determined that the planned position information and the actual position information of the motor in the current cycle are not equal.

[0016] In order to solve the above technical problems, an embodiment of the present application also provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the processor executes the computer-readable instructions, it implements the steps of the control method of the pulse controller as described in any one of the above items.

[0017] In order to solve the above technical problems, an embodiment of the present application also provides a computer-readable storage medium, which adopts the following technical solution: the computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps of the control method of the pulse controller described above are implemented.

[0018] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0019] The present application provides a control method, device, computer equipment and storage medium for a pulse controller, which performs logical position counting through an internal FPGA without the need for additional external encoder counting. When a cycle interruption is detected, it is determined whether the position information planned for the current cycle of the motor is equal to the position information of the previous cycle, and then the number of pulses required to be issued in the current cycle is determined based on the position information of the previous cycle and the current cycle, thereby achieving compensation operation for the position of the motor in the current cycle. It has high precision and strong stability, and can achieve closed-loop control of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the solutions in this application, a brief introduction will be given below to the drawings required for use in the description of the embodiments of this application. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a schematic structural diagram of an embodiment of a closed-loop control system of a pulse controller of the present application;

[0022] Figure 2This is a flow chart of an embodiment of a control method of a pulse controller of the present application;

[0023] Figure 3 This is a flowchart of an implementation method of step S300 of this application;

[0024] Figure 4 This is a flowchart of an implementation method of step S310 of this application;

[0025] Figure 5 This is a flowchart of an implementation method of step S320 of this application;

[0026] Figure 6 It is a curve diagram of the motor position information of this application;

[0027] Figure 7 It is a schematic diagram of the internal logic of the system of this application;

[0028] Figure 8 This is a schematic structural diagram of an embodiment of a control device of a pulse controller of the present application;

[0029] Figure 9 It is a structural diagram of an embodiment of a computer device according to the present application. DETAILED DESCRIPTION

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned description of the drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order.

[0031] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0033] Please combine Figure 1 , Figure 1This is a schematic diagram of the structure of an embodiment of a closed-loop control system of a pulse controller of this application, as shown in FIG. Figure 1 The control system of the present application includes a master station, a slave station, a servo drive and a motor.

[0034] The master station and the slave stations are connected via the RS485 bus.

[0035] The slave station also includes an MCU (Microcontroller Unit), an FPGA (Field Programmable Gate Array), a differential drive circuit, and a differential-to-single-ended converter. The MCU is connected to the FPGA via a parallel bus and a periodic interrupt line, the FPGA is connected to the differential drive circuit and the differential-to-single-ended converter, and the differential drive circuit and the differential-to-single-ended converter are connected to the servo drive and motor.

[0036] Understandably, in motion control systems, the master module is limited by FPGA resources and pins and generally has only 4-8 pulse axes. However, when more than 8 pulse axes are required, the number of local axis pulses may not meet the demand, so an external axis pulse module is required. The external pulse axis module is a slave station, which consists of an MCU and an FPGA control system. In the entire system, the master and slave stations communicate via the RS485 bus. Since the master MCU has a clock and the slave MCU also has a clock, and the two clocks have different clock domains and need to be synchronized, jitter will be generated. For example, if the master clock is fast and the slave clock is slow, the slave clock needs to speed up its own clock, but it can never adjust to a precise value, so a jitter of approximately ±2us will be generated.

[0037] For the slave module, the MCU and FPGA maintain synchronous communication through a periodic interrupt line, which is provided by the MCU to the FPGA. When the slave FPGA detects a rising edge, it generates a periodic interrupt signal, and then records and saves the planned logical position sent by the MCU to the FPGA. The number of pulses that need to be sent in the current cycle is the difference between the planned logical position of the current cycle and the planned logical position of the previous cycle, plus the sum of the number of pulses that need to be compensated in the current cycle. The extended pulse axis control method of this application is applicable to all motion control fields, not limited to the control field of PLC systems.

[0038] The control method of this application is described in detail below:

[0039] Please combine Figure 2 , Figure 2 This is a flow chart of an embodiment of the control method of the pulse controller of the present application, as shown in FIG. Figure 2 The control method of the pulse controller provided in this application includes the following steps:

[0040] S100, confirm whether a time interruption occurs in the current cycle.

[0041] Combine Figure 1 The MCU and FPGA of the slave station are connected through a pin. The MCU sends a high level to the FPGA through the pin at a fixed period (with slight jitter). When the FPGA detects a rising edge, it is equivalent to detecting a cycle interrupt.

[0042] S200: If it is confirmed that the current cycle is interrupted, determine whether the position information planned for the current cycle of the motor is equal to the actual position information.

[0043] Optionally, when it is detected that a time interruption occurs in the current cycle, it is necessary to determine whether the position information planned for the current cycle of the motor and the actual position information are equal. It will be understood that the position information of the motor in this application may include but is not limited to the planned logical position, the actual logical position and the actual cumulative logical position. In an embodiment of the present application, when it is detected that a time interruption occurs in the current cycle, it is determined whether the actual logical position of the current cycle of the motor is equal to the planned logical position of the previous cycle. If the actual logical position of the current cycle of the motor is equal to the planned logical position of the previous cycle, the position of the motor in the current cycle is not compensated. On the contrary, if the actual logical position of the current cycle is not equal to the planned logical position of the previous cycle, step S300 is entered to determine the number of pulses that need to be issued in the current cycle to compensate for the position of the motor based on the position information of the previous cycle and the current cycle of the motor, so that when the shaft stops, it is ensured that the actual logical position is equal to the planned logical position.

[0044] S300: If they are not equal, the number of pulses required to be sent in the current cycle is determined based on the position information of the motor in the previous cycle and the current cycle to compensate for the position of the motor.

[0045] Please further combine Figure 3 , Figure 3 This is a flow chart of an implementation method of step S300 of this application, as shown in FIG. Figure 3 Step S300 further includes the following sub-steps:

[0046] S310: Determine the number of pulses that need to be corrected in the current cycle based on the position information of the motor in the previous cycle and the position information of the current cycle.

[0047] Please further combine Figure 4 , Figure 4 This is a flow chart of an implementation of step S310 of this application, as shown in FIG. Figure 4 Step S310 further includes the following sub-steps:

[0048] S311, obtaining the planned logical position of the motor in the previous cycle and the logical position accumulated by the FPGA.

[0049] Specifically, the planned logic position P of the motor in the last cycle and the logic position P' accumulated by the FPGA in the last cycle are obtained.

[0050] S312: Calculate the number of pulses that need to be corrected in the current cycle according to the difference between the planned logic position and the accumulated logic position.

[0051] Furthermore, the number of pulses that need to be corrected in the current cycle is obtained based on the planned logical position P of the motor in the previous cycle and the logical position P' accumulated by the FPGA in the previous cycle. The expression is as follows:

[0052] ΔP=PP`

[0053] It is understandable that the number of pulses that were less or more than sent in the previous time period needs to be compensated in the current time period.

[0054] S320: Determine the number of pulses that need to be sent by the motor in the current cycle based on the number of pulses that need to be corrected to compensate for the position of the motor.

[0055] Please further combine Figure 5 , Figure 5 This is a flow chart of an implementation method of step S320 of this application, as shown in FIG. Figure 5 Step S320 further includes the following sub-steps:

[0056] S321, obtaining the planned logical position of the motor in the current cycle and the planned logical position of the motor in the previous cycle.

[0057] Furthermore, the planned logical position P2 of the motor in the current cycle and the planned logical position P of the motor in the previous cycle are obtained respectively.

[0058] S322, determining the difference between the planned logical position of the motor in the current cycle and the planned logical position in the previous cycle.

[0059] Furthermore, the difference between the planned logical position P2 of the motor in the current cycle and the planned logical position P of the motor in the previous cycle is obtained.

[0060] S323, obtaining the number of pulses that need to be sent by the motor in the current cycle according to the difference and the number of pulses that need to be corrected in the current cycle to compensate for the position of the motor.

[0061] According to the difference and the number of pulses that need to be corrected in the current cycle, the number of pulses that the motor needs to send in the current cycle is obtained to compensate the position of the motor P L

[0062] P L=P2-P+ΔP

[0063] Therefore, from the above formula, it can be seen that the number of pulses that need to be sent in the current cycle is the difference between the planned logical position of the current cycle and the planned logical position of the previous cycle plus the number of pulses that need to be corrected. This ensures that when the axis stops, the actual logical position of the motor is equal to the planned logical position.

[0064] Please further combine Figure 6 and Figure 7 , Figure 6 This is a curve diagram of the motor position information for this application. Figure 7 This is the internal logic diagram of the system of this application, in which Figure 6 The motor position information includes the planned logical position, the detailed logical position and the actual logical position. Figure 6 and Figure 7 Introducing the control method of this application:

[0065] 1. In the t1 cycle, the planned logical position is P = 100, and the actual number of pulses to be run in the current cycle is 100. At the end of the t1 cycle, due to the early arrival of the cycle interrupt, the actual counting logical position P` = 98, so ΔP = PP` = 100-98 = 2, and 2 pulses are missing. Therefore, these 2 pulses need to be compensated in the t2 cycle. The actual number of pulses sent in the t2 cycle is 102.

[0066] 2. In the t2 cycle, the planned logical position P = 200. The actual number of pulses to be run in the current cycle is 200-100 = 100. However, the two pulses that were less sent in the t1 cycle need to be compensated. Therefore, the number of pulses that need to be sent in the t2 cycle is 200-100+2=100+2=102. At the end of the t2 cycle, due to the delayed arrival of the cycle interrupt, the actual counting logical position P`=202, so ΔP=PP`=200-202=-2, and two pulses are sent too many. These two pulses need to be compensated in the t3 cycle. The actual number of pulses sent in the t3 cycle is 98.

[0067] 3. In the t3 cycle, the planned logical position P = 300. The actual number of pulses to be run in the current cycle is 300-200 = 100. However, the two extra pulses in the t2 cycle need to be compensated. Therefore, the number of pulses that need to be sent in the t3 cycle is 300-200-2 = 100-2 = 98. At the end of the t3 cycle, due to the early arrival of the cycle interrupt, the actual counting logical position P` = 298. Therefore, ΔP = PP` = 300-298 = 2, and two pulses are missing. These two pulses need to be compensated in the t4 cycle. The actual number of pulses sent in the t4 cycle is 102.

[0068] 4. In cycle t4, the planned logical position P = 400. The actual number of pulses to be run in the current cycle is 400-300 = 100. However, the two pulses that were missed in cycle t3 need to be compensated. Therefore, the number of pulses that need to be sent in cycle t4 is 400-300+2=100+2=102. At the end of cycle t3, due to the delayed arrival of the cycle interrupt, the actual counting logical position P`=402. Therefore, ΔP=PP`=400-402=-2, and two pulses are sent too many. These two pulses need to be compensated in cycle t5. The actual number of pulses sent in cycle t5 is 98.

[0069] 5. In cycle t5, the planned logical position P = 500. The actual number of pulses to be run in the current cycle is 500-400 = 100. However, the two extra pulses in cycle t4 need to be compensated. Therefore, the number of pulses to be sent in cycle t5 is 500-400-2 = 100-2 = 98. At the end of cycle t5, due to the early arrival of the cycle interrupt, the actual counted logical position P` = 498. Therefore, ΔP = PP` = 500-498 = 2. Two pulses are missing, and these two pulses need to be compensated in cycle t6. The actual number of pulses sent in cycle t6 is 102.

[0070] 6. In cycle t6, the planned logical position P = 500, which means the pulse axis needs to stop. The actual number of pulses expected in the current cycle is 500 - 500 = 0, meaning the axis needs to stop. However, the two pulses missing in cycle t5 need to be compensated. Therefore, the number of pulses required in cycle t6 is 500 - 500 + 2 = 0 + 2 = 2. At the end of cycle t6, the actual counted logical position P` = 500, so ΔP = PP` = 500 - 500 = 0. The pulses are sent just right, and the axis stops its entire motion without missing pulses.

[0071] In the above implementation, logical position counting is performed through the internal FPGA, and there is no need to add additional external encoder counting. When a cycle interruption is detected, it is determined whether the position information planned for the current cycle of the motor is equal to the actual position information, and then the number of pulses that need to be sent in the current cycle is determined based on the position information of the previous cycle and the current cycle, thereby realizing compensation operation for the position of the motor in the current cycle. It has high precision and strong stability, and can realize closed-loop control of the entire system.

[0072] In order to solve the above technical problems, the embodiment of the present application also provides a closed-loop control device for a pulse controller. Figure 8 , Figure 8 This is a schematic diagram of the structure of an embodiment of a closed-loop control device of a pulse controller of the present application, as shown in FIG. Figure 8The closed-loop control device 100 of the pulse controller provided in the present application includes a confirmation module 110 , a judgment module 120 and a compensation module 130 .

[0073] The confirmation module 110 is used to confirm whether a time interruption occurs in the current cycle.

[0074] The judgment module 120 is used to determine whether the planned position information of the motor in the current cycle is equal to the position information of the previous cycle when confirming that the current cycle is interrupted.

[0075] The compensation module 130 is used to determine the number of pulses required to be issued in the current cycle to compensate for the position of the motor based on the position information of the motor in the previous cycle and the current cycle when it is determined that the planned position information of the motor in the current cycle is not equal to the position information of the previous cycle.

[0076] It can be understood that the various modules of the closed-loop control device of the pulse controller in the present application are used to execute the steps in the first embodiment of the control method of the pulse controller mentioned above, which will not be repeated here.

[0077] In the above implementation, logical position counting is performed through the internal FPGA, and there is no need to add an external encoder count. When a cycle interruption is detected, the position information of the motor's current cycle is determined to be equal to the position information of the previous cycle, and then the number of pulses required to be issued in the current cycle is determined based on the position information of the previous cycle and the current cycle, thereby achieving compensation operation for the position of the motor in the current cycle. It has high precision and strong stability, and can achieve closed-loop control of the entire system. In order to solve the above technical problems, the embodiment of the present application also provides a computer device. For details, please refer to Figure 9 , Figure 9 This is a basic structural block diagram of the computer device in this embodiment.

[0078] The computer device 300 includes a memory 301, a processor 302, and a network interface 303 that are interconnected through a system bus. It should be noted that Figure 9Only a computer device 300 having components 301-303 is shown, but it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead. Among them, those skilled in the art will understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0079] The computer device may be a desktop computer, notebook computer, PDA, cloud server, etc. The computer device may interact with the user via a keyboard, mouse, remote control, touchpad, or voice control device.

[0080] The memory 301 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 301 may be an internal storage unit of the computer device 300, such as the hard disk or memory of the computer device 300. In other embodiments, the memory 301 may also be an external storage device of the computer device 300, such as a plug-in hard disk equipped on the computer device 300, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Of course, the memory 301 may also include both the internal storage unit of the computer device 300 and its external storage device. In this embodiment, the memory 301 is generally used to store the operating system and various application software installed on the computer device 300, such as computer-readable instructions for interface calling methods, etc. In addition, the memory 301 can also be used to temporarily store various data that has been output or is to be output.

[0081] In some embodiments, the processor 302 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 302 is generally used to control the overall operation of the computer device 300. In this embodiment, the processor 302 is used to execute computer-readable instructions or process data stored in the memory 301, such as computer-readable instructions for executing a control method for a pulse controller.

[0082] The network interface 303 may include a wireless network interface or a wired network interface. The network interface 303 is generally used to establish a communication connection between the computer device 300 and other electronic devices.

[0083] In the above implementation, logical position counting is performed through the internal FPGA, and there is no need to add additional external encoder counting. When a cycle interruption is detected, it is determined whether the position information planned for the current cycle of the motor is equal to the position information of the previous cycle, and then the number of pulses that need to be sent in the current cycle is determined based on the position information of the previous cycle and the current cycle, thereby realizing compensation operation for the position of the motor in the current cycle. It has high precision and strong stability, and can realize closed-loop control of the entire system.

[0084] The present application also provides another embodiment, namely, providing a computer-readable storage medium, which stores computer-readable instructions. The computer-readable instructions can be executed by at least one processor to enable at least one processor to perform the steps of the control method of the pulse controller as described above.

[0085] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of each embodiment of the present application.

[0086] Obviously, the embodiments described above are only some of the embodiments of the present application, rather than all of the embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned specific embodiments, or to make equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the present application specification and the accompanying drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present application.

Claims

1. A control method for a pulse controller, characterized in that: The control method includes: Check whether a time interruption occurs in the current cycle; If it is confirmed that the current cycle is interrupted, determine whether the position information of the motor planned for the current cycle is equal to the position information of the previous cycle; If they are not equal, the number of pulses that need to be corrected in the current cycle is determined based on the position information of the motor in the previous cycle and the position information of the current cycle, and the number of pulses that need to be issued in the current cycle of the motor is determined based on the number of pulses that need to be corrected to compensate for the position of the motor, wherein the number of pulses that need to be issued is the sum of the difference between the planned logical position of the current cycle and the planned logical position of the previous cycle and the corrected number of pulses.

2. The control method according to claim 1, characterized in that: The step of determining the number of pulses that need to be corrected in the current cycle based on the position information of the motor in the previous cycle and the position information of the current cycle includes: Obtain the planned logical position of the motor in the previous cycle and the accumulated logical position of the FPGA; The number of pulses that need to be corrected in the current cycle is obtained according to the difference between the planned logical position of the motor and the logical position accumulated by the FPGA.

3. The control method according to claim 1, wherein: The method of determining the number of pulses required to be sent by the motor in the current cycle according to the pulse number corrected as needed to compensate for the position of the motor includes: Obtaining the planned logical position of the motor in the current cycle and the planned logical position of the motor in the previous cycle; Determine the difference between the planned logical position of the motor in the current cycle and the planned logical position in the previous cycle; The number of pulses that need to be sent by the motor in the current cycle is obtained according to the difference and the number of pulses that need to be corrected in the current cycle to compensate for the position of the motor.

4. The control method according to claim 1, wherein: If it is determined that the position information of the motor in the current cycle is equal to the position information of the previous cycle, then there is no need to perform position compensation on the motor in the current cycle.

5. The control method according to claim 4, characterized in that: The position information of the motor in the current cycle is the actual logical position, and the position information of the motor in the previous cycle is the planned logical position.

6. The control method according to claim 1, characterized in that: The confirmation of whether an interrupt occurs in the current cycle is performed by judging whether a rising edge of a high level is detected in the current cycle.

7. A control device for a pulse controller, characterized in that: The control device comprises: Confirmation module, used to confirm whether a time interruption occurs in the current cycle; A judgment module, configured to determine whether the planned position information of the motor in the current cycle is equal to the position information of the previous cycle when confirming that the current cycle is interrupted; A compensation module is used to determine the number of pulses that need to be corrected in the current cycle based on the position information of the motor in the previous cycle and the position information of the current cycle when it is determined that the planned position information and the actual position information of the motor in the current cycle are not equal, and to determine the number of pulses that need to be issued in the current cycle of the motor based on the number of pulses that need to be corrected to compensate for the position of the motor, wherein the number of pulses that need to be issued is the sum of the difference between the planned logical position of the current cycle and the planned logical position of the previous cycle and the number of corrected pulses.

8. A computer device, characterized in that: The device comprises a memory and a processor, wherein the memory stores computer-readable instructions, and the processor implements the steps of the control method of the pulse controller according to any one of claims 1 to 6 when executing the computer-readable instructions.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the control method of the pulse controller according to any one of claims 1 to 6 are implemented.

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