A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a display area and a non-display area; the non-display area includes a detection area; a plurality of pads are provided in the detection area; the plurality of pads include a plurality of detection pads, a first virtual pad, and a second virtual pad; the display panel includes a substrate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the groove exposes the plurality of detection pads, the first virtual pad, and the second virtual pad; the first virtual pad and the second virtual pad are electrically connected through a connection line; the connection line includes a first portion, a second portion, and a third portion connected in sequence; the first portion is electrically connected to the first virtual pad; the third portion is electrically connected to the second virtual pad; both the first portion and the third portion are parallel to a first direction; the second portion is parallel to a second direction; at least the second portion is covered with an insulating layer. In the embodiment of the present invention, by covering at least the second portion of the connection line with an insulating layer, the wear rate of the connection line is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] The visual test (VT) of a display panel is a very important link in the process of manufacturing a display panel. After the display panel is manufactured and before bonding the driving chips, the data lines, gate lines, and common electrode lines are respectively connected to the corresponding test pads, and corresponding test signals are loaded through a test flexible circuit board to make the display panel display an image, so as to detect whether each transistor in the display panel is normal, and to detect whether the traces of each gate line and each data line are normal, preventing defective products from flowing into the module section and causing waste of costs.

[0003] In the prior art, there are two dummy pads in the test pads for testing in a display panel, and a connection line is connected between the dummy pads. The dummy pads are used to detect whether the gold fingers of the test flexible circuit board aligned with them are accurately aligned with the test pads. However, in the prior art, this connection line is generally directly exposed. Therefore, when the test flexible circuit board is aligned and bonded with the test pads, due to contact friction, the exposed connection line is likely to break, thereby affecting the accuracy of the detection result. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device to avoid breakage of the connection line and prevent misjudgment in the detection of the display panel.

[0005] Embodiments of the present invention provide a display panel, including: a display area and a non-display area; the non-display area includes a detection area; a plurality of pads are provided in the detection area; the plurality of pads include a plurality of detection pads, a first dummy pad, and a second dummy pad;

[0006] The display panel includes a substrate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the groove exposes the plurality of detection pads, the first dummy pad, and the second dummy pad;

[0007] The plurality of pads are arranged parallel to each other in a first direction and arranged in a second direction; the first direction and the second direction intersect; the first dummy pad and the second dummy pad are electrically connected through a connection line; the connection line includes a first portion, a second portion, and a third portion connected in sequence; the first portion is electrically connected to the first dummy pad; the third portion is electrically connected to the second dummy pad; both the first portion and the third portion are parallel to the first direction; the second portion is parallel to the second direction; at least the second portion is covered with an insulating layer.

[0008] In an embodiment of the present invention, an insulating layer is covered on at least a second part of the connection line between the first virtual pad and the second virtual pad. When the first virtual pad and the second virtual pad in the detection area are connected to the test flexible circuit board, although there will be friction during the alignment process between the test flexible circuit board and the first virtual pad and the second virtual pad, since an insulating layer is covered on at least a second part of the connection line connecting the first virtual pad and the second virtual pad, the second part that is most likely to break is protected by the insulating layer, so the probability of the connection line breaking can be reduced, and misjudgment of the alignment result caused by the test flexible circuit board can be prevented. Brief Description of the Drawings

[0009] Figure 1 is a schematic structural diagram of a display panel in the prior art;

[0010] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0011] Figure 3 is Figure 2 a schematic cross-sectional structure diagram of the provided display panel along the section line A - B;

[0012] Figure 4 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0013] Figure 5 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 6 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0015] Figure 7 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0016] Figure 8 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 9 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0018] Figure 10 is a schematic top view structure diagram of the detection area of a display panel provided by an embodiment of the present invention;

[0019] Figure 11 is a schematic top view structure diagram of the detection area of another display panel provided by an embodiment of the present invention;

[0020] Figure 12It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that for the sake of description, only the parts related to the present invention rather than all the structures are shown in the drawings.

[0022] A display panel provided by an embodiment of the present invention includes a display area and a non-display area; the non-display area includes a detection area; a plurality of pads are provided in the detection area; the plurality of pads include a plurality of detection pads, a first virtual pad, and a second virtual pad; the display panel includes a substrate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the groove exposes the plurality of detection pads, the first virtual pad, and the second virtual pad; the plurality of pads are arranged in parallel along a first direction and arranged along a second direction; the first direction and the second direction intersect; the first virtual pad and the second virtual pad are electrically connected through a connection line; the connection line includes a first part, a second part, and a third part connected in sequence; the first part is electrically connected to the first virtual pad; the third part is electrically connected to the second virtual pad; both the first part and the third part are parallel to the first direction; the second part is parallel to the second direction; at least the second part is covered with an insulating layer. The display panel provided by the embodiment of the present invention is provided with a groove in the detection area of the thin film transistor layer, the groove exposes the plurality of detection pads, the first virtual pad, and the second virtual pad, and at least the second part of the connection line between the first virtual pad and the second virtual pad is covered with an insulating layer. When the first virtual pad and the second virtual pad in the detection area are connected to the flexible circuit board of the display panel through the connection line, by covering at least the second part of the connection line with an insulating layer, the second part can be protected from being scratched or worn by external devices.

[0023] The above is the core idea of the present invention. Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] Figure 1 It is a schematic structural diagram of a display panel in the prior art, as Figure 1As shown, the display panel includes a display area 100, where multiple data signal lines 101 are provided. In the non-display area 200, multiple display pads 400 are provided, and the display pads 400 are correspondingly connected to the multiple data signal lines 101 (the specific connection is not shown). The display panel further includes a VT detection circuit 102, which includes multiple thin film transistors 301, a DO signal line, a DE signal line, and a SW signal line. The odd-numbered data signal lines 101 are connected to the DO signal line through the thin film transistors 301, and the even-numbered data signal lines 101 are connected to the DE signal line through the thin film transistors 301. The gates of the thin film transistors 301 are connected to the SW signal line. When performing VT detection on the display panel, a control signal is provided to the SW signal line through the detection pad 302, and a display signal is provided to the DO signal line and the DE signal line. The SW signal line controls the thin film transistors 301 to conduct, charges the odd-numbered data signal lines 101 through the DO signal line, and charges the even-numbered data signal lines 101 through the DE signal line to perform VT detection. The display pads 400 are used for subsequent bonding with the driving chip, and each detection pad 302 is connected in alignment with each gold finger of the test flexible circuit board. However, due to the small size of each detection pad 302 and the distance between each detection pad 302, it is easy to have an inaccurate alignment problem when aligning the detection pad 302 with each gold finger of the test flexible circuit board. If the position connection between the gold finger of the test flexible circuit board and the detection pad 302 is accurate, through the loaded test signal, it is possible to effectively detect whether each transistor, each gate line, and each data line in the display panel are normal; if the position connection is inaccurate, a short circuit is likely to occur after loading the test signal, thereby damaging the display panel. Therefore, two dummy pads 303 are also provided in the non-display area 200. The two dummy pads 303 are connected by a connection line 304. When the two dummy pads 303 are accurately aligned with the corresponding gold fingers of the test flexible circuit board, a loop is formed between the two dummy pads 303 and the test flexible circuit board. At this time, the external detection device can output a low level, indicating that the gold finger of the test flexible circuit board is accurately aligned with the detection pad 302. If the two dummy pads 303 are not aligned with the corresponding gold fingers of the test flexible circuit board, the two dummy pads 303 are open-circuited with the test flexible circuit board. At this time, the external detection device outputs a high level, indicating that the gold finger of the test flexible circuit board is not aligned with the detection pad 302. Since the connection line 304 between the detection pad 302 and the two dummy pads 303 is exposed, the connection line is easily broken when subjected to external friction. If the connection line 304 is broken, even if the two dummy pads 303 are accurately aligned with the corresponding gold fingers of the test flexible circuit board, a loop cannot be formed between the two dummy pads 303 and the test flexible circuit board, resulting in a misjudgment at this time.

[0025] Accordingly, an embodiment of the present invention provides a display panel to solve the problem that the connection lines between virtual pads are prone to breakage.

[0026] Figure 2 FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Figure 3 is Figure 2 FIG. 5 is a schematic cross-sectional structure of the provided display panel along the section line A-B, as Figure 2 and Figure 3 shown, the schematic structural diagram of the display panel provided by an embodiment of the present invention includes: a display area 10 and a non-display area 20; the non-display area 20 includes a detection area 30; a plurality of pads 300 are provided in the detection area 30; the plurality of pads 300 include a plurality of detection pads 310, a first virtual pad 320, and a second virtual pad 330. The plurality of pads 300 are arranged in parallel along a first direction Y and along a second direction X; the first direction Y and the second direction X intersect. The first virtual pad 320 and the second virtual pad 330 are electrically connected by a connection line 40; the connection line 40 includes a first part 41, a second part 42, and a third part 43 connected in sequence; the first part 41 is electrically connected to the first virtual pad 320; the third part 43 is electrically connected to the second virtual pad 330; both the first part 41 and the third part 43 are parallel to the first direction Y; the second part 42 is parallel to the second direction X. The plurality of detection pads 310 are used to transmit test signals loaded by a test flexible circuit board to the display panel, and the first virtual pad 320 and the second virtual pad 330 are used to test whether they are accurately aligned with the test flexible circuit board.

[0027] The display panel includes a substrate 50 and a thin film transistor layer 60; the thin film transistor layer 60 is provided with a groove 70 in the detection area 30; the groove 70 exposes the plurality of detection pads 310, the first virtual pad 320, and the second virtual pad 330. Since it is necessary to bind and connect the plurality of pads 300 to the test flexible circuit board during testing, it is necessary to perform a grooving process on the thin film transistor layer 60 in the detection area 30 to form the groove 70, and the groove 70 exposes the plurality of detection pads 310, the first virtual pad 320, and the second virtual pad 330. In order to conform to the development trend of narrow borders, the first part 41 and the third part 43 of the connection line 40 are set to be relatively short, and in contrast, the second part 42 is relatively long. Therefore, the second part 42 is more likely to be worn and broken. Therefore, in order to avoid misjudgment of detection caused by the breakage of the connection line 40, at least the second part 42 of the display panel provided by an embodiment of the present invention is covered with an insulating layer 44. Figure 2 and Figure 3 Exemplarily, the first part 41, the first part 42, and the third part 43 of the connection line 40 are all covered with an insulating layer 44. The connection line 40 is protected by the insulating layer 44 to avoid breakage caused by external friction and scratching.

[0028] It should be noted that in the embodiments of the present invention, the position of the detection area 30 in the non-display area 20 is not limited. For example, it can be set on both sides of the bonding pads of the driving chip, or only on one side. Figure 2 Exemplarily, a detection area 30 is arranged in the non-display area 20, and the number of detection areas 30 can be set to one or more according to actual situations. The embodiments of the present invention do not specifically limit the number of detection areas 30.

[0029] In addition, in the embodiments of the present invention, the arrangement order of the detection pads 310, the first virtual pad 320, and the second virtual pad 330 is not limited. Figure 2 Exemplarily, a detection pad 310 is arranged between the first virtual pad 320 and the second virtual pad 330. In other embodiments, the first virtual pad 320 and the second virtual pad 330 can also be arranged adjacent to each other or interspersed among multiple detection pads 310. For example, the first virtual pad 320 and the second virtual pad 330 are arranged closely, and there is no detection pad 310 between the first virtual pad 320 and the second virtual pad 330; multiple detection pads 310 are arranged between the first virtual pad 320 and the second virtual pad 330; all the detection pads 310 are arranged between the first virtual pad 320 and the second virtual pad 330, and so on.

[0030] Optionally, Figure 4 is a schematic cross-sectional structure diagram of another display panel provided by the embodiments of the present invention. Refer to Figure 4, the display panel includes a first metal layer 61 and a semiconductor layer 62. The semiconductor layer 62 is located between the first metal layer 61 and the substrate 50. An insulating layer 44 is also provided between the semiconductor layer 62 and the first metal layer 61. The semiconductor layer 62 includes an active layer 621 of the thin film transistor layer and a connection line 40. The connection line 40 is a heavily doped semiconductor layer. When forming the active layer 621 of the thin film transistor layer 60, the connection line 40 is formed using the same material. Since the connection line 40 needs to conduct electricity, the connection line 40 can be a heavily doped semiconductor layer. For example, after forming the active layer 621 of the thin film transistor layer 60 and the connection line pattern, the connection line 40 pattern is subjected to a heavy doping process. The first metal layer 61 includes a gate 611 of the thin film transistor layer 60 and a plurality of pads 300. The active layer 621 of the thin film transistor layer 60 and the connection line 40 are arranged in the same layer, and the plurality of pads 300 and the gate 611 of the thin film transistor layer 60 are arranged in the same layer, that is, in the same process, the active layer 621 of the thin film transistor layer and the connection line 40 are formed using the same material at the same time, and in the same process, the plurality of pads 300 and the gate 611 of the thin film transistor layer 60 are formed using the same material at the same time. This can not only reduce the overall thickness of the display device, but also the connection line 40 and the active layer 621 of the thin film transistor layer 60 only require one process when arranged in the same layer, and the plurality of pads 300 and the gate 611 of the thin film transistor layer 60 also only require one process when arranged in the same layer. Therefore, during the manufacturing process, both the first metal layer 61 and the semiconductor layer 62 only require one etching process and do not need to be masked and manufactured separately, saving costs, reducing the manufacturing process, improving production efficiency, and reducing process complexity.

[0031] It should be noted that the first metal layer 61 may include the gate 611 of the thin film transistor layer 60 and a plurality of pads 300, or may include the source / drain 612 of the thin film transistor layer 60 and a plurality of pads 300. The connection line 40 is connected to the first virtual pad 320 and the second virtual pad 330 by punching holes in the insulating layer 44. Figure 4 Exemplarily, the first metal layer 61 may include the gate 611 of the thin film transistor layer and a plurality of pads 300. In other embodiments, such as Figure 5 shown, it may also be set that the first metal layer 61 includes the source / drain 612 of the thin film transistor layer 60 and a plurality of pads 300. As Figure 4 shown, the insulating layer 44 between the first metal layer 61 and the semiconductor layer 62 is a gate insulating layer; as Figure 5 shown, the insulating layer 44 between the first metal layer 61 and the semiconductor layer 62 includes a gate insulating layer between the gate of the thin film transistor layer and the active layer and an interlayer insulating layer between the gate of the thin film transistor layer and the source / drain.

[0032] Optionally, the semiconductor layer 62 includes polysilicon. The semiconductor layer 62 can be formed, for example, by a low-temperature polysilicon process.

[0033] Optionally, refer to Figure 6 , Figure 6 which is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. As Figure 6 shown, the display panel includes a first metal layer 63 and a second metal layer 64; the first metal layer 63 is located between the substrate 50 and the second metal layer 64; the first metal layer 63 includes connection lines 40; the second metal layer 64 includes a plurality of pads 300; an insulating layer 44 is provided between the first metal layer 63 and the second metal layer 64, and the first metal layer 63 further includes a light-shielding layer 630 of the thin-film transistor layer.

[0034] The second metal layer 64 further includes a gate 641 of the thin-film transistor layer 60; or, includes source / drain electrodes 642 of the thin-film transistor layer 60. Figure 6 Exemplarily, it is shown that the second metal layer 64 can include a gate 641 of the thin-film transistor layer 60 and a plurality of pads 300. In other embodiments, as Figure 7 shown, it can also be arranged that the second metal layer 64 includes source / drain electrodes 642 of the thin-film transistor layer 60 and a plurality of pads 300.

[0035] Since the thin-film transistor layer 60 will undergo a photo-induced degradation effect under a strong light intensity, by providing a light-shielding layer 630 of the thin-film transistor layer 60 in the first metal layer 63, the photo-induced attenuation effect of the thin-film transistor under light is avoided, the photoelectric conversion rate of the thin-film transistor is improved, and thus the resolution of the display panel is improved. The light-shielding layer 630 and the connection lines 40 are formed of the same material in the same process, which can also reduce the number of masks, save costs, improve production efficiency, and reduce process complexity. The insulating layer 44 between the first metal layer 63 and the second metal layer 64 can include one or more insulating layers. As Figure 6 shown, the insulating layer 44 between the first metal layer 63 and the second metal layer 64 includes an insulating layer between the light-shielding layer 630 of the thin-film transistor layer and the active layer and a gate insulating layer between the active layer and the gate of the thin-film transistor layer. As Figure 7 shown, the insulating layer 44 between the first metal layer 63 and the second metal layer 64 includes an insulating layer between the light-shielding layer 630 of the thin-film transistor layer and the active layer, a gate insulating layer between the active layer and the gate of the thin-film transistor layer, and an interlayer insulating layer between the gate of the thin-film transistor layer and the drain of the thin-film transistor layer.

[0036] Optionally, refer to Figure 8 , Figure 8 which is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. As Figure 8As shown, the display panel includes a first metal layer 63 and a second metal layer 64; the first metal layer 63 is located between the substrate 50 and the second metal layer 64; an insulating layer 44 is provided between the first metal layer 63 and the second metal layer 64; the first metal layer 63 includes the gate 631 of the thin film transistor layer and the connection line 40; the second metal layer 64 includes the source / drain electrodes 642 of the thin film transistor layer and a plurality of pads 300.

[0037] By providing the gate 631 of the thin film transistor layer and the connection line 40 in the first metal layer 63, and providing the source / drain electrodes 642 of the thin film transistor layer and a plurality of pads 300 in the second metal layer 64. The gate 631 of the thin film transistor layer and the connection line 40 are formed of the same material in the same process. Similarly, the source / drain electrodes 642 of the thin film transistor layer and a plurality of pads 300 are formed of the same material in the same process, which can reduce the number of masks, save costs, improve production efficiency, and reduce process complexity. As Figure 8 shown, the insulating layer 44 between the first metal layer 63 and the second metal layer 64 includes the gate insulating layer between the active layer of the thin film transistor layer and the gate of the thin film transistor layer and the insulating layer between the gate of the thin film transistor layer and the source / drain electrodes of the thin film transistor layer.

[0038] Optionally, the first part 41, the second part 43, and the third part 42 are all covered with the insulating layer 44.

[0039] In an embodiment of the present invention, for example, the first part 41, the second part 42, and the third part 43 of the connection line 40 can be covered with the insulating layer 44 to avoid the phenomenon that the connection line 40 is broken due to the alignment friction during the connection and alignment process between the first virtual pad 320 and the second virtual pad 330 and the flexible printed circuit board, thereby improving the accuracy of the detection result.

[0040] Optionally, referring to Figure 9 , Figure 9 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. As Figure 9 shown, the display panel includes a first metal layer 65; the first metal layer 65 includes the connection line 40 and a plurality of pads 300; the first metal layer 65 further includes the gate, source / drain electrodes, or light-shielding layer of the thin film transistor layer.

[0041] It should be noted that, Figure 9Exemplarily, the first metal layer 65 includes connection lines 40, a plurality of pads 300, and the gate 652 of the thin film transistor layer 60, that is, the connection lines 40, the plurality of pads 300, and the gate 652 of the thin film transistor layer are all formed by the first metal layer 65. In other embodiments, the first metal layer 65 may also be provided to include connection lines 40, a plurality of pads 300, and the source / drain electrodes of the thin film transistor layer 60, or the first metal layer 65 includes connection lines 40, a plurality of pads 300, and a light-shielding layer, which will not be elaborated here.

[0042] Optionally, Figure 10 As shown in the top view structural schematic diagram of the detection area of a display panel provided by an embodiment of the present invention, a plurality of pads 300 need to be aligned with corresponding gold fingers on a test flexible circuit board. Therefore, a groove 70 needs to be provided to expose the plurality of pads 300. Therefore, the vertical projections of the plurality of pads 300 on the substrate 50 are all located within the vertical projection of the groove 70 on the substrate 50, so that the plurality of pads 300 can be in full alignment contact with the corresponding gold fingers on the test flexible circuit board.

[0043] Optionally, as Figure 10 shown, the boundary of the groove 70 may also coincide with a partial boundary of the plurality of pads 300. By setting the boundary of the groove 70 to coincide with a partial boundary of the plurality of pads 300, an insulating layer is covered on the entire connection line 40 to protect the connection line 40 from external frictional damage or scratches of the device.

[0044] Optionally, refer to Figure 11 , Figure 11 As shown in the top view structural schematic diagram of another detection area of a display panel provided by an embodiment of the present invention, as Figure 11 shown, the groove 70 exposes a part of the first portion 41 and a part of the second portion 42. In order to conform to the development trend of narrow borders, the first portion 41 and the third portion 43 of the connection line 40 are set to be relatively short, and the second portion 42 is relatively long. Therefore, the second portion 42 is more likely to be worn and broken. Therefore, in the embodiment of the present invention, as long as an insulating layer is covered on the second portion 42, the groove 70 can expose a part of the first portion 41 and a part of the second portion 42. In addition, due to possible errors in the preparation process of the groove 70, resulting in the deviation of the position of the groove 70, if the size of the groove 70 is too small, it is possible that the deviation of the position of the groove 70 in the process causes the groove 70 to fail to completely expose the plurality of pads 300. Therefore, the size of the groove 70 along the extension direction of the pad 300 can be set to be larger than the size of the pad 300. If the preparation process of the groove 70 is accurate, the groove 70 exposes a part of the first portion 41 and a part of the second portion 42. In addition, in order to make the gold fingers of the test FPC be in full contact with the plurality of pads 300, the opening of the groove 70 also needs to be appropriately increased. At this time, the groove 70 exposes a part of the first portion 41 and a part of the second portion 42.

[0045] Based on the above embodiments, Figure 12 is a schematic structural diagram of a display device provided by an embodiment of the present invention. Refer to Figure 12 , the display device may include the display panel 11 described in any embodiment of the present invention. It should be noted that the display device provided by the embodiment of the present invention may be a display device such as a computer, a television, a smart wearable device, etc., or other display devices. The embodiment of the present invention does not make special limitations on this.

[0046] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments may be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, it includes a display area and a non-display area; the non-display area includes a detection area; a plurality of pads are provided in the detection area; the plurality of pads include a plurality of detection pads, a first virtual pad, and a second virtual pad; the display panel includes a substrate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the groove exposes the plurality of detection pads, the first virtual pad, and the second virtual pad; the plurality of pads are arranged parallel to each other in a first direction and arranged in a second direction; the first direction and the second direction intersect; the first virtual pad and the second virtual pad are electrically connected through a connection line; the connection line includes a first part, a second part, and a third part connected in sequence; the first part is electrically connected to the first virtual pad; the third part is electrically connected to the second virtual pad; both the first part and the third part are parallel to the first direction; the second part is parallel to the second direction; the first part, the second part, and the third part are all covered with an insulating layer; the vertical projections of the plurality of pads on the substrate are located within the vertical projection of the groove on the substrate.

2. The display panel according to claim 1, characterized in that, the display panel includes a first metal layer and a semiconductor layer; the semiconductor layer is located between the first metal layer and the substrate; an insulating layer is further provided between the semiconductor layer and the first metal layer; the semiconductor layer includes the active layer of the thin film transistor layer and the connection line; the connection line is a heavily doped semiconductor layer; the first metal layer includes the gate of the thin film transistor layer and the plurality of pads; or, the first metal layer includes the source and drain electrodes of the thin film transistor layer and the plurality of pads.

3. The display panel according to claim 2, characterized in that, the semiconductor layer includes polysilicon.

4. The display panel according to claim 1, characterized in that, the display panel includes a first metal layer and a second metal layer; the first metal layer is located between the substrate and the second metal layer; the first metal layer includes the connection line; the second metal layer includes the plurality of pads; an insulating layer is provided between the first metal layer and the second metal layer; the first metal layer further includes the light-shielding layer of the thin film transistor layer; the second metal layer further includes the gate of the thin film transistor layer; or, includes the source and drain electrodes of the thin film transistor layer.

5. The display panel according to claim 1, characterized in that, the display panel includes a first metal layer and a second metal layer; the first metal layer is located between the substrate and the second metal layer; an insulating layer is provided between the first metal layer and the second metal layer; the first metal layer includes the gate of the thin film transistor layer and the connection line; the second metal layer includes the source and drain electrodes of the thin film transistor layer and the plurality of pads.

6. The display panel according to claim 1, characterized in that, the display panel includes a first metal layer; The first metal layer includes the connection lines and a plurality of the pads; The first metal layer further includes a gate, a source / drain electrode, or a light-shielding layer of the thin-film transistor layer.

7. The display panel according to claim 6, wherein, The groove exposes a part of the first portion and a part of the second portion.

8. The display panel according to claim 1, wherein, A boundary of the groove coincides with a partial boundary of the plurality of pads.

9. A display device, wherein, It includes the display panel according to any one of claims 1-8.

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