Display device

Abstract

Embodiments of the present disclosure relate to a display device. In particular, embodiments of the present disclosure can provide a display device including a sub-pixel including a light emitting device and a drive transistor DRT electrically connected to a first electrode of the light emitting device and configured to drive the light emitting device, and a reference voltage line electrically connected to the sub-pixel SP and applying an initialization voltage to the first electrode of the light emitting device, wherein a voltage level of the initialization voltage is changed according to a length of a blank period. Accordingly, a display device having improved image display quality at a low refresh rate in a variable refresh rate mode can be provided.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0150126, filed on November 3, 2021, which is incorporated herein by reference as fully set forth herein for all purposes. Technical Field

[0003] Embodiments of this disclosure relate to display devices. Background Technology

[0004] With the development of the information society, the demand for various forms of display devices for displaying images is constantly increasing, and various display devices such as liquid crystal displays and organic light-emitting diode displays are being utilized.

[0005] Display devices are used to display images of various content. For example, display devices can display images of various content such as broadcasts, movies, and games.

[0006] Furthermore, unlike broadcasts and movies, users watching game images may expect rapid frame changes. Therefore, some display devices are designed to support Variable Refresh Rate (VRR) modes, which can drive refresh rates from low to high. Summary of the Invention

[0007] Embodiments of this disclosure can provide a display device with improved image display quality in a variable refresh rate mode.

[0008] Embodiments of this disclosure can provide a display device with improved performance of low grayscale images at low refresh rates.

[0009] Embodiments of this disclosure may provide a display device comprising: a sub-pixel including a light-emitting device and a driving transistor electrically connected to a first electrode of the light-emitting device and configured to drive the light-emitting device; and a reference voltage line electrically connected to the sub-pixel and applying an initialization voltage to the first electrode of the light-emitting device, wherein the voltage level of the initialization voltage varies according to the length of a blank period.

[0010] According to embodiments of this disclosure, a display device with improved image display quality in a variable refresh rate mode can be provided.

[0011] According to embodiments of this disclosure, a display device can be provided that has improved performance of low grayscale images at low refresh rates. Attached Figure Description

[0012] Figure 1 is a schematic configuration block diagram of a display device according to the present disclosure.

[0013] Figure 2 is a diagram for explaining a display device according to the present disclosure.

[0014] Figure 3 schematically illustrates a sub-pixel structure of a display device according to the present disclosure and a configuration for compensating for a characteristic value of a sub-pixel.

[0015] Figure 4 is exemplarily illustrated a change in frame rate over time in a certain mode.

[0016] Figure 5 is a diagram for explaining driving of a display panel when a vertical synchronization mode (VSYNC mode) is on.

[0017] Figure 6 is a diagram for explaining an example of a frame lag occurring when a vertical synchronization mode (VSYNC mode) is on.

[0018] Figure 7 is a diagram for explaining a tearing phenomenon occurring when a vertical synchronization mode (VSYNC mode) is off.

[0019] Figure 8 is a diagram for explaining a tearing phenomenon.

[0020] Figure 9 is a diagram for explaining an embodiment in which a display panel is driven in a variable refresh rate mode when a vertical synchronization mode (VSYNC mode) is off.

[0021] Figure 10 is illustrated a frame period in each of a first mode in which a display device is driven in a fixed refresh rate mode and a second mode in which the display device is driven in a variable refresh rate mode, based on a data enable signal DE.

[0022] Figure 11 is a diagram for explaining a relationship between a length of a blank period and a voltage difference between a first node and a second node of a driving transistor.

[0023] Figure 12 is a diagram for exemplarily explaining a black defect phenomenon in which a display panel recognizes a black in a low refresh rate in a variable refresh rate mode.

[0024] Figure 13 is a diagram for describing a process of compensating for a first initialization voltage in a display device according to an embodiment of the present disclosure.

[0025] Figure 14This is a diagram illustrating the monitoring sub-pixel MSP and the monitoring sub-pixel sensing voltage in a display device according to an embodiment of the present disclosure.

[0026] Figure 15 It is a diagram used to describe the process in which a timing controller controls a power management circuit to change the voltage value of a first initialization voltage based on a reference refresh rate value and a reference sense voltage value at the reference refresh rate value.

[0027] Figure 16 This illustration schematically shows the difference between displaying a general image and displaying a gaming image in a display device according to this disclosure.

[0028] Figure 17 An exemplary illustration shows a display device according to an embodiment of the present disclosure displaying all black in a variable refresh rate mode. Detailed Implementation

[0029] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and in the drawings, the same reference numerals and symbols may be used to refer to the same or similar components even when the same or similar components are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein may render the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” “composed of,” and “formed from” as used herein are generally intended to allow for the addition of additional components unless the term is used in conjunction with “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0030] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0031] When referring to the first element and the second element as "connected or coupled," "in contact or overlapping," etc., it should be interpreted that the first element can not only be "directly connected or coupled" or "directly contact or overlap" with the second element, but also that a third element can be "inserted" between the first element and the second element, or that the first element and the second element can be "connected or coupled," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can include at least one of two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0032] When time-related terms such as "after," "subsequently," "next," "before," or the like are used to describe a process or operation of elements or configurations or a flow or step in an operation, process, or manufacturing method, these terms can be used to describe a non-sequential or non-continuous process or operation, unless used with the term "directly" or "immediately."

[0033] Furthermore, when referring to any dimension, relative size, or the like, it should be considered that the numerical value or the corresponding information of the element or feature (e.g., level, range, or the like) includes a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, or the like), even when the relevant description is not specified. In addition, the term "may" completely covers all meanings of the term "can."

[0034] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a schematic configuration block diagram of a display apparatus 100 according to the present disclosure.

[0036] Referring to Figure 1 , the display apparatus 100 according to the present disclosure can include a main control apparatus 110 for controlling the operation of the display apparatus 100 according to an external input, and a display panel 130 for displaying image data provided from the main control apparatus 110, and a driving circuit 120 for driving the display panel 130. The main control apparatus 110 can also be referred to as a system on chip (SoC) apparatus.

[0037] In the display apparatus 100 according to the present disclosure, the main control apparatus 110 can include a system memory, a central processing unit (CPU), an interrupt controller, and a transceiver (Tx / Rx), a memory controller, an image generator, and a display controller.

[0038] The system memory in the main control apparatus 110 can store commands, parameters, and the like required for the operation of the driving circuit 120. For example, the CPU can operate using the commands and parameters stored in the system memory.

[0039] The CPU in the main control apparatus 110 can control the operation of the main control apparatus 110 as a whole. For example, the CPU can control the operation of the system memory, the interrupt controller, the transceiver, the memory controller, the image generator, and the display controller. In addition, the CPU can request the image generator to generate or process an image.

[0040] The interrupt controller in the main control device 110 can control the overall operation of the main control device 110. That is, the interrupt controller can receive interrupts from each component, adjust the execution order of each interrupt, and transmit information to the CPU to perform an operation corresponding to the interrupt.

[0041] The transceiver in the main control device 110 can transmit commands, signals, interrupts, and data converted according to various interface standards to the driving circuit 120, or can receive commands, signals, interrupts, and data converted according to various interface standards from the driving circuit 120. The transceiver in the main control device 110 can provide image data stored in an external memory to a source driving integrated circuit through a timing controller of the driving circuit 120.

[0042] The memory controller in the main control device 110 can control an external memory when transmitting and receiving data from and to the external memory connected to the main control device 110. That is, the memory controller can read, write, and delete image data by accessing the external memory according to the request of the CPU, the image generator, or the display controller.

[0043] The image generator in the main control device 110 can read and execute program commands related to graphic processing under the control of the CPU, and can generate or process an image. Such an image generator can be implemented as a graphic engine, a graphic processing unit (GPU), a graphic accelerator, 2D, etc.

[0044] The display controller in the main control device 110 can control the operation of the main control device 110 with respect to the driving circuit 120, or control the operation of the driving circuit 120 with respect to the main control device 110. For example, the display controller can control the memory controller to output data stored in the external memory through the transceiver. In addition, the display controller can control the image generator so that image data generated by the image generator is output through the transceiver.

[0045] The system bus in the main control device 110 can serve as a path for data transmission / reception between each component by connecting each component of the main control device 110. The system bus can include a small bus for data communication between components.

[0046] The main control device 110 can be referred to as an integrated circuit (IC), a processor, an application processor, a multimedia processor, or an integrated multimedia processor, etc.

[0047] Figure 2 FIG. 1 is a diagram for explaining a display device 100 according to the present disclosure.

[0048] Referring to Figure 2A display device according to the disclosure can include a display panel 130 and a driving circuit 120 for driving the display panel 130.

[0049] Signal lines such as a plurality of data lines DL and a plurality of gate lines GL can be disposed on the display panel 130 and on a substrate. A plurality of sub-pixels SP electrically connected to the plurality of data lines DL and the plurality of gate lines GL can be disposed on the display panel 130.

[0050] The display panel 130 can include a display area AA in which an image is displayed and a non-display area NA in which an image is not displayed. In the display panel 130, a plurality of sub-pixels SP for displaying an image are disposed in the display area AA, and a data driving circuit 220 and a gate driving circuit 230 are mounted in the non-display area NA. Alternatively, a pad portion connected to the data driving circuit 220 or the gate driving circuit 230 can be disposed.

[0051] One or more monitoring sub-pixels in which an image is not displayed can be located in the non-display area NA of the display panel 130.

[0052] In a case where two or more dummy sub-pixels are located on the display panel 130, the two or more monitoring sub-pixels can be located on the dummy line 210.

[0053] The monitoring sub-pixel can receive a data signal from the data line DL and can receive a gate signal from the gate line GL.

[0054] The monitoring sub-pixel can not include a light emitting device. Accordingly, the monitoring sub-pixel does not emit light.

[0055] The monitoring sub-pixel can be located outside the display area AA. For example, the monitoring sub-pixel can be located on an upper side of the display panel 130 adjacent to the data driving circuit 220 and / or on a lower side of the display panel 130 farthest from the data driving circuit 220.

[0056] The dummy line 210 can be disposed in the display panel 130 in a direction parallel to the plurality of gate lines GL.

[0057] The data driving circuit 220 is a circuit configured to drive the plurality of data lines DL and can supply a data signal to the plurality of data lines DL. The gate driving circuit 230 is a circuit configured to drive the plurality of gate lines GL and can supply a gate signal to the plurality of gate lines GL. The timing controller 240 can supply a data driving timing control signal DCS to the data driving circuit 220 to control an operation timing of the data driving circuit 220. The timing controller 240 can supply a gate driving timing control signal GCS for controlling an operation timing of the gate driving circuit 230 to the gate driving circuit 230.

[0058] The timing controller 240 can start scanning according to the timing implemented in each frame, and convert input image data inputted from the outside according to a data signal format used by the data driving circuit 220, supply the converted image data DATA to the data driving circuit 220, and control the data driving at an appropriate time according to the scanning.

[0059] The timing controller 240 can receive various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input image data enable signal DE, and a clock signal CLK, and input image data from the outside (e.g., the main control device 110) of the display device 100. Figure 1

[0060] In order to control the data driving circuit 220 and the gate driving circuit 230, the timing controller 240 can receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, a clock signal CLK, and the like, and can generate various control signals (e.g., DCS, GCS, and the like) to output to the data driving circuit 220 and the gate driving circuit 230.

[0061] The timing controller 240 can output various gate driving timing control signals GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like, in order to control the gate driving circuit 230.

[0062] The timing controller 240 can output various data driving timing control signals DCS including a source start pulse SSP, a source sampling clock SSC, and the like, in order to control the data driving circuit 220.

[0063] The data driving circuit 220 receives image data DATA from the timing controller 240, and drives a plurality of data lines DL.

[0064] The data driving circuit 220 can include one or more source driving integrated circuits SDIC.

[0065] Each source driving integrated circuit SDIC can be connected to the display panel 130 by a tape automated bonding (TAB) method, or can be connected to a bonding pad of the display panel 130 by a chip on glass (COG) method, or can be implemented as electrically connected to the display panel 130 by a chip on film (COF) method.

[0066] The gate driving circuit 230 can output a gate signal having an on-level voltage or a gate signal having an off-level voltage under the control of the timing controller 240. The gate driving circuit 230 can drive a plurality of gate lines GL by supplying a gate signal having an on-level voltage to the plurality of gate lines GL.

[0067] ​The gate driving circuit 230 can be connected to the display panel 130 through a tape automated bonding (TAB) method, or can be connected to a bonding pad of the display panel 130 through a chip on glass (COG) method or a chip on panel (COP) method, or can be electrically connected to the display panel 130 according to a chip on film (COF) method.

[0068] The gate driving circuit 230 can be formed in a panel-in-gate (GIP) type in the non-display area NA of the display panel 130. The gate driving circuit 230 can be disposed on or connected to the substrate of the display panel 130. In the case of the panel-in-gate (GIP) type, the gate driving circuit 230 can be disposed in the non-display area NA of the substrate. In the case of the chip on glass (COG) method or the chip on film (COF) method, the gate driving circuit 230 can be connected to the substrate of the display panel 130.

[0069] If a certain gate line GL is turned on by the gate driving circuit 230, the data driving circuit 120 can convert image data DATA received from the timing controller 240 into an analog data voltage to be supplied to the plurality of data lines DL.

[0070] The data driving circuit 220 can be connected to one side (e.g., an upper side or a lower side) of the display panel 130. Depending on a driving method, a panel design method, etc., the data driving circuit 220 can be connected to both sides (e.g., an upper side and a lower side) of the display panel 130, or can be connected to two or more sides among four sides of the display panel 130.

[0071] The gate driving circuit 230 can be connected to one side (e.g., a left side or a right side) of the display panel 130. Depending on a driving method, a panel design method, etc., the gate driving circuit 230 can be connected to both sides (e.g., a left side and a right side) of the display panel 130, or can be connected to two or more sides among four sides of the display panel 130.

[0072] The timing controller 240 can be a timing controller used in a conventional display technology, or can be a control device including a timing controller that is also capable of performing other control functions, or can be a circuit within a control device. The timing controller 240 can be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0073] The timing controller 240 can be mounted on a printed circuit board (PCB), a flexible printed circuit board (FPCB), etc., and can be electrically connected to the data driving circuit 220 and the gate driving circuit 230 through the printed circuit board (PCB), the flexible printed circuit board (FPCB), etc.

[0074] The timing controller 240 can transmit or receive a signal to or from the data driving circuit 220 according to one or more predetermined interfaces. Here, for example, the interface can include a low voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0075] The timing controller 240 can include a storage medium such as one or more registers.

[0076] The display device 100 according to an embodiment of the disclosure can be a display device including a liquid crystal display (LCD) device having a backlight unit, or can be a self-emissive display device such as an organic light-emitting diode (OLED) display, a quantum dot display, and a micro light-emitting diode (micro-LED) display.

[0077] In the case where the display device 100 according to an embodiment of the disclosure is an OLED display, each sub-pixel SP can include an organic light-emitting diode (OLED) that emits light as a light-emitting device. If the display device 100 according to an embodiment of the disclosure is a quantum dot display, each sub-pixel SP can include a light-emitting device made of a quantum dot, which is a semiconductor crystal that emits light by itself. In the case where the display device according to an embodiment of the disclosure is a micro-LED display, each sub-pixel SP can include a micro-LED as a light-emitting device, which emits light by itself and is made of an inorganic material.

[0078] Figure 3 FIG. 1 is a diagram briefly illustrating a structure of a sub-pixel SP of a display device according to an embodiment of the disclosure and a configuration for compensating for a characteristic value of the sub-pixel SP.

[0079] Referring to Figure 3 Each of the plurality of sub-pixels SP can include a light-emitting device ED, a driving transistor DRT, a scan transistor SCT, and a storage capacitor Cst.

[0080] The light-emitting device ED can include a first electrode and a second electrode and a light-emitting layer EL between the first electrode and the second electrode.

[0081] The first electrode of the light-emitting device ED is a pixel electrode PE, and the second electrode of the light-emitting device ED is a common electrode CE.

[0082] The pixel electrode PE of the light emitting device ED can be an electrode provided in each of the sub-pixels SP, and the common electrode CE can be an electrode commonly provided in all of the sub-pixels SP. Here, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Alternatively, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0083] For example, the light emitting device ED can be an organic light emitting diode OLED, a light emitting diode LED, or a quantum dot light emitting device.

[0084] The driving transistor DRT is a transistor for driving the light emitting device ED, and can include a first node N1, a second node N2, a third node N3, etc.

[0085] The first node N1 of the driving transistor DRT can be a gate node of the driving transistor DRT, and can be electrically connected to a source node or a drain node of the scan transistor SCT. The second node N2 of the driving transistor DRT can be a source node or a drain node of the driving transistor DRT, and can be electrically connected to a source node or a drain node of the sensing transistor SENT and the light emitting device ED, and the second node N2 of the driving transistor DRT can also be electrically connected to the pixel electrode PE of the light emitting device ED. The third node N3 of the driving transistor DRT can be electrically connected to a driving voltage line DVL that supplies a high potential driving voltage EVDD.

[0086] The scan transistor SCT can be controlled by a scan pulse SCAN that is one type of gate signal, and can switch electrical connection between the first node N1 of the driving transistor DRT and the data line DL. That is, the scan transistor SCT can be turned on or off according to the scan pulse SCAN supplied from the scan line SCL that is one type of gate line GL, and can control electrical connection between the data line DL and the first node N1 of the driving transistor DRT.

[0087] The scan transistor SCT can be turned on by the scan pulse SCAN having an on level voltage, and can transfer a data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0088] Here, in the case where the scan transistor SCT is an n-type transistor, the on level voltage of the scan pulse SCAN can be a high level voltage. If the scan transistor SCT is a p-type transistor, the on level voltage of the scan pulse SCAN can be a low level voltage.

[0089] The storage capacitor Cst can be electrically connected to the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of electric charge corresponding to a voltage difference between both ends, and functions to maintain the voltage difference between both ends for a predetermined frame time. Accordingly, the corresponding sub-pixel SP can emit light during the predetermined frame time.

[0090] Referring to Figure 3 Each of the plurality of sub-pixels SP disposed on the display panel 130 of the display device 100 according to the embodiment of the disclosure can further include a sensing transistor SENT.

[0091] The sensing transistor SENT can be controlled by a sensing pulse SENSE which is a type of gate signal, and can be electrically connected to the second node N2 of the driving transistor DRT and a reference voltage line RVL. That is, the sensing transistor SENT is turned on or off according to the sensing pulse SENSE supplied from a sensing line SENL which is another type of gate line GL, and can switch the electrical connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0092] The second node N2 of the driving transistor DRT is also referred to as a sensing node.

[0093] The sensing transistor SENT can be turned on by the sensing pulse SENSE having an on level voltage, and can deliver an initialization voltage VpreR, VpreS, etc. supplied from the reference voltage line RVL to the second node N2 of the driving transistor DRT. The reference voltage line RVL is also referred to as a sensing line.

[0094] The first initialization switch RPRE can switch the electrical connection between the reference voltage line RVL and an initialization voltage supply node NpreR. The first initialization switch RPRE includes one end portion electrically connected to the reference voltage line RVL and the other end portion electrically connected to the first initialization voltage supply node NpreR.

[0095] The first initialization voltage VpreR is applied to the first initialization voltage supply node NpreR.

[0096] The second initialization switch SPRE can switch the electrical connection between the reference voltage line RVL and a second initialization voltage supply node NpreS. The second initialization switch SPRE includes one end portion electrically connected to the reference voltage line RVL and the other end portion electrically connected to the second initialization voltage supply node NpreS.

[0097] The second initialization voltage VpreS is applied to the second initialization voltage supply node NpreS. The voltage level of the second initialization voltage VpreS can be different from the voltage level of the first initialization voltage VpreR.

[0098] The first initialization voltage VpreR can be a voltage input for initializing the voltage of the second node N2 of the driving transistor DRT when the data voltage Vdata for image display is input to the data line DL. For example, the data voltage Vdata for image display is supplied to the first node N1 of the driving transistor DRT, and the first initialization voltage VpreR is supplied to the second node N2 of the driving transistor DRT, so that a potential difference can be generated at both ends of the storage capacitor Cst.

[0099] The second initialization voltage VpreS can be a voltage input for initializing the voltage of the second node N2 of the driving transistor DRT when a voltage for sensing a characteristic value of the sub-pixel SP is input to the data line DL. For example, the voltage Vdata for sensing a characteristic value of the sub-pixel SP is supplied to the first node N1 of the driving transistor DRT, and the second initialization voltage VpreS can be supplied to the second node N2 of the driving transistor DRT, so that a potential difference can be generated between both ends of the storage capacitor Cst.

[0100] As described above, the reference voltage line RVL can apply the first initialization voltage VpreR or the second initialization voltage VpreS to the sub-pixel SP. Similarly, a voltage source that supplies the first initialization voltage VpreR can apply the first initialization voltage VpreR to the sub-pixel SP. A voltage source that supplies the second initialization voltage VpreS can apply the second initialization voltage VpreS to the sub-pixel SP. The voltage source for applying the first initialization voltage VpreR and / or the second initialization voltage VpreS to the sub-pixel SP can be, for example, a power management circuit.

[0101] The sensing transistor SENT can be turned on by the sensing pulse SENSE having an on-level voltage, and transfer the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0102] Here, if the sensing transistor SENT is an n-type transistor, the on-level voltage of the sensing pulse SENSE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-level voltage of the sensing pulse SENSE can be a low-level voltage.

[0103] The function of the sensing transistor SENT for transferring the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used when driving to sense a characteristic value of the sub-pixel SP. In this case, the voltage transferred to the reference voltage line RVL can be a voltage for calculating a characteristic value of the sub-pixel SP or a voltage reflecting a characteristic value of the sub-pixel SP.

[0104] Each of the drive transistor DRT, the scan transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In an embodiment of the disclosure, for ease of description, each of the drive transistor DRT, the scan transistor SCT, and the sensing transistor SENT is an n-type, as an example.

[0105] The storage capacitor Cst can not be a parasitic capacitor (e.g., Cgs, Cgd) as an internal capacitor between the gate node and the source node (or the drain node) of the drive transistor DRT, but can be an external capacitor intentionally designed outside the drive transistor DRT.

[0106] The scan line SCL and the sensing line SENL can be different gate lines GL. In this case, the scan pulse SCAN and the sensing pulse SENSE can be separate gate signals, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be independent. That is, the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be the same or different.

[0107] Alternatively, the scan line SCL and the sensing line SENL can be the same gate line GL. That is, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP can be connected to one gate line GL. In this case, the scan pulse SCAN and the sensing pulse SENSE can be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be the same.

[0108] Figure 3 The structure of the sub-pixel SP shown is only an example, and various modifications can be made by further including one or more transistors or further including one or more capacitors.

[0109] In addition, in Figure 3 , the sub-pixel SP structure is described assuming that the display device 100 is a self-emissive display device. However, in the case of the display device 100 being a liquid crystal display device, each sub-pixel SP can include a transistor and a pixel electrode.

[0110] Referring to Figure 3 , the display device 100 according to the disclosure can include a line capacitor Crvl. The line capacitor Crvl can be a capacitor element electrically connected to one end of the reference voltage line RVL, or a parasitic capacitor formed on the reference voltage line RVL.

[0111] Referring toFigure 3 The source driving integrated circuit SDIC can further include an analog-digital converter ADC and a sampling switch SAM.

[0112] The reference voltage line RVL can be electrically connected to the analog-digital converter ADC. The analog-digital converter ADC can sense a voltage of the reference voltage line RVL. The voltage sensed by the analog-digital converter ADC can be a voltage reflecting a characteristic value of the sub-pixel SP.

[0113] In the disclosure, the characteristic value of the sub-pixel SP can be a characteristic value of the driving transistor DRT or the light emitting device ED. The characteristic value of the driving transistor DRT can include a threshold voltage and a mobility of the driving transistor DRT. The characteristic value of the light emitting device ED can include a threshold voltage of the light emitting device ED.

[0114] The analog-digital converter ADC can receive an analog voltage, convert the analog voltage into a digital value, and output the digital value to the timing controller 240.

[0115] The sampling switch SAM can be located between the analog-digital converter ADC and the reference voltage line RVL. The sampling switch SAM can switch electrical connection between the reference voltage line RVL and the analog-digital converter ADC.

[0116] The timing controller 240 can include a memory 310 storing characteristic value information of the sub-pixel SP, and a compensation circuit 320 for performing a calculation for compensating for a change in the characteristic value of the sub-pixel SP based on the information stored in the memory 310.

[0117] The information for compensating for the characteristic value of the sub-pixel SP can be stored in the memory 310. For example, information on a threshold voltage and a mobility of the driving transistor DRT of each of a plurality of sub-pixels SP and a threshold voltage of the light emitting device ED included in the sub-pixel SP can be stored in the memory 310.

[0118] The information on the threshold voltage of the light emitting device ED can be stored in a look-up table LUT of the memory 310.

[0119] The compensation circuit 320 can calculate a degree of change in the characteristic value of the sub-pixel SP based on the digital value input from the analog-digital converter ADC and the characteristic value information of the sub-pixel SP stored in the memory 310. The compensation circuit 320 can update the characteristic value of the sub-pixel SP stored in the memory 310.

[0120] The timing controller 240 can drive the data driving circuit 220 by reflecting the change in the characteristic value of the sub-pixel SP calculated by the compensation circuit 320 and compensating for the image data.

[0121] A data signal Vdata reflecting a change in a characteristic value of the sub-pixel SP can be output to a corresponding data line DL through a digital-to-analog converter DAC.

[0122] The above-described process of sensing and compensating for a change in a characteristic value of the sub-pixel SP is also referred to as a "sub-pixel characteristic value compensation process".

[0123] Figure 4 It is exemplarily shown that a frame rate varies with time in a certain mode.

[0124] Referring to Figure 4 In a certain mode, a frame rate can vary depending on time. The certain mode can be, for example, a game mode for displaying an image of a game or a game image.

[0125] A frame rate, also referred to as frames per second (FPS), can be defined as the number of frames displayed on a display device within 1 second.

[0126] When a general broadcast image is received and displayed on a display panel, a frame rate can be constant at 24 fps, 30 fps, or the like. However, in the case of a game mode, a frame rate can vary with time depending on a user's movement in a game.

[0127] Referring to Figure 4 , a frame rate can be higher or lower than 60 fps depending on time.

[0128] Figure 5 is a diagram for explaining driving of a display panel when a vertical synchronization mode (VSYNC mode) is turned on.

[0129] A vertical synchronization mode (VSYNC mode) can mean a mode in which a main control device 110 starts to generate timing of an image of a next frame is synchronized with timing of outputting an image of a corresponding frame by a display panel 130.

[0130] Referring to Figure 5 , the display panel 130 can be driven in a case where a vertical synchronization mode (VSYNC mode) is turned on.

[0131] In a state where the vertical synchronization mode (VSYNC mode) is turned on, the display panel 130 displays an image according to timing of a vertical synchronization signal Vsync. For example, the vertical synchronization signal Vsync can include a first voltage level (e.g., a high level) application period having a preset length and a second voltage level (e.g., a low level) application period having a preset length.

[0132] For example, a period in which the vertical synchronization signal Vsync is applied at the first voltage level can correspond to an active period in which a data voltage for displaying an image is applied to the display panel 130. A period in which the vertical synchronization signal Vsync is applied at the second voltage level can correspond to a blank period between the active periods.

[0133] Referring to Figure 5 In the state in which the vertical synchronization mode is on, the display panel 130 can display an image of a corresponding frame according to a timing in which the vertical synchronization signal Vsync is switched from the second voltage level to the first voltage level.

[0134] An image processed by the main control device 110 is displayed on the display panel 130, and the display panel 130 displays the image according to a timing of the vertical synchronization signal Vsync.

[0135] In the state in which the vertical synchronization mode is on, when the signal level of the vertical synchronization signal Vsync is at a high level, even if the processing of a next frame image in the main control device 110 is completed, an image of a corresponding frame is displayed on the display panel 130, and an image of the next frame is not displayed on the display panel 130.

[0136] In the state in which the vertical synchronization mode is on, even if the image processing speed of the main control device 110 is fast, the timing in which the main control device 110 starts to process an image cannot be faster. Accordingly, in the state in which the vertical synchronization mode is on, the length of the blank period can be the same for each frame.

[0137] Referring to Figure 5 , the main control device 110 processes an image of an Nth frame (frame N) when the signal level of the vertical synchronization signal Vsync is at a high level. Then, the display panel 130 starts to process an image of an (N+1)th frame (frame N+1) according to a timing in which the image of the Nth frame (frame N) is displayed.

[0138] Figure 6 is a diagram for explaining an example in which a frame lag occurs when the vertical synchronization mode is on.

[0139] Referring to Figure 6 If the image processing speed of the main control device 110 is slow when the vertical synchronization mode is on, even if a frame is changed, the display panel 130 displays an image of a previous frame as it is.

[0140] Accordingly, although frames are switched by the vertical synchronization signal Vsync, a frame lag phenomenon in which the same image is displayed in the display panel 130 can still occur.

[0141] That is, if the image processing speed of the main control device 110 is slow when the vertical synchronization mode is on, frame lag can occur, and thus the timing at which the main control device 110 processes the image of the next frame is also delayed.

[0142] This frame lag can be particularly problematic in a game mode environment that requires a fast response according to frame switching.

[0143] Figure 7 FIG. 1 is a diagram for explaining a tearing phenomenon that occurs when the vertical synchronization mode is off.

[0144] Referring to Figure 7 When the vertical synchronization mode is off, the main control device 110 can start image processing of the next frame when the image processing of the corresponding frame is completed, regardless of the signal level of the vertical synchronization signal.

[0145] Thus, if the image processing speed of the main control device 110 is fast, the time at which the main control device 110 starts to process the image can be faster than in the mode in which the vertical synchronization mode is on.

[0146] Further, when the image processing of the corresponding frame is completed in the main control device 110, the main control device 110 controls the driving circuit to display the processed image on the display panel 130.

[0147] Thus, the image of the previous frame and the image of the corresponding frame can be displayed on one screen on the display panel 130.

[0148] This phenomenon can be referred to as a tearing of a screen.

[0149] If the vertical synchronization mode is off, the tearing of a screen phenomenon can be recognized on the display panel 130.

[0150] Figure 8 FIG. 2 is a diagram for explaining the tearing of a screen phenomenon.

[0151] Referring to Figure 8 On the display panel 130, the image of the previous frame image (1) and the image of the corresponding frame image (2) can be displayed on one screen with respect to a screen tearing line STL.

[0152] If the tearing of a screen occurs, the image of the previous frame image (1) and the image of the corresponding frame image (2) are displayed on the display panel 130 and on one screen, and thus the display panel 130 displays the screen as if the images are torn.

[0153] Figure 9 FIG. 3 is a diagram for explaining an embodiment in which the display panel 130 is driven in a variable refresh rate mode when the vertical synchronization mode is off. In the disclosure, the refresh rate and the frame rate can be used as equivalent meanings.

[0154] Referring to Figure 9 When the vertical synchronization mode is off, the main control device 110 processes an image of a corresponding frame, and the processed image is displayed on the display panel 130.

[0155] In the active period ACT, a data signal for displaying an image of a corresponding frame is input to the plurality of data lines DL of the display panel 130.

[0156] Each of the plurality of frames can include an active period ACT in which an image of a corresponding frame is input to the plurality of data lines DL and a blank period BLANK which is a period from after the image of the corresponding frame is input to the plurality of data lines DL until an image of a next frame is input to the plurality of data lines DL.

[0157] When the vertical synchronization mode is off, each of the plurality of frames can have a frame period which is different from each other.

[0158] Each of the plurality of frames can have an active period ACT of the same length and a blank period BLANK of different lengths. That is, when the vertical synchronization mode is on, the length of the blank period BLANK of each of the plurality of frames can be the same. Also, when the vertical synchronization mode is off, the length of the blank period BLANK of each of the plurality of frames can be different from each other.

[0159] Referring to Figure 9 , the frame period of the first frame (frame period 1), the frame period of the second frame (frame period 2), and the frame period of the third frame (frame period 3) can all be different, however, the active periods ACT of these frames can have the same length.

[0160] Accordingly, when the vertical synchronization mode is off, a screen tearing phenomenon does not occur in the display panel 130.

[0161] Figure 10 The frame periods in each mode based on the data enable signal DE in a first mode (mode 1) in which the display device is driven in a fixed refresh rate mode and a second mode (mode 2) in which the display device is driven in a variable refresh rate mode are shown.

[0162] Referring to Figure 10 , the display device according to an embodiment of the disclosure can be driven in any one of a first mode (mode 1) and a second mode (mode 2) under the control of the main control device.

[0163] The driving mode of the display apparatus can vary according to the type of an image displayed by the display apparatus. For example, when the display apparatus displays an image such as a broadcast picture or a movie, it can be driven in a first mode (Mode 1). When the display apparatus displays a game picture image, it can be driven in a second mode (Mode 2).

[0164] In the first mode (Mode 1), the display apparatus can display an image at a preset refresh rate, and the preset refresh rate can be, for example, 120 Hz.

[0165] If the display apparatus switches from displaying a general image to displaying an image such as a game picture, the driving mode of the display apparatus can switch from the first mode (Mode 1) to the second mode (Mode 2).

[0166] In the second mode (Mode 2), the refresh rate of the display apparatus for displaying an image can be variable. That is, the frame length of each frame can be different.

[0167] In the second mode (Mode 2), in each frame, the length of the active period ACT for displaying an image can be the same, and only the length of the blank period BLANK can be different.

[0168] In order to adjust the length of the active period ACT differently for each frame, it is required to change the length of one horizontal period (1H time) of the data enable signal DE for each frame. However, if the length of one horizontal period (1H time) of the data enable signal DE is different for each frame, the length of the period during which a data signal is applied to each sub-pixel can be different for each frame, so that a flicker phenomenon can be recognized, and thus the picture quality can be degraded. Therefore, by adjusting the length of the blank period BLANK while maintaining the length of one horizontal period (1H time) of the data enable signal DE for each frame, the length of the period for each frame can be adjusted differently.

[0169] The above one horizontal period (1H time) can correspond to a period in which the voltage level of the data enable signal DE changes from a high level (H) to a low level (L) and then to a high level (H) again. The period in which the data enable signal DE is at a high level can correspond to the length of the period in which a data signal for displaying an image of a corresponding frame is applied to one sub-pixel.

[0170] In the display apparatus according to the present disclosure, in the second mode (Mode 2), even if the length of the frame period varies for each frame, the display apparatus can be driven in a manner in which only the length of the blank period BLANK is changed and the length of the active period ACT is maintained constant.

[0171] For example, in the display apparatus according to the embodiment of the disclosure, when an image is displayed at a refresh rate of 120 Hz, the length of the active period ACT can be set to the length of the active period ACT in the second mode. That is, even if the refresh rate is changed to 40 Hz, 60 Hz, or 120 Hz in the second mode (mode 2), the length of the active period ACT can be constant. In this case, the refresh rate of 120 Hz can be the highest level of refresh rate that the corresponding display apparatus can implement in the second mode (mode 2).

[0172] The highest level of refresh rate that the corresponding display apparatus can implement in the second mode (mode 2) can also be referred to as a reference frame rate FRref. A refresh rate lower than the reference refresh rate FRref (e.g., 120 Hz) (e.g., 40 Hz, 60 Hz, etc.) can be implemented by maintaining the length of the active period ACT and adjusting only the length of the blank period BLANK.

[0173] In the display apparatus according to the embodiment of the disclosure, the color coordinate values or the data voltage levels for displaying a black image can be set based on the reference refresh rate FRref in the pre-shipment stage.

[0174] The reference refresh rate FRref value in the second mode (mode 2) can be set to be the same as the refresh rate in the first mode (mode 1), but the two refresh rates can be designed differently.

[0175] For example, in the second mode (mode 2), the reference refresh rate FRref can be 60 Hz or 120 Hz, but can be designed as a different value.

[0176] In the length of one horizontal period (1H time) in the second mode (mode 2), compared to the length of one horizontal period (1H time) in the first mode (mode 1), the length of the period in which the data enable signal DE is at a high level can be the same, and the length of the period in which the data enable signal DE is at a low level can be shorter.

[0177] In the first mode (mode 1) and the second mode (mode 2), it can mean that the length of one horizontal clock (1HCLK) is the same in the first mode (mode 1) and the second mode (mode 2), that the length of the period in which the voltage level of one horizontal period (1H time) is at a high level is the same in the first mode (mode 1) and the second mode (mode 2).

[0178] In the second mode (mode 2), when the reference refresh rate FRref is 144 Hz, the length of one horizontal period (1H time) can be constant at 3.1 µs for each frame.

[0179] Reference Figure 10When the second mode (mode 2) is terminated, the display apparatus according to the disclosure switches to the first mode (mode 1) which is a fixed refresh rate mode.

[0180] Figure 11 is a graph for illustrating a relationship between a length of a blank period and a voltage difference Vgs between the first node and the second node of the driving transistor DRT.

[0181] During the blank period BLANK, a gate voltage of the off voltage level is applied to the scan transistor SCT. However, due to a drain current of the scan transistor SCT, the voltage of the first node N1 of the driving transistor DRT can gradually increase. Also, as the voltage of the first node N1 of the driving transistor DRT gradually increases, the voltage of the second node N2 of the driving transistor DRT can also slightly increase during the blank period BLANK.

[0182] When the refresh rate is lowered in the variable refresh rate mode, the voltage of the second node N2 of the driving transistor DRT in the partial sub-pixel SP of the display panel can increase to the extent that the light emitting device ED emits light.

[0183] Referring to Figure 11 When the refresh rate is 120 Hz or 60 Hz in the second mode (mode 2), the voltage X and Y of the second node N2 of the driving transistor DRT can be lower than the emission threshold voltage ETV. However, when the refresh rate is 40 Hz, the voltage Z of the second node N2 of the driving transistor DRT can be higher than the emission threshold voltage ETV.

[0184] In such a sub-pixel SP, a black defect phenomenon in which the light emitting device ED emits light during the blank period BLANK at a low refresh rate can occur, so that full black is not displayed.

[0185] Figure 12 is a graph for exemplarily illustrating a black defect phenomenon recognized by the display panel at a low refresh rate in the variable refresh rate mode.

[0186] Referring to Figure 12 In a case where an image is displayed at a high refresh rate (for example, a refresh rate of 120 Hz or more) in the second mode (mode 2), the black defect phenomenon does not occur in the blank period BLANK.

[0187] However, if an image is displayed at a low refresh rate (for example, a refresh rate of 40 Hz or less) in the second mode (mode 2), the black defect phenomenon can occur in the blank period BLANK.

[0188] The black defect phenomenon can be as Figure 12The entire black defect phenomenon can occur in the display panel 130, but can also occur in a specific area of the display panel 130.

[0189] Therefore, when the display panel 130 displays an image at a low refresh rate, a phenomenon in which the luminance of a low gray scale (e.g., 1 Gray to 40 Gray) image is recognized as higher or a flickering phenomenon in which screen flickering occurs can occur.

[0190] In a case in which the black defect phenomenon occurs locally in a specific area of the display panel 130, a phenomenon in which low gray scales are clustered in the specific area or a phenomenon in which the recognition of luminance differences in low gray scale images can occur.

[0191] Therefore, when a low gray scale image is displayed, a problem in which display quality is poor can occur. Therefore, a method for solving this problem is needed.

[0192] Figure 13 is a diagram for describing a process of compensating for a first initialization voltage VpreR in a display apparatus according to an embodiment of the disclosure.

[0193] The display apparatus according to an embodiment of the disclosure can adjust the voltage level of the first initialization voltage VpreR by reflecting the length of the blank period BLANK. In the display apparatus according to an embodiment of the disclosure, if the length of the blank period BLANK increases, the voltage level of the first initialization voltage VpreR applied to the second node N2 of the driving transistor DRT can be adjusted to increase. Therefore, the voltage difference Vgs between the first node N1 and the second node N2 of the driving transistor DRT decreases, thereby improving the black defect phenomenon.

[0194] An example method of adjusting the voltage level of the first initialization voltage VpreR by reflecting the length of the blank period BLANK in the display apparatus according to an embodiment of the disclosure will be described in detail below.

[0195] Referring to Figure 13 The display apparatus according to an embodiment of the disclosure can include a monitor sub-pixel MSP, and a reference voltage line RVL can be electrically connected to the monitor sub-pixel MSP.

[0196] A monitor sub-pixel sensing voltage Vsen_MSP input from the monitor sub-pixel MSP can be applied to the reference voltage line RVL.

[0197] The monitor sub-pixel sensing voltage Vsen_MSP is a voltage that reflects the length of the blank period BLANK in a variable refresh rate mode.

[0198] An analog-to-digital converter ADC can receive the monitoring sub-pixel sensing voltage Vsen_MSP and output a digital value Dsen_MSP corresponding to the input monitoring sub-pixel sensing voltage Vsen_MSP to the timing controller 240.

[0199] The timing controller 240 can store a reference frame rate FRref and a monitoring sub-pixel sensing voltage value "x" at the reference frame rate FRref.

[0200] The timing controller 240 can calculate a difference value "Δ" between the monitoring sub-pixel sensing voltage value "x+Δ" at the current frame rate FRcurrent and the monitoring sub-pixel sensing voltage value "x" at the reference refresh rate FRref. This can be referred to as an "increment calculation process".

[0201] The timing controller 240 can calculate the difference value "Δ" in the increment calculation process and control the power management circuit 250 to correct the voltage value of the first initialization voltage VpreR by the calculated difference value "Δ".

[0202] For example, when the calculated difference value "Δ" is positive, the timing controller 240 can control the power management circuit 250 to increase the voltage level of the first initialization voltage VpreR by the difference value "Δ". If the calculated difference value "Δ" is negative, the timing controller 240 can control the power management circuit 250 to decrease the voltage level of the first initialization voltage VpreR by the difference value "Δ".

[0203] The process of the timing controller 240 for controlling the power management circuit 250 to change the voltage level of the first initialization voltage VpreR based on the calculated difference value "Δ" can be referred to as a "first initialization voltage VpreR compensation process".

[0204] These "increment calculation processes" and "first initialization voltage VpreR compensation processes" can be performed for each blank period BLANK in the variable refresh rate mode.

[0205] Accordingly, the voltage level of the first initialization voltage VpreR can be increased or decreased in real time by reflecting the refresh rate of the previous frame.

[0206] Specifically, if the length of the blank period BLANK of the previous frame is relatively long, the voltage level of the monitoring sub-pixel sensing voltage Vsen_MSP is high. Accordingly, the voltage level of the first initialization voltage VpreR is also increased. If the length of the blank period BLANK of the previous frame is relatively short, the voltage level of the monitoring sub-pixel sensing voltage Vsen_MSP is low. Accordingly, the voltage level of the first initialization voltage VpreR is also decreased.

[0207] Reference will be made to Figure 14The length of the blank period BLANK is described in detail in relation to the monitoring sub-pixel sensing voltage Vsen_MSP.

[0208] Figure 14 is a diagram for describing a monitoring sub-pixel MSP and a monitoring sub-pixel sensing voltage Vsen_MSP in a display apparatus according to an embodiment of the disclosure.

[0209] Referring to Figure 14 , the monitoring sub-pixel MSP can include a scan transistor SCT and a charging transistor CHART, a monitoring capacitor Cmtr, and a sensing transistor SENT.

[0210] The scan transistor SCT can be controlled by a scan signal SCAN which is a type of gate signal, and can transfer a data voltage Vdata applied to a data line DL to the charging transistor CHART.

[0211] The charging transistor CHART of the monitoring sub-pixel MSP can correspond to a driving transistor DRT of a sub-pixel SP for displaying an image. However, the charging transistor CHART can be different from the driving transistor DRT in that the charging transistor CHART is not electrically connected to a light emitting device.

[0212] A first node N1 of the charging transistor CHART is electrically connected to the scan transistor SCT. A second node N2 of the charging transistor CHART is electrically connected to one end of the monitoring capacitor Cmtr. A high potential driving voltage EVDD is applied to a third node N3 of the charging transistor CHART. The first node N1 of the charging transistor CHART can be a gate node. The second node N2 of the charging transistor CHART can be a source node or a drain node. The third node N3 of the charging transistor CHART can be the other of the source node and the drain node.

[0213] One end of the monitoring capacitor Cmtr is electrically connected to the second node N2 of the charging transistor CHART. A base voltage EVSS is applied to the other end of the monitoring capacitor Cmtr.

[0214] The sensing transistor SENT can be controlled by a sensing pulse SENSE which is a type of gate signal, and switches electrical connection between the second node N2 of the charging transistor CHART and a reference voltage line RVL.

[0215] The sensing transistor SENT can be turned on or turned off according to the sensing pulse SENSE. If the sensing transistor SENT is turned on, a first initialization voltage VpreR is input to the second node N2 of the charging transistor CHART, or a voltage of one end of the monitoring capacitor Cmtr is input to the reference voltage line RVL.

[0216] The display device according to the embodiment of the present disclosure can monitor the voltage of one end of the monitoring capacitor Cmtr to change the voltage level of the first initialization voltage VpreR. Accordingly, the voltage at one end of the monitoring capacitor Cmtr input to the reference voltage line RVL can also be referred to as a monitoring sub-pixel sensing voltage Vsen_MSP.

[0217] When the display device is driven in the variable refresh rate mode, the data signal Vdata is input to the monitoring sub-pixel MSP.

[0218] In the active period ACT, the voltage level of the second node N2 of the charging transistor CHART is initialized to the first initialization voltage VpreR. Thereafter, the data signal Vdata for a voltage level for displaying a low gray scale image is applied to the first node N1 of the charging transistor CHART. Here, the low gray scale image can mean, for example, a black gray scale image.

[0219] In the blank period BLANK, the gate voltage applied to the first node N1 of the charging transistor CHART can increase due to the drain current of the scan transistor SCT. Accordingly, the voltage of the first node N1 of the charging transistor CHART gradually increases during the blank period BLANK.

[0220] As the voltage of the first node N1 of the charging transistor CHART increases, the voltage of the second node N2 of the charging transistor CHART also increases from the first initialization voltage VpreR. The voltage of the second node N2 of the charging transistor CHART is applied to one end of the monitoring capacitor Cmtr.

[0221] In the variable refresh rate mode, if the length of the blank period BLANK changes, the amount of increase in the voltage of the second node N2 of the charging transistor CHART can also change. For example, if the length of the blank period BLANK is relatively long, the voltage of the second node N2 of the charging transistor CHART relatively increases more. In contrast, if the length of the blank period BLANK is relatively short, the increase in the voltage of the second node N2 of the charging transistor CHART is relatively less.

[0222] In the blank period BLANK, the sensing pulse SENSE of the on voltage level is input to the sensing transistor SENT of the monitoring sub-pixel MSP. When the sensing pulse SENSE of the on voltage level is input to the sensing transistor SENT, the reference voltage line RVL and the second node N2 of the charging transistor CHART are electrically connected. The monitoring sub-pixel sensing voltage Vsen_MSP is applied to the reference voltage line RVL.

[0223] The monitoring sub-pixel sensing voltage Vsen_MSP applied to the reference voltage line RVL is a voltage reflecting the length of the blank period BLANK. In the same sense, the monitoring sub-pixel sensing voltage Vsen_MSP is a voltage reflecting the current refresh rate in real time in the variable refresh rate mode.

[0224] The analog-to-digital converter ADC can receive the monitoring sub-pixel sensing voltage Vsen_MSP, convert the monitoring sub-pixel sensing voltage Vsen_MSP into a digital value, and output the digital value to the timing controller 240.

[0225] The timing controller 240 can perform the above-described "increment calculation process" and "first initialization voltage VpreR compensation process" using a lookup table LUT stored in the memory 310.

[0226] In the display apparatus according to the embodiment of the disclosure, in the variable refresh rate mode, when the length of the blank period BLANK gradually increases during the continuous frame period, the voltage level of the first initialization voltage VpreR can be adjusted to increase in real time. Therefore, the voltage difference Vgs between the gate node and the source node of the driving transistor included in the sub-pixel displaying a low gray image decreases, and thus it is possible to solve the problem that the black defect phenomenon is recognized.

[0227] In addition, in the display apparatus according to the embodiment of the disclosure, as the voltage level of the first initialization voltage VpreR increases, the voltage difference Vgs between the gate node and the source node of the driving transistor included in the sub-pixel displaying a high gray image can also slightly decrease. However, in the sub-pixel displaying a high gray image, the decrease in the voltage difference Vgs has little effect on the visual perception of the viewer, whereas the resolution of the black defect phenomenon in the low gray image due to the decrease in the voltage difference Vgs greatly affects the visual perception of the viewer.

[0228] Therefore, when the display apparatus according to the embodiment of the disclosure operates in the variable refresh rate mode, it is particularly effective in improving the display quality at a low refresh rate.

[0229] Figure 15 is a graph for describing a process in which the timing controller controls the power management circuit 250 to change the voltage value of the first initialization voltage VpreR based on the reference refresh rate value FRref and the reference sensing voltage value Vsen_ref at the reference refresh rate value.

[0230] Referring to Figure 15 The timing controller 240 can include the memory 310, and the memory 310 stores the lookup table LUT.

[0231] The look-up table LUT stored in the memory 310 can store frame rate values and the monitoring sub-pixel sensing voltage Vsen_MSP values of the monitoring sub-pixels at corresponding refresh rates. The look-up table LUT can be pre-stored before the display apparatus is shipped, or can be updated after the display apparatus is shipped.

[0232] The look-up table LUT can store a reference refresh rate FRref value and a monitoring sub-pixel sensing voltage Vsen_MSP value when the display apparatus is driven at the reference refresh rate FRref. The value of the monitoring sub-pixel sensing voltage Vsen_MSP when driven at the reference refresh rate FRref can be defined as a reference sensing voltage Vsen_ref.

[0233] In the display apparatus according to the disclosure, the analog-to-digital converter ADC can receive the monitoring sub-pixel sensing voltage Vsen_MSP, convert the input analog voltage into a digital value to output to the timing controller 240.

[0234] The timing controller 240 can check the value of the monitoring sub-pixel sensing voltage Vsen_MSP input to the analog-to-digital converter ADC based on the input digital value.

[0235] In addition, the timing controller 240 can refer to the look-up table LUT stored in the memory 310 to calculate a frame rate value corresponding to the monitoring sub-pixel sensing voltage Vsen_MSP.

[0236] Referring to the above Figure 4 In a certain mode (e.g., a variable refresh rate mode), the image displayed on the display panel 130 can be an image in which the number of frames per second FPS varies according to time. For example, the number of frames per second FPS at a current time point can increase, remain at a constant level, or decrease compared to a previous time point.

[0237] In a conventional display apparatus, it is difficult to specify the number of frames per second FPS of the image displayed at a current time due to the characteristic that the number of frames per second FPS randomly varies over time. Therefore, in the conventional display apparatus, it is also difficult to improve the black defect phenomenon that can occur when the number of frames per second FPS varies over time.

[0238] The display apparatus according to the embodiment of the disclosure can identify information about the number of frames per second FPS at a previous time point based on the monitoring sub-pixel sensing voltage Vsen_MSP sensed at the previous time point. For example, the timing controller 240 can receive a value corresponding to the monitoring sub-pixel sensing voltage Vsen_MSP for each blank period in the variable refresh rate mode. When the display apparatus operates in the variable refresh rate mode, the timing controller 240 can calculate a value equal to or similar to the refresh rate at a current time point.

[0239] Accordingly, the timing controller 240 can follow the number of frames per second FPS that varies in the above-described specific mode. The timing controller 240 can set the level of the first initialization voltage VpreR based on the level of the monitoring sub-pixel sensing voltage Vsen_MSP. The timing controller 240 can control the power management circuit 250 to apply the first initialization voltage VpreR of the set level to the first initialization voltage supply node NpreR.

[0240] For example, the timing controller 240 can receive a value corresponding to the monitoring sub-pixel sensing voltage Vsen_MSP during the blank period of the first frame operating in the variable refresh rate mode.

[0241] The timing controller 240 can set the level of the first initialization voltage VpreR (e.g., VpreR+Δ) based on the level of the monitoring sub-pixel sensing voltage Vsen_MSP in the blank period.

[0242] The timing controller 240 can control the power management circuit 250 to apply the first initialization voltage VpreR+Δ having the set level.

[0243] The power management circuit 250 can input the first initialization voltage VpreR+Δ of the set voltage level to the first initialization voltage supply node NpreR. The first initialization voltage VpreR+Δ having the set voltage level can be input to the first initialization voltage supply node NpreR during the blank period of the corresponding frame and / or the active period of the next frame.

[0244] Hereinafter, a process of calculating the first initialization voltage VpreR+Δ having the set voltage level will be described in detail.

[0245] The timing controller 240 can calculate the voltage difference between the monitoring sub-pixel sensing voltage Vsen_MSP value input to the analog-to-digital converter ADC and the reference sensing voltage Vsen_ref value as a difference value "Δ". The timing controller 240 can compare the monitoring sub-pixel sensing voltage Vsen_ref at the current refresh rate FRcurrent with the reference sensing voltage Vsen_ref at the reference refresh rate FRref to obtain the difference value "Δ" between the two voltage values.

[0246] For example, in a look-up table (LUT) stored in the memory 310, when the refresh rate is 144 Hz, 120 Hz, 80 Hz, 60 Hz, and 40 Hz, the monitoring sub-pixel sensing voltage Vsen_MSP can be stored as A, B, C, D, and E, respectively. If the reference refresh rate FRref is 120 Hz, the reference sensing voltage Vsen_ref is B. The timing controller 310 calculates the difference value "Δ" between the monitoring sub-pixel sensing voltage Vsen_MSP sensed during the driving period and the reference sensing voltage Vsen_ref value.

[0247] The above process in which the timing controller 240 calculates the difference value Δ can be referred to as an "increment calculation process".

[0248] Referring to Figure 15 The power management circuit 250 can supply the first initialization voltage VpreR to the first initialization voltage supply node NpreR.

[0249] The power management circuit 250 can include a variable voltage output circuit 1500, and the power management circuit 250 can supply a voltage output from the variable voltage output circuit 1500 to the first initialization voltage supply node NpreR.

[0250] The variable voltage output circuit 1500 can include, for example, a resistor string in which two or more resistors are connected in series, and a voltage input terminal to which a voltage is input across both ends of the resistor string. The power management circuit 250 can adjust the level of the voltage output from the variable voltage output circuit 1500 using the resistor string in a voltage division method.

[0251] The timing controller 240 controls the power management circuit 250 to apply the first initialization voltage VpreR+Δ corrected by the difference value "Δ" to the first initialization voltage supply node NpreR. This can be referred to as "first initialization voltage compensation (VpreR compensation)".

[0252] The power management circuit 250 outputs the first initialization voltage VpreR+Δ of the compensated voltage level to the first initialization voltage supply node NpreR under the control of the timing controller 240.

[0253] Accordingly, the first initialization voltage VpreR+Δ having the voltage level compensated by the difference value "Δ" can be applied to the first initialization voltage supply node NpreR.

[0254] The difference value "Δ" is a value reflecting the frame period length of the corresponding frame and the frame rate or refresh rate of the corresponding frame in the variable refresh rate mode.

[0255] The display apparatus according to the disclosure can supply a first initialization voltage VpreR reflecting a refresh rate or a frame rate of a corresponding frame to a first initialization voltage supply node NpreR in a variable refresh rate mode. Accordingly, a black defect phenomenon at a low refresh rate can be effectively prevented.

[0256] Figure 16 A difference between a case where a general image is displayed and a case where a game image is displayed in the display apparatus 100 according to the disclosure is schematically shown.

[0257] Referring to Figure 16 , the main control apparatus 110 can receive general image data or can receive game image data.

[0258] When the main control apparatus 110 receives general image data, the driving circuit 120 stores image data of a corresponding frame in a frame buffer.

[0259] The driving circuit 120 can perform an image correction algorithm for modulating the image data stored in the frame buffer. The algorithm can be, for example, an algorithm for preventing a ghosting phenomenon from occurring in a display area when a display panel 130 is driven for a long time. For example, the driving circuit 120 can detect a logo area where the same image is displayed for a long time, and perform an algorithm for reducing brightness of the detected logo area.

[0260] The driving circuit 120 outputs various signals for image output to the display panel 130 based on the modulated image data. The display panel 130 displays an image at a preset refresh rate.

[0261] In addition, the main control apparatus 110 can receive game image data. Referring to the above-described Figure 4 , the game image data can refer to image data in which the number of frames per second FPS varies over time. Unlike the game image data, image data for displaying a general image can mean image data having a constant number of frames per second.

[0262] When the main control apparatus 110 receives game image data, the driving circuit 120 can not store the game image data input to the main control apparatus 110 in a frame memory.

[0263] The driving circuit 120 does not apply the aforementioned algorithm to the game image data, and thus a game image to which the image modulation algorithm is not applied can be displayed on the display panel 130. Since a period in which the game image data is stored in the frame memory of the driving circuit 120 is omitted, a game screen of the next frame is displayed on the display panel 130 at a timing slightly earlier than that of a general image. Accordingly, satisfaction of a user using game content can be improved. In consideration of the characteristic that an image displayed on a screen is rapidly switched in the game image, the advantage can be greater than the disadvantage.

[0264] According to the type of game image received by the main control device 110, the display panel 130 can display an image in a fixed refresh rate mode (mode 1) or in a variable refresh rate mode (mode 2). For example, if the main control device 110 receives first game image data, the display panel 130 can display an image in a fixed refresh rate mode (mode 1). Alternatively, if the main control device 110 receives second game image data, the display panel 130 can display an image in a variable refresh rate mode (mode 2).

[0265] When the display panel 130 displays an image in a fixed refresh rate mode (mode 1), the display panel 130 can display an image, for example, at a refresh rate of 60 Hz or at a refresh rate of 120 Hz. In some cases, the display panel 130 can display a game image at a refresh rate of 60 Hz and then switch to a refresh rate of 120 Hz to display an image.

[0266] When the display panel 130 displays an image in a variable refresh rate mode (mode 2), the display panel 130 can variably display an image from a low refresh rate to a high refresh rate. For example, the display panel 130 can display an image while varying from a low refresh rate of 40 Hz or less to a high refresh rate of 120 Hz or more.

[0267] The display device 100 according to the embodiment of the disclosure can display a full black image when inputting second game image data in a variable refresh rate mode (mode 2), and thus can provide a display device 100 having improved display quality.

[0268] Figure 17 An exemplary display device according to the embodiment of the disclosure is shown to display a full black in a variable refresh rate mode (mode 2).

[0269] Referring to Figure 17 The display device according to the embodiment of the disclosure can display a full black image on the display panel 130 in a variable refresh rate mode (mode 2) regardless of the refresh rate. Accordingly, a display device having greatly improved display quality can be provided.

[0270] A brief description of the embodiments of the disclosure will be provided below.

[0271] The display device 100 according to the embodiment of the present disclosure can include a sub-pixel SP including a light emitting device ED and a drive transistor DRT electrically connected to a first electrode of the light emitting device ED and configured to drive the light emitting device ED, and a reference voltage line RVL electrically connected to the sub-pixel SP and applying an initialization voltage VpreR to the first electrode of the light emitting device ED, wherein a voltage level of the initialization voltage VpreR is changed according to a length of a blank period BLANK.

[0272] The display device 100 according to the embodiment of the present disclosure can further include a display panel 130 including a display area AA in which the sub-pixel SP is disposed and a non-display area NA around the display area AA. A monitor sub-pixel MSP is located in the non-display area NA, the monitor sub-pixel MSP including a monitor capacitor Cmtr and a charging transistor CHART electrically connected to one end of the monitor capacitor Cmtr, and the one end of the monitor capacitor Cmtr can be electrically connected to the reference voltage line RVL.

[0273] In the display device 100 according to the embodiment of the present disclosure, the monitor capacitor Cmtr can include the other end to which the base voltage EVSS is applied.

[0274] In the display device 100 according to the embodiment of the present disclosure, the monitor sub-pixel MSP can further include a sensing transistor SENT configured to switch an electrical connection between the monitor capacitor Cmtr and the reference voltage line RVL. In the variable refresh rate mode (mode 2), a timing of applying a sensing pulse SENSE of an on voltage level can be changed according to a length of the blank period BLANK.

[0275] The display device 100 according to the embodiment of the present disclosure can further include an analog-to-digital converter ADC for sensing a voltage of the reference voltage line RVL and converting a sensed analog voltage Vsen_MSP into a digital value to output the digital value. A voltage of the one end of the monitor capacitor Cmtr input to the analog-to-digital converter ADC can be changed according to a length of the blank period BLANK.

[0276] The display device 100 according to the embodiment of the present disclosure can further include a timing controller 240 for receiving the digital value output from the analog-to-digital converter ADC, and a power management circuit 250 for changing a voltage level of the initialization voltage VpreR under control of the timing controller 240.

[0277] In the display device 100 according to the embodiment of the disclosure, the timing controller 240 can include a memory 310 for storing a look-up table (LUT) including a reference refresh rate FRref value and a reference sensing voltage Vsen ref value at the reference refresh rate FRref, wherein the timing controller 240 can control the power management circuit 250 to change the voltage level of the initialization voltage VpreR based on the reference sensing voltage Vsen ref value.

[0278] In the display device 100 according to the embodiment of the disclosure, the power management circuit 250 can further include a variable voltage output circuit 1500, and the initialization voltage VpreR can be output from the variable voltage output circuit 1500.

[0279] In the display device 100 according to the embodiment of the disclosure, the variable voltage output circuit 1500 can include a resistor column (resistor string) including two or more resistors. Further, the power management circuit 250 can apply a voltage divided by the resistor column (resistor string) to the initialization voltage supply node NpreR.

[0280] In the display device 100 according to the embodiment of the disclosure, during driving the display device in the variable refresh rate mode (mode 2), for a plurality of consecutive frames in the variable refresh rate mode (mode 2), when the length of the blank period BLANK increases, the voltage level of the initialization voltage VpreR can increase, and when the length of the blank period BLANK decreases, the voltage level of the initialization voltage VpreR can decrease.

[0281] The display device 100 according to the embodiment of the disclosure can further include a main control device 110 for controlling a driving mode of the display device 100 to drive the display device 100 in the variable refresh rate mode (mode 2) or the fixed refresh rate mode (mode 1).

[0282] In the display device 100 according to the embodiment of the disclosure, in the variable refresh rate mode (mode 2), a plurality of frames can have the same active period ACT length.

[0283] The display device 100 according to the embodiment of the disclosure can further include an initialization voltage supply node NpreR electrically connected to a reference voltage line RVL by a switch RPRE and supplied with the initialization voltage VpreR, wherein during the active period ACT immediately after the blank period BLANK, the voltage level of the initialization voltage VpreR applied to the initialization voltage supply node NpreR can vary based on the length of the blank period BLANK.

[0284] The above description has been presented to enable any person skilled in the art to make and use the inventive concept, and has been provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. The above description and drawings are provided for exemplary purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the inventive concept. Thus, the scope of the present application is not limited to the embodiments shown but is consistent with the widest scope consistent with the claims. The scope of the present application should be construed based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as included in the scope of the present application.

Claims

1. A display device comprising: a sub-pixel including a light emitting device and a drive transistor electrically connected to a first electrode of the light emitting device and configured to drive the light emitting device; and a reference voltage line electrically connected to the sub-pixel and applying an initialization voltage to the first electrode of the light emitting device, wherein a voltage level of the initialization voltage varies according to a length of a blank period, wherein the display device further includes a display panel including a display area provided with the sub-pixel and a non-display area around the display area, wherein a monitoring sub-pixel is provided in the non-display area, the monitoring sub-pixel including a monitoring capacitor and a charging transistor electrically connected to one end of the monitoring capacitor, wherein one end of the monitoring capacitor is electrically connected to the reference voltage line. The monitoring capacitor includes the other end to which a base voltage is applied.

2. The display device according to claim 1, wherein The monitoring sub-pixel further includes a sensing transistor configured to switch electrical connection between the monitoring capacitor and the reference voltage line according to a sensing pulse, 3. The display device according to claim 1, wherein wherein in a variable refresh rate mode, timing of the sensing pulse applying an on voltage level varies according to the length of the blank period.

4. The display device of claim 3, further comprising an analog-to-digital converter configured to sense a voltage of the reference voltage line, convert the sensed voltage into a digital value, and output the converted digital value, wherein a voltage of the one end of the monitoring capacitor input to the analog-to-digital converter varies according to the length of the blank period. wherein 5. The display device of claim 4, further comprising: a timing controller configured to receive a digital value output from the analog-to-digital converter; and a power management circuit configured to vary a voltage level of the initialization voltage under control of the timing controller. The timing controller includes a memory for storing a lookup table including a reference refresh rate value and a reference sensing voltage value at the reference refresh rate value, wherein the timing controller is configured to control the power management circuit to vary the voltage level of the initialization voltage based on the reference sensing voltage value.

6. The display device of claim 5, wherein, The power management circuit further includes a variable voltage output circuit configured to output the initialization voltage. The variable voltage output circuit includes a resistor column including two or more resistors, 7. The display device according to claim 5, wherein wherein the power management circuit is configured to apply a voltage divided by the resistor column to an initialization voltage supply node.

8. The display device of claim 7, wherein, During driving of the display device in a variable refresh rate mode, for a plurality of consecutive frames in the variable refresh rate mode, as the length of the blank period increases, the voltage level of the initialization voltage increases, and as the length of the blank period decreases, the voltage level of the initialization voltage decreases. ​ 9. The display device according to claim 1, wherein ​ 10.The display apparatus according to claim 1, further comprising a main control apparatus configured to control a driving mode of the display apparatus so that the display apparatus is driven in a variable refresh rate mode or a fixed refresh rate mode.

11. The display device according to claim 1, wherein In the variable refresh rate mode, a plurality of frames have an active period of the same length. 12.The display apparatus according to claim 1, further comprising an initialization voltage supply node electrically connected to the reference voltage line by a switch and supplied with the initialization voltage, wherein, a voltage level of the initialization voltage applied to the initialization voltage supply node varies based on a length of the blank period during an active period immediately after the blank period. 13.A display apparatus comprising: a display panel in which a sub-pixel for image display and a data line for supplying a data voltage for image display to the sub-pixel are provided, the sub-pixel including a light emitting apparatus and a driving transistor for driving the light emitting apparatus; and a reference voltage line electrically connected to the sub-pixel and applying an initialization voltage to a second node of the driving transistor, wherein the initialization voltage is used to initialize a voltage of the second node of the driving transistor when the data voltage is input to the data line, wherein in a variable refresh rate mode, as a length of a blank period of a previous frame increases, an initialization voltage applied during a current frame increases, wherein a first node of the driving transistor is a gate node and a second node of the driving transistor is a source node or a drain node, wherein the display panel includes a display area in which the sub-pixel is provided and a non-display area around the display area, wherein a monitoring sub-pixel is provided in the non-display area, the monitoring sub-pixel including a monitoring capacitor and a charging transistor electrically connected to one end of the monitoring capacitor, wherein one end of the monitoring capacitor is electrically connected to the reference voltage line.

Images