A storage cell and storage method for VCMA-STT MTJ

Abstract

The application relates to a storage unit and a storage method of a VCMA-STT MTJ, the storage unit of the VCMA-STT MTJ comprising: a plurality of VCMA-STT MTJ devices; a driving circuit configured to apply a voltage to the devices, including applying a first voltage to regulate a critical flipping current of a free layer of the MTJ; and applying a second voltage to regulate a magnetic moment direction of the free layer of the MTJ. The application realizes switching of the devices in the VCMA and STT modes through voltage regulation, realizes the gating switch and storage functions of the memory device, replaces the 1T-1R storage structure in the prior art, avoids the process complexity of CMOS integration, and has great scientific research use value in the implementation of a specific small-scale prototype storage array.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a memory cell and storage method for a VCMA-STT MTJ. Background Technology

[0002] Memory is one of the core chips in the field of integrated circuits and an indispensable module in various electronic products.

[0003] Magnetic random access memory (MRAM) is a promising memory technology due to its non-volatile data storage, fast read / write speeds, and low power consumption. The non-volatile storage function of MRAM devices is provided by magnetic tunnel junction (MTJ) devices. An MRAM memory cell consists of a transistor and a magnetic tunnel junction (1T-1R). The magnetic tunnel junction structure may include a free layer, a tunnel barrier isolation layer, and a pinned layer. The magnetization state of the pinned layer is fixed by the pinned layer. The magnetization direction of the free layer can switch between two different directions relative to the pinned layer, typically corresponding to a magnetic "parallel" state and a magnetic "antiparallel" state, respectively. The relative orientation of the magnetization of the pinned and free layers determines the current resistance of the MTJ device. MTJ devices can exhibit lower resistance when the free layer is in a parallel state and higher resistance when the free layer is in an antiparallel state. The tunnel magnetoresistance ratio (TMR) is a measure of the difference in MTJ resistance between the parallel and antiparallel states.

[0004] Voltage-controlled magnetic anisotropy magnetic random access memory (VCMA-MRAM) rapidly modulates the magnetization direction by changing the applied voltage (electric field), thereby effectively reducing ohmic losses caused by current. Therefore, it features fast write speeds and low write power consumption, and is expected to become the next generation of mainstream non-volatile memory. Data storage is achieved by controlling the magnetization direction of the MTJ free layer using voltage.

[0005] Currently, mainstream MeRAMs utilize the spin transfer torque (STT) characteristic of the MTJ for erase and write operations. In this type of MeRAM array, programming the MTJ is primarily achieved by applying voltage polarity across its positive and negative terminals. For example... Figure 2As shown, applying a positive voltage decreases the resistance of the MTJ, while applying a negative voltage increases its resistance. When reading stored data, the characteristic that the MTJ has different resistance values ​​in different states is utilized to convert the resistance difference into a voltage or current difference. By appropriately designing the resistance value of the reference resistor, the difference between it and the MTJ's resistance value is converted into a voltage or current signal difference by the reading circuit, and then compared by a sensitive amplifier to obtain the corresponding stored value.

[0006] A novel MeRAM technology based on voltage-controlled magnetic anisotropy (VCMA) effect MTJs has been developed. Its main difference from STT (Single-Touch Technology) lies in its use of voltage pulses rather than polarity to alter the MTJ's resistance characteristics. Specifically, applying a voltage pulse of a certain duration to the MTJ changes its resistance characteristics; high resistance becomes low resistance, and vice versa. The advantage of VCMA is that it effectively reduces programming time and increases memory operating speed. Due to the different programming method, the design of its peripheral control circuitry also differs. However, all current memory cells use a one-transistor-one-memory-element (1T-1R) structure, where the transistor mainly acts as a "gating switch." This allows for individual control of the memory element, avoiding crosstalk problems during access, especially erroneous writes caused by crosstalk during writing. Furthermore, this structure requires separate front-end and back-end integration technologies for CMOS, resulting in complex process steps. Additionally, the structure is only compatible with 3D integration and cannot be extended to future 3D IC technologies. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention discloses a VCMA-STT MTJ device structure as a storage element. Based on the VCMA effect, STT-MRAM is a novel non-volatile magnetic random access memory that uses spin current to write information, replacing the existing 1T-1R structure storage cell. Voltage regulation allows the VCMA-STT MTJ device to switch between VCMA and STT modes. When the device operates in VCMA mode, the vertical anisotropy of the CoFeB free layer in the MTJ is voltage-regulated, acting as a selector switch. When the device operates in STT mode, data writing to the free layer can be achieved through current. When both electrodes are used simultaneously, V1 modulates the vertical anisotropy of the CoFeB free layer through an electric field, while V2 enables STT information writing.

[0008] The present invention adopts the following technical solution: A VCMA-STT MTJ memory cell includes: Multiple VCMA-STT MTJ storage devices; The driving circuit is configured to apply voltage to the storage device, including applying a first voltage to regulate the critical flip current of the free layer of the MTJ; and applying a second voltage to regulate the magnetic moment direction of the free layer of the MTJ.

[0009] A storage method for the storage unit as described above is specifically as follows: a. Storage device switch selection By adjusting the voltage of a bit line and applying different bias voltages, when a high bias voltage is applied, the free layer magnetization reversal current increases, and when a low bias voltage is applied, the free layer magnetization reversal current decreases. This means that the memory device is in VCMA mode, thus realizing the gating and switching function of the magnetic memory device. b. Writing stored information By adjusting the voltage of another bit line and controlling the direction of the magnetic moment of the free layer to adjust the resistance of the magnetic tunnel junction, the storage device is in STT mode, thus enabling the writing of stored information.

[0010] The advantages of this invention over the prior art are as follows: This invention achieves the switching of the device between VCMA and STT modes through voltage regulation, realizes the selection switch and storage function of the memory device, replaces the 1T-1R memory structure in the prior art, avoids the process complexity of integration with CMOS, and has great scientific research value in the implementation of specific small-scale prototype memory arrays. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0012] Figure 1 This is a flowchart illustrating the fabrication process of the VCMA-STT MTJ device structure of the present invention.

[0013] Figure 2 This is a schematic diagram of the storage unit of the VCMA-STT MTJ of the present invention. Detailed Implementation

[0014] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0015] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0016] In the context of this invention, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0017] In this embodiment, a storage unit and storage method for a VCMA-STT MTJ are provided. The storage unit consists of multiple storage devices and a driving circuit. See [link to documentation]. Figure 2 . Figure 1 This is a schematic diagram illustrating the fabrication process of the VCMA-STT MTJ memory device of the present invention. The specific steps for fabricating the VCMA-STT MTJ memory device include: The core magnetic tunnel junction 101 of the MRAM memory device is deposited by magnetron sputtering. First, a pinned layer 101-1 is deposited. In one embodiment, the pinned layer 101-1 is made of CoFeB and has a thickness ranging from 1 to 1.5 nm. Then, an isolation layer 101-2 is deposited. In one embodiment, the isolation layer 101-2 is made of MgO and has a thickness ranging from 0.8 to 1 nm. Finally, a free layer 101-3 is deposited. In one embodiment, the free layer 101-3 is made of CoFeB and has a thickness ranging from 1 to 1.5 nm.

[0018] A dielectric layer 102 is grown above the free layer 101-3 by magnetron sputtering. The dielectric layer is made of MgO and has a thickness ranging from 2 to 5 nm.

[0019] Through exposure and etching processes, the CoFeB / MgO / CoFeB / MgO structure formed above is processed into multiple cylinders with a diameter of 100nm to form a memory device array.

[0020] Exposure overlay is performed on the dielectric layer 102 of each memory device to expose the top layer of the dielectric layer 102, forming a photoresist region 103 with a diameter of 50 nm. Using this photoresist region 103 as a mask, the dielectric layer 102 is etched to form a region with a diameter of 50 nm. Then the photoresist region 103 is etched away. Then, an insulating dielectric is filled around the dielectric layer 102 to form an insulating layer 104, so that the insulating layer 104 completely surrounds the dielectric layer 102. In one embodiment, the insulating dielectric is SiN or SiO2.

[0021] Through the perforation technique, perforations are made from top to bottom in the insulating layer 105. The perforations are respectively connected to the dielectric layer 102 and the free layer 101-3. Conductive metal is deposited in the perforations. In this embodiment, the conductive metal is Au, which forms electrode 105-1 and electrode 205-2 respectively.

[0022] At this point, the storage device fabrication of VCMA-STT MTJ is complete.

[0023] Multiple VCMA-STT MTJ memory devices are connected to a driving circuit, which may include multiple bit lines and multiple word lines. Each memory device is connected between two corresponding bit lines and one word line. Electrode 105-1 and electrode 105-2 of the VCMA-STT MTJ memory device are each connected to two bit lines. Electrode 105-1 is connected to voltage V1, and electrode 105-2 is connected to voltage V2. The pinned layer 101-1 is connected to the word line, which is typically grounded. Thus, by controlling the word line voltage, a single memory device is selected for reading and writing.

[0024] The mechanism of voltage-regulated magnetic anisotropy (VCMA) is that the electric field applied across the MTJ causes the accumulation of electron charge, leading to changes in the atomic orbitals and density of states at the interface, thus resulting in changes in the magnetic anisotropy of the interface. When current flows through the pinned layer, the current is polarized, forming a spin-polarized current. When the polarized current flows through a very thin isolation layer, it ensures a high degree of polarization (i.e., the thickness of the isolation layer must be less than the spin coherence length λsd, ensuring that the electron maintains its initial spin polarization direction after passing through the isolation layer. The spin coherence length refers to the distance traveled by the spin electron before the spin direction reverses. During coherent transport, the spin electron undergoes N collisions that can change momentum. The average distance of its momentum coherent collisions is λ, the magnitude of which is estimated by the spin electron Fermi velocity and the spin reversal time). The spin-polarized electron can transfer its spin angular momentum to the free layer, changing the magnetization equilibrium state of the free layer.

[0025] Spin electrons transfer spin momentum to the magnetic moment of the free layer, causing the magnetic moment of the spin magnetic layer to gain spin momentum and change direction. This process is called spin transfer moment. By inputting current into the free layer, the magnetic moment of the free layer is flipped, thereby changing the resistance state of the magnetic tunnel junction and enabling data writing.

[0026] In the process of free-layer magnetization reversal induced by normal current, VCMA adjusts the structure of the magnetic storage device and applies different bias voltages during the reversal process. When a high bias voltage is applied, the free-layer magnetization reversal current increases, and when a low bias voltage is applied, the free-layer magnetization reversal current decreases. In other words, VCMA can realize the selection and switching function of the magnetic storage device. At the same time, it can realize the magnetic storage device while significantly reducing the current density required for magnetization reversal, so that the device size can be further reduced, and the write power consumption can be greatly reduced.

[0027] The drive circuit can be configured as follows: When a voltage V1 is applied between electrode 105-1 and pinned layer 101-1 of any memory device, the duration of voltage V1 is controlled by the word line and the amplitude of the voltage V1 pulse is controlled by the bit line. At this time, the device operates in VCMA mode, meaning the vertical anisotropy of CoFeB in the free layer 101-3 of the MTJ is voltage-regulated, controlling the critical switching current of the free layer 101-3. Applying a high bias voltage increases the free layer magnetization switching current, while applying a low bias voltage decreases it, thus achieving the function of a selection switch.

[0028] When a voltage V2 is applied between electrode 105-2 and pinned layer 101-1 of any memory device, the duration of voltage V2 is controlled by the word line and the amplitude of the voltage V2 pulse is controlled by the bit line. At this time, the device operates in STT mode. When current flows through pinned layer 101-1, the current is polarized, forming a spin-polarized current. This polarized current flows through a very thin isolation layer 101-2 to ensure high polarization. Spin-polarized electrons can transfer their spin angular momentum to the free layer 101-3, changing the magnetization equilibrium state of the free layer. The spin electrons transfer spin momentum to the magnetic moment of the free layer, causing the magnetic moment of the spin magnetic layer to gain spin momentum and change direction; this process is called spin transfer moment. By inputting current into the free layer, the magnetic moment of the free layer is flipped, thereby changing the resistance state of the magnetic tunnel junction and enabling data writing.

[0029] The resistance of the magnetic tunnel junction depends on the magnetization directions of the free layer 101-3 and the pinned layer 101-1. If the magnetization directions of the free layer 101-3 and the pinned layer 101-1 are the same, the resistance of the magnetic tunnel junction is low, and the magnetic tunnel junction is in a low-resistance state. Conversely, if the magnetization directions of the free layer 101-3 and the pinned layer 101-1 are opposite, the resistance of the magnetic tunnel junction is high, and the magnetic tunnel junction is in a high-resistance state. The magnetization direction of the pinned layer 101-1 is preset to a fixed direction; for example, a synthetic antiferromagnetic layer can be used to fix the magnetization direction of the pinned layer. The magnetization direction of the free layer 101-3 can be changed through a write operation. During subsequent data reading, the data stored in the memory can be determined by analyzing the resistance state of the magnetic tunnel junction through the read circuit.

[0030] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0031] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A memory cell of VCMA-STT MTJ, characterized in that: It includes: Multiple VCMA-STT MTJ storage devices; The driving circuit is configured to apply a voltage to the storage device, including applying a first voltage to regulate the critical switching current of the free layer of the MTJ; and applying a second voltage to regulate the magnetic moment direction of the free layer of the MTJ. The VCMA-STT MTJ memory device, from bottom to top, includes: a magnetic tunnel junction, a dielectric layer, wherein the pinned layer / isolation layer / free layer of the magnetic tunnel junction is specifically CoFeB / MgO / CoFeB, the dielectric layer is MgO, and the dielectric layer is in contact with the free layer; The first voltage of the driving circuit is applied between the dielectric layer and the pinned layer, and the second voltage is applied between the free layer and the pinned layer.

2. The storage unit according to claim 1, characterized in that: The magnetic tunnel junction is composed of CoFeB / MgO / CoFeB, where the thickness of MgO is 0.8-1 nm and the dielectric layer is composed of MgO with a thickness of 2-5 nm.

3. The storage unit according to claim 2, characterized in that: The driving circuit includes: each VCMA-STT MTJ device is connected to two bit lines and one word line, wherein the two bit lines are respectively connected to the dielectric layer and the free layer of the VCMA-STT MTJ device, and the word line is connected to the pinned layer of the VCMA-STT MTJ device.

4. A storage method for a storage cell as described in claim 1, characterized in that: a. Storage device switching selection: By adjusting the voltage of a bit line and applying different bias voltages, when a high bias voltage is applied, the free layer magnetization reversal current increases, and when a low bias voltage is applied, the free layer magnetization reversal current decreases. This means that the memory device is in VCMA mode, thus realizing the gating and switching function of the magnetic memory device. b. Writing stored information: By adjusting the voltage of another bit line and controlling the direction of the magnetic moment of the free layer to adjust the resistance of the magnetic tunnel junction, the storage device is in STT mode, thus enabling the writing of stored information.

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