Memory cell, semiconductor device, and memory

Abstract

An embodiment of the present disclosure provides a storage unit, a semiconductor device, and a memory, wherein the storage unit includes at least: a first transistor and a second transistor; the control end of the first transistor is connected to the control end of the second transistor, and the first end of the first transistor is connected to the first end of the second transistor; the second end of the first transistor is connected to a first voltage, and the second end of the second transistor is connected to a second voltage; the storage unit stores data based on the parasitic capacitance of the first transistor or the second transistor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a storage unit, a semiconductor device, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. A traditional DRAM memory cell consists of a transistor and a capacitor structure, where the gate of the transistor is connected to the word line, the source is connected to the bit line, and the drain is connected to the capacitor.

[0003] However, as DRAM integration increases, the capacitor structure within the DRAM memory cell continues to shrink, resulting in a continuous decrease in charge storage capacity and faster leakage. Furthermore, as DRAM feature sizes continue to shrink, the aspect ratio of the capacitor structure increases, making manufacturing increasingly difficult. Summary of the Invention

[0004] Embodiments of the present disclosure provide a storage unit, a semiconductor device, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory cell, comprising at least: a first transistor and a second transistor;

[0006] The control terminal of the first transistor is connected to the control terminal of the second transistor, and the first terminal of the first transistor is connected to the first terminal of the second transistor; the second terminal of the first transistor is connected to a first voltage, and the second terminal of the second transistor is connected to a second voltage;

[0007] The memory cell stores data based on a parasitic capacitance of the first transistor or the second transistor.

[0008] In some embodiments, further comprising a third transistor;

[0009] The control terminal of the third transistor is connected to the first terminal of the first transistor and the second transistor, the first terminal of the third transistor is connected to the control terminals of the first transistor and the second transistor, and the second terminal of the third transistor is connected to the second voltage;

[0010] The first transistor and the third transistor are used together to latch the data written into the storage unit, or,

[0011] The second transistor and the third transistor are used together to latch data written into the memory cell.

[0012] In some embodiments, the second transistor and the third transistor are PMOS transistors, and the first transistor is an NMOS transistor; the first voltage is less than the second voltage;

[0013] The parasitic capacitance of the first transistor is greater than the parasitic capacitance of the second transistor, and the width-to-length ratio of the second transistor is greater than or equal to twice the width-to-length ratio of the first transistor.

[0014] In some embodiments, the second transistor and the third transistor are NMOS transistors, the first transistor is a PMOS transistor; the first voltage is greater than the second voltage;

[0015] The parasitic capacitance of the second transistor is greater than the parasitic capacitance of the first transistor, and the width-to-length ratio of the first transistor is greater than or equal to twice the width-to-length ratio of the second transistor.

[0016] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: a memory array stacked sequentially along a third direction, the memory array comprising a plurality of memory cells according to any of the above embodiments arranged in an array along a first direction and a second direction, and a control transistor connected to each of the memory cells;

[0017] The control end of the control transistor is connected to the word line, the first end of the control transistor is connected to the bit line, and the second end of the control transistor is connected to the control ends of the first transistor and the second transistor in the memory cell;

[0018] The control transistor is at least used to control the storage unit to store data.

[0019] In some embodiments, a driving capability of the control transistor is greater than a driving capability of the third transistor.

[0020] In some embodiments, the control transistor is an NMOS transistor, and a width-to-length ratio of the control transistor is greater than a width-to-length ratio of the third transistor.

[0021] In some embodiments, the memory cells located in the same column along the first direction are connected to the same bit line through the control transistor; the memory cells located in the same row along the second direction are connected to the same word line through the control transistor.

[0022] In some embodiments, some of the memory cells located in the same column along the third direction are connected to the same bit line via the control transistor; or,

[0023] All the memory cells located in the same column along the third direction are connected to the same bit line via the control transistor.

[0024] In a third aspect, an embodiment of the present disclosure provides a memory comprising the semiconductor device described in any of the above embodiments.

[0025] The embodiments of the present disclosure provide a storage unit, a semiconductor device and a memory, wherein the storage unit includes at least: a first transistor and a second transistor; the control end of the first transistor is connected to the control end of the second transistor, and the first end of the first transistor is connected to the first end of the second transistor; the second end of the first transistor is connected to a first voltage, and the second end of the second transistor is connected to a second voltage; the storage unit stores data based on the parasitic capacitance of the first transistor or the second transistor. Since the storage unit in the embodiment of the present disclosure only includes the first transistor and the second transistor, and stores data based on the parasitic capacitance of the first transistor or the second transistor, there is no need to manufacture additional capacitors; and when storing data, the other end of the parasitic capacitance can be set to the first voltage or the second voltage, which is conducive to storing more charge compared to setting it to a fixed intermediate potential. In other words, it can have a longer data retention time without refreshing, or have a lower refresh frequency. In summary, compared with the storage unit in the related art, the integration area is smaller, the preparation difficulty is lower, the performance is higher, and the power consumption is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0027] Figure 1 A schematic diagram of a circuit structure of a storage unit provided in an embodiment of the present disclosure;

[0028] Figure 2 A schematic diagram of the circuit structure of another storage unit provided in an embodiment of the present disclosure;

[0029] Figure 3 A schematic diagram of a circuit structure of another storage unit provided in an embodiment of the present disclosure;

[0030] Figure 4 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 1 ;

[0031] Figure 5 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 2 ;

[0032] Figure 6 A schematic diagram of a circuit structure of a semiconductor device provided in an embodiment of the present disclosure;

[0033] Figure 7 A schematic diagram of the circuit structure of another semiconductor device provided in an embodiment of the present disclosure;

[0034] Figure 8 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0037] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the circuit structure of a storage unit 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the memory cell 10 at least includes: a first transistor MN1 and a second transistor MP2; wherein,

[0041] The control terminal of the first transistor MN1 is connected to the control terminal of the second transistor MP2, and the first terminal of the first transistor MN1 is connected to the first terminal of the second transistor MP2; the second terminal of the first transistor MN1 is connected to the first voltage, and the second terminal of the second transistor MP2 is connected to the second voltage;

[0042] The memory cell 10 stores data based on the parasitic capacitance of the first transistor MN1 .

[0043] It should be noted that the first transistor MN1 and the second transistor MP2 in the embodiment of the present disclosure form an inverter, wherein the control terminal of the first transistor MN1 and the control terminal of the second transistor MP2 are connected to form the input terminal of the inverter, and the first terminal of the first transistor MN1 and the first terminal of the second transistor MP2 are connected to form the output terminal of the inverter. The input terminal of the inverter receives a bitline signal transmitted by a bitline (BL) and inverts the bitline signal. For example, if the bitline input is high, the output terminal of the inverter outputs a low level. For another example, if the bitline input is low, the output terminal of the inverter outputs a high level.

[0044] It should also be noted that the first transistor MN1 and the second transistor MP2 are of opposite types. In some embodiments of the present disclosure, the first transistor MN1 is an NMOS transistor and the second transistor MP2 is a PMOS transistor. The first terminals of the first transistor MN1 and the second transistor MP2 are both drain terminals, and the second terminals of the first transistor MN1 and the second transistor MP2 are both source terminals.

[0045] In some embodiments, when the first transistor MN1 is an NMOS transistor and the second transistor is a PMOS transistor, the first voltage is less than the second voltage. For example, the first voltage may be the ground voltage Vss and the second voltage may be the power supply voltage Vcc.

[0046] In other embodiments, the first transistor may be a PMOS transistor, and the second transistor may be an NMOS transistor. In this case, data is stored through the gate capacitance of the second transistor.

[0047] It is worth noting that the memory cell 10 in the embodiment of the present disclosure stores data based on the gate capacitance of the first transistor MN1 . Thus, no additional capacitor is required, which reduces the area of ​​the memory cell 10 and improves the integration of the semiconductor device.

[0048] Next, combine Figure 1 The storage principle of the storage unit 10 in the embodiment of the present disclosure is described.

[0049] When writing "1", the bit line is at a high level. At this time, the first transistor MN1 is turned on and the second transistor MP2 is turned off. By maintaining the level of the control terminal of the first transistor MN1 at a high level, "1" can be stored.

[0050] When writing "0", the bit line is at a low level. At this time, the first transistor MN1 is turned off and the second transistor MP2 is turned on. At this time, by maintaining the level of the control terminal of the first transistor MN1 at a low level, "0" can be stored.

[0051] To read a "1," the bit line is set to a low state for charge sharing. Since the control terminal of the first transistor MN1 remains high when storing a "1," the voltage on the bit line can be pulled high when the control terminal of the first transistor MN1 shares charge with the bit line. This allows a "1" to be read after sensing and amplification.

[0052] To read a "0," the bit line is set to a low level for charge sharing. Since the control terminal of the first transistor MN1 remains low when storing a "0," the voltage on the bit line remains unchanged when the control terminal of the first transistor MN1 and the bit line share charge, enabling a "0" to be read.

[0053] The memory cell provided by the embodiment of the present disclosure only includes a transistor structure and stores data based on the parasitic capacitance of the transistor, so there is no need to manufacture additional capacitors. When storing data, the other end of the parasitic capacitance can be set to a first voltage or a second voltage, which is conducive to storing more charge compared to setting it to a fixed intermediate potential. In other words, it can have a longer data retention time without refreshing, or have a lower refresh frequency. In summary, compared with the memory cell in the related art, it has a smaller integration area, is less difficult to prepare, has higher performance, and lower power consumption.

[0054] In some embodiments, please refer to Figure 2 , which shows a structural diagram of another storage unit 10 provided by an embodiment of the present disclosure, such as Figure 2 As shown, the memory cell 10 further includes a third transistor MP3;

[0055] The control end of the third transistor MP3 is connected to the first end of the first transistor MN1 and the second transistor MP2, the first end of the third transistor MP3 is connected to the control ends of the first transistor MN1 and the second transistor MP2, and the second end of the third transistor MP3 is connected to the second voltage Vcc.

[0056] It should be noted that the type of the third transistor MP3 is the same as that of the second transistor MP2. In the embodiment of the present disclosure, the third transistor MP3 is a PMOS transistor, the first end of the third transistor MP3 is a drain end, and the second end of the third transistor MP3 is a source end.

[0057] It should also be noted that the control terminal of the third transistor MP3 is connected to the output terminal of the inverter, the first terminal of the third transistor MP3 is connected to the input terminal of the inverter, and the first transistor MN1 and the third transistor MP3 are used together to latch the data written into the storage unit 10.

[0058] In some embodiments, the parasitic capacitance of the first transistor MN1 is greater than the parasitic capacitance of the second transistor MP2. This is because during the data writing process, the parasitic capacitance of the gate of the first transistor MN1 is used to store the written data. Therefore, the parasitic capacitance of the first transistor MN1 needs to be set larger to store more charge, extend the data retention time, and shorten the refresh frequency, thereby achieving higher performance and lower power consumption of the memory cell provided by the embodiments of the present disclosure.

[0059] In some embodiments, the width-to-length ratio of the second transistor MP2 is greater than or equal to twice the width-to-length ratio of the first transistor MN1. This is because, for NMOS and PMOS transistors with the same width-to-length ratio, the NMOS transistor's conduction capability is greater than or equal to twice that of the PMOS transistor. In the disclosed embodiments, in order to enable the PMOS transistor (i.e., the second transistor MP2) and the NMOS transistor (i.e., the first transistor MN1) in the inverter to be turned on simultaneously, and to ensure that the output terminal of the inverter reaches the first voltage at the same time as the output terminal of the inverter reaches the second voltage, the width-to-length ratio of the second transistor MP2 needs to be set to be greater than or equal to twice the width-to-length ratio of the first transistor MN1.

[0060] Next, combine Figure 2 The storage principle of the storage unit 10 in the embodiment of the present disclosure is explained.

[0061] When writing a "1," the bit line is at a high level. At this point, the first transistor MN1 is turned on, and the second transistor MP2 is turned off. Since the first transistor MN1 is turned on, the first voltage Vss at the second terminal of the first transistor MN1 continuously supplies power to the control terminal of the third transistor MP3. The control terminal of the third transistor MP3 is at a low level, thus turning on the third transistor MP3. After the third transistor MP3 is turned on, the first voltage Vcc at the second terminal of the third transistor MP3 continuously supplies power to the control terminal of the first transistor MN1. Therefore, the control terminal of the first transistor MN1 remains at a high level, thus storing a "1."

[0062] It should be noted that, in the embodiment of the present disclosure, the first transistor MN1 and the third transistor MP3 form a loop. Since the first voltage Vcc at the second end of the third transistor MP3 continuously supplies power to the control end of the first transistor MN1, "1" is always stored in the gate capacitance of the first transistor MN1 and does not disappear. That is, the first transistor MN1 and the third transistor MP3 are jointly used to latch the data "1" written into the storage unit 10.

[0063] When writing a "0," the bit line is at a low level. At this point, the first transistor MN1 is off, and the second transistor MP2 is on. Since the second transistor MP2 is on, the second voltage Vcc at the second terminal of the second transistor MP2 continuously supplies power to the control terminal of the third transistor MP3. The control terminal of the third transistor MP3 is at a high level, and therefore, the third transistor MP3 remains off. At this point, the control terminal of the first transistor MN1 remains at a low level, allowing the "0" to be stored.

[0064] It should be noted that when writing "0", since the second voltage Vcc at the second terminal of the second transistor MP2 continuously supplies power to the control terminal of the third transistor MP3, the voltage at the control terminal of the third transistor MP3 continues to increase. At this time, since the gate of the first transistor MN1 is in a low-level state, it will attract external charge to continuously diffuse to the gate of the first transistor MN1, that is, charge accumulation occurs, causing the voltage at the control terminal of the first transistor MN1 to continue to increase. However, the voltage at the control terminal of the first transistor MN1 cannot turn on the first transistor MN1 (that is, the charge accumulation cannot exceed the threshold voltage of the first transistor MN1). If the voltage at the control terminal of the first transistor MN1 accumulates to a level that can turn on the first transistor MN1, the third transistor MP3 will also turn on. At this time, the data stored in the gate capacitance of the first transistor MN1 will be flipped. Therefore, when storing "0", the charge at the control terminal of the first transistor MN1 needs to be periodically discharged, that is, refreshed.

[0065] To read a "1," the bit line is set to a low level, enabling charge sharing. Since the control terminal of the first transistor MN1 remains high when storing a "1," the voltage on the bit line can be pulled up to "1" when the control terminal of the first transistor MN1 and the bit line share charge, enabling a "1" to be read.

[0066] To read a "0," the bit line is set to a low level for charge sharing. Since the control terminal of the first transistor MN1 remains low when storing a "0," the voltage on the bit line remains unchanged when the control terminal of the first transistor MN1 and the bit line share charge, enabling a "0" to be read.

[0067] In another embodiment of the present disclosure, reference is made to Figure 3 , which shows a circuit structure diagram of another storage unit 10 provided by an embodiment of the present disclosure. Figure 3 As shown, the memory cell 10 includes: a first transistor MP1, a second transistor MN2 and a third transistor MN3; wherein,

[0068] A control terminal of the first transistor MP1 is connected to a control terminal of the second transistor MN2, and a first terminal of the first transistor MP1 is connected to a first terminal of the second transistor MN2; a second terminal of the first transistor MP1 is connected to a first voltage, and a second terminal of the second transistor MN2 is connected to a second voltage; a control terminal of the third transistor MN3 is connected to the first terminals of the first transistor MP1 and the second transistor MN2, a first terminal of the third transistor MN3 is connected to the control terminals of the first transistor MP1 and the second transistor MN2, and a second terminal of the third transistor MN3 is connected to the second voltage;

[0069] The memory cell 10 stores data based on the parasitic capacitance of the second transistor MN2 , and the second transistor MN2 and the third transistor MN3 are used together to latch the data written into the memory cell 10 .

[0070] It should be noted that in the embodiment of the present disclosure, the first transistor MP1 and the second transistor MN2 form an inverter, and the third transistor MN3 is of the same type as the second transistor MN2. The first transistor MP1 is a PMOS transistor, and the second transistor MN2 and the third transistor MN3 are NMOS transistors. The first terminals of the first transistor MP1, the second transistor MN2, and the third transistor MN3 are all drain terminals, and the second terminals of the first transistor MP1, the second transistor MN2, and the third transistor MN3 are all source terminals.

[0071] In some embodiments, when the first transistor MP1 is a PMOS transistor and the second transistor MN2 is an NMOS transistor, the first voltage is greater than the second voltage. For example, the first voltage may be the power supply voltage Vcc and the second voltage may be the ground voltage Vss.

[0072] In some embodiments, the parasitic capacitance of the second transistor MN2 is greater than the parasitic capacitance of the first transistor MP1. This is because during the data writing process, the parasitic capacitance of the gate of the second transistor MN2 is used to store the written data. Therefore, the parasitic capacitance of the second transistor MN2 needs to be set larger to store more charge, extend the data retention time, and shorten the refresh frequency, thereby achieving higher performance and lower power consumption of the memory cell provided by the embodiments of the present disclosure.

[0073] In some embodiments, the width-to-length ratio of the first transistor MP1 is greater than or equal to twice the width-to-length ratio of the second transistor MN2. This is because, for NMOS and PMOS transistors with the same width-to-length ratio, the conduction capability of the NMOS transistor is greater than or equal to twice that of the PMOS transistor. In the embodiments of the present disclosure, in order to enable the PMOS transistor (i.e., the first transistor MP1) and the NMOS transistor (i.e., the second transistor MN2) in the inverter to be turned on simultaneously and to enable the output terminal of the inverter to reach the first voltage or the second voltage within the same time, the width-to-length ratio of the first transistor MP1 needs to be set to be greater than or equal to twice the width-to-length ratio of the second transistor MN2.

[0074] Next, combine Figure 3 The storage principle of the storage unit 10 in the embodiment of the present disclosure is explained.

[0075] When writing "1", the bit line is at a high level. At this time, the first transistor MP1 is turned off, the second transistor MN2 is turned on, and the third transistor MN2 is turned off. At this time, the control end of the third transistor MN2 is always kept at a low level, while the control end of the second transistor MN2 is always kept at a high level, so that "1" can be stored.

[0076] When writing "0", the bit line is at a low level. At this time, the first transistor MP1 is turned on and the second transistor MN2 is turned off. Since the first transistor MP1 is turned on, the second voltage Vcc at the second terminal of the first transistor MP1 continuously supplies power to the control terminal of the third transistor MN3. The control terminal of the third transistor MN3 is at a high level. Therefore, the third transistor MN3 is turned on. At this time, the control terminal of the second transistor MN2 is always maintained at a low level, and "0" can be stored.

[0077] It should be noted that when writing "0", since the second voltage Vcc at the second terminal of the first transistor MP1 continuously supplies power to the control terminal of the third transistor MN3, the voltage at the control terminal of the third transistor MN3 continues to increase. At this time, since the gate of the second transistor MN2 is in a low-level state, it will attract external charge to continuously diffuse to the gate of the second transistor MN2, that is, charge accumulation occurs, causing the voltage at the control terminal of the second transistor MN2 to continue to increase. However, the voltage at the control terminal of the second transistor MN2 cannot turn on the second transistor MN2 (that is, the charge accumulation cannot exceed the threshold voltage of the second transistor MN2). If the voltage at the control terminal of the second transistor MN2 accumulates to a level that can turn on the second transistor MN2, then the third transistor MN3 will be turned off. At this time, the data stored in the gate capacitor of the second transistor MN2 will be flipped. Therefore, it is necessary to regularly discharge the charge in the gate capacitor of the second transistor MN2, that is, refresh it.

[0078] To read a "1," the bit line is set to a low state for charge sharing. Since the control terminal of the second transistor MN2 remains high when storing a "1," the voltage on the bit line can be pulled up to "1" when the control terminal of the second transistor MN2 and the bit line share charge, enabling a "1" read.

[0079] To read a "0," the bit line is set to a low level for charge sharing. Since the control terminal of the second transistor MN2 remains low when storing a "0," the voltage on the bit line remains unchanged when the control terminal of the second transistor MN2 and the bit line share charge, enabling a "0" read.

[0080] In another embodiment of the present disclosure, see Figure 4 and Figure 5 , which shows a schematic structural diagram of a semiconductor device 20 provided by an embodiment of the present disclosure, wherein: Figure 4 and Figure 5 The semiconductor devices 20 with different numbers of memory cells 10 are shown respectively. Figure 4 A storage unit 10 is shown, Figure 5 Two storage units 10 are shown. Figure 4 and Figure 5As shown, the semiconductor device 20 includes a memory array stacked sequentially along a third direction, the memory array includes a plurality of memory cells 10 arranged in an array along a first direction and a second direction, and a control transistor MN4 connected to each memory cell;

[0081] The control end of the control transistor MN4 is connected to the word line (WL), the first end of the control transistor MN4 is connected to the bit line BL, and the second end of the control transistor MN4 is connected to the control ends of the first transistor and the second transistor in the memory cell 10;

[0082] The control transistor MN4 is at least used to control the memory cell 10 to store data.

[0083] It should be noted that, in the embodiment of the present disclosure, the memory cell 10 and the control transistor MN4 are formed on the substrate ( Figure 4 and Figure 5 The substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor materials, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof. In other embodiments, the substrate may be an N-type doped substrate or a P-type doped substrate.

[0084] It should also be noted that the first direction, the second direction and the third direction are defined as Figure 4 and Figure 5 The X-axis, Y-axis, and Z-axis directions are parallel to the plane of the substrate, and the Z-axis intersects the plane of the substrate (for example). In some embodiments, the X-axis, Y-axis, and Z-axis directions may be perpendicular to each other. In other embodiments, the X-axis, Y-axis, and Z-axis directions may not be perpendicular to each other.

[0085] In some embodiments, memory cells 10 in the same column along the X-axis are connected to the same bit line BL through the control transistor MN4 ; memory cells 10 in the same row along the Y-axis are connected to the same word line WL through the control transistor MN4 .

[0086] It should be noted that, in the embodiment of the present disclosure, some memory cells 10 located in the same column along the Z-axis direction are connected to the same bit line BL via the control transistor MN4. For example, Figure 5The two memory cells 10 above and below along the Z axis share the same bit line BL. The above-mentioned “part of the memory cells 10” refers to every two non-overlapping memory cells 10 in the Z direction.

[0087] It should also be noted that all memory cells 10 located in the same column along the Z-axis are connected to the same bit line 12 via the control transistor MN4. In implementation, contact holes can be formed between adjacent memory cells 10 along the Z-axis, and the bit lines of adjacent memory cells 10 can be connected through the contact holes, thereby achieving connection between all memory cells 10 along the Z-axis.

[0088] In some embodiments, see Figure 6 , which shows a circuit structure diagram of a semiconductor device 20 provided by an embodiment of the present disclosure. Figures 2 to 6 As shown, the semiconductor device 20 includes a memory cell 10 and a control transistor MN4 connected to the memory cell 10. The memory cell 10 includes: a first transistor MN1, a second transistor MP2, and a third transistor MP3; the control terminal of the first transistor MN1 is connected to the control terminal of the second transistor MP2, and the first terminal of the first transistor MN1 is connected to the first terminal of the second transistor MP2; the second terminal of the first transistor MN1 is connected to the first voltage Vss, and the second terminal of the second transistor MP2 is connected to the second voltage Vcc; the control terminal of the third transistor MP3 is connected to the first terminals of the first transistor MN1 and the second transistor MP2, the first terminal of the third transistor MP3 is connected to the control terminals of the first transistor MN1 and the second transistor MP2, and the second terminal of the third transistor MP3 is connected to the second voltage Vcc.

[0089] In the embodiment of the present disclosure, the first transistor MN1 is an NMOS transistor, and the second transistor MP2 and the third transistor MP3 are PMOS transistors.

[0090] Next, combine Figure 6 The working principle of the semiconductor device 20 in the embodiment of the present disclosure is described below.

[0091] Writing process: The voltage of the control word line WL is greater than the threshold voltage of the control transistor MN4, so that the control transistor MN4 is in a fully turned-on state. At this time, the signal on the bit line BL is quickly transmitted to the second end of the control transistor MN4 to perform the writing process. The specific writing process is the same as the data storage process in the above embodiment and will not be repeated here.

[0092] During the reading process, the voltage of the control word line WL is smaller than and close to the threshold voltage of the control transistor MN4, so that the control transistor MN4 is in a sub-threshold state. At this time, the bit line BL is set to a low level state to perform a reading operation.

[0093] It should be noted that the time for reading "1" in the embodiment of the present disclosure cannot be too long. If the reading is too long, the gate voltage of the first transistor MN1 will be pulled down to a low level. In this way, the control end of the second transistor MP2 will also be in a low level state. In this way, the second transistor MP2 will be turned on. At this time, the gate voltage of the first transistor MN1 is low, which can be considered to store "0", and the data will be flipped.

[0094] During the refresh process, the voltage of the control word line WL is less than and close to the threshold voltage of the control transistor MN4, so that the control transistor MN4 is in a subthreshold state. At this time, the bit line BL is set to a low level state to discharge the charge accumulated in the gate of the first transistor MN1 to achieve data refresh.

[0095] It should be noted that in the disclosed embodiment, the refresh processing interval is a preset duration; wherein, during the preset duration, the voltage at the control terminal of the first transistor MN1 is less than or equal to the first voltage Vss, and the voltage at the control terminal of the first transistor MN1 is less than the threshold voltage of the first transistor MN1. In other words, the voltage at the control terminal of the first transistor MN1 is detected to be less than or equal to the first voltage Vss, and if it is greater than the first voltage Vss, the refresh operation is performed.

[0096] It should also be noted that, during the reading process and the refreshing process, the conduction degree of the control transistor MN4 is less than the conduction degree of the third transistor MP3.

[0097] In some embodiments, the driving capability of the control transistor MN4 is greater than the driving capability of the third transistor MP3 .

[0098] Furthermore, the control transistor MN4 is an NMOS transistor, and the width-to-length ratio of the control transistor MN4 is greater than the width-to-length ratio of the third transistor MP3.

[0099] In the disclosed embodiment, the control transistor MN4 is a read-write control transistor. When a high level is written, the first transistor MN1 and the third transistor MP3 are turned on, and the second transistor MP2 is turned off. The signal is latched to a high level and will not disappear even if it is not refreshed. When a low level is written, the first transistor MN1 and the third transistor MP3 are turned off, and the second transistor MP2 is turned on. As long as the charge accumulated at the control terminal of the first transistor MN1 is regularly refreshed to release the charge so that the control terminal of the first transistor MN1 is kept at a low potential, the stored information can be kept unchanged. When refreshing, it is only necessary to periodically open the control transistor MN4 to release the charge. The refresh can be completed without reading the stored content. In this way, power consumption can be significantly reduced (the power consumption consumed when refreshing data is extremely small).

[0100] It should be noted that in the disclosed embodiments, the wordline control signals for writing data differ from those for reading data and refreshing data. When writing data, control transistor MN4 must be fully on, ensuring that its current capability is greater than that of third transistor MP3. This allows the internal state to be quickly switched to the appropriate state. Reading and refreshing data operate in the same manner: first, the bitline is set to a low level, and then the wordline signal is used to control control transistor MN4 to operate in the subthreshold region (i.e., the current capability of control transistor MN is less than that of MP15 to prevent data flipping). If the bitline potential can be pulled high, a "1" is read; if there is no significant change in the bitline potential, a "0" is read.

[0101] It should also be noted that in the embodiment of the present disclosure, data is refreshed while data is read. To reduce power consumption, the on-time of the transistor MN4 during refresh can be shortened as much as possible to effectively discharge the charge accumulated on the gate of the first transistor MN1.

[0102] Reasonably setting the width-to-length ratio of the first transistor MN1 and the second transistor MP2 to increase the flip point of the inverter formed by the second transistor MP2 and the first transistor MN1 can effectively reduce the power consumption when changing data from 1 to 0. In order to obtain a suitable refresh time without increasing power consumption, a negative voltage (less than the voltage at the source of the first transistor MN1) is stored at the gate of MN25 when writing data 0. When the charge accumulates to the point where the gate voltage of the first transistor MN1 equals Vss (the source voltage of the first transistor MN1), the first transistor MN1 is refreshed so that it always operates in the cutoff region. When the gate voltage of the first transistor MN1 is Vss (the source voltage of the first transistor MN1), once charge accumulates, the gate voltage of the first transistor MN1 increases and enters the subthreshold region. At this time, if the refresh is not timely, additional power consumption will be generated.

[0103] In addition, the semiconductor device provided by the embodiment of the present disclosure is a pure transistor structure, which facilitates three-dimensional integration.

[0104] In some embodiments, see Figure 7 , which shows a circuit structure diagram of another semiconductor device 20 provided by an embodiment of the present disclosure. Figure 7As shown, the semiconductor device 20 includes a memory cell 10 and a control transistor MN4 connected to the memory cell 10. The memory cell 10 includes: a first transistor MP1, a second transistor MN2, and a third transistor MN3; the control terminal of the first transistor MP1 is connected to the control terminal of the second transistor MN2, and the first terminal of the first transistor MP1 is connected to the first terminal of the second transistor MN2; the second terminal of the first transistor MP1 is connected to the first voltage Vcc, and the second terminal of the second transistor MN2 is connected to the second voltage Vss; the control terminal of the third transistor MN3 is connected to the first terminals of the first transistor MP1 and the second transistor MN2, the first terminal of the third transistor MN3 is connected to the control terminals of the first transistor MP1 and the second transistor MN2, and the second terminal of the third transistor MN3 is connected to the second voltage Vcc.

[0105] In the embodiment of the present disclosure, the first transistor MP1 is a PMOS transistor, and the second transistor MN2 and the third transistor MN3 are NMOS transistors.

[0106] Next, combine Figure 7 The working principle of the semiconductor device 20 in the embodiment of the present disclosure is described below.

[0107] Writing process: The voltage of the control word line WL is greater than the threshold voltage of the control transistor MN4, so that the control transistor MN4 is in a fully turned-on state. At this time, the signal on the bit line BL is quickly transmitted to the second end of the control transistor MN4 to perform the writing process. The specific writing process is the same as the data storage process in the above embodiment and will not be repeated here.

[0108] During the reading process, the voltage of the control word line WL is smaller than and close to the threshold voltage of the control transistor MN4, so that the control transistor MN4 is in a sub-threshold state. At this time, the bit line BL is set to a low level state to perform a reading operation.

[0109] It should be noted that when reading "1" in the embodiment of the present disclosure, the time cannot be too long. If the reading is carried out for a long time, the gate voltage of the second transistor MN2 will be pulled down to a low level. In this way, the control end of the first transistor MP1 will also be in a low level state. In this way, the first transistor MP1 will be turned on. At this time, the gate voltage of the second transistor MN2 is low, which can be considered to store "0", and the data will be flipped.

[0110] During the refresh process, the voltage of the control word line WL is less than and close to the threshold voltage of the control transistor MN4, so that the control transistor MN4 is in a sub-threshold state. At this time, the bit line BL is set to a low level state to discharge the charge accumulated in the gate of the second transistor MN2 to achieve data refresh.

[0111] It should be noted that, in the embodiment of the present disclosure, the time interval of the refresh process is a preset duration; wherein, within the preset duration, the voltage accumulated at the control terminal of the second transistor MN2 is less than the threshold voltage of the second transistor MN2.

[0112] It should also be noted that, during the reading process and the refreshing process, the conduction degree of the control transistor MN4 is less than the conduction degree of the third transistor MN3.

[0113] In some embodiments, the driving capability of the control transistor MN4 is greater than the driving capability of the third transistor MP3 .

[0114] Furthermore, the control transistor MN4 is an NMOS transistor, and its width-to-length ratio is greater than that of the third transistor MP3. This allows for efficient data writing. This is because only when the drive capability of the control transistor MN4 is greater than that of the third transistor MP3 can a "0" be written while a "1" is being stored, thereby lowering the potential at the inverter input. Otherwise, the potential at the inverter input cannot be lowered, and the data "0" cannot be stored.

[0115] The semiconductor device provided by the embodiment of the present disclosure includes the memory cell in the above embodiment. Since the memory cell only includes a first transistor and a second transistor and stores data based on the parasitic capacitance of the first transistor or the second transistor, there is no need to manufacture additional capacitors. When storing data, the other end of the parasitic capacitance can be set to the first voltage or the second voltage, which is conducive to storing more charge compared to setting it to a fixed intermediate potential. In summary, compared with the memory cell in the related art, the integration area is smaller, the preparation difficulty is lower, the performance is higher, and the power consumption is lower. Therefore, the embodiment of the present disclosure can provide a semiconductor device with excellent performance, small area, and easy preparation.

[0116] In another embodiment of the present disclosure, see Figure 8 , which shows a schematic diagram of the structure of a memory 30 provided by an embodiment of the present disclosure. Figure 8 As shown, the memory 30 at least includes the semiconductor device 20 described in any one of the aforementioned embodiments.

[0117] In some embodiments, the memory 30 may include DRAM. The DRAM may conform to memory specifications such as Double Data Rate (DDR), DDR2, DDR3, DDR4, and DDR5, and may also conform to memory specifications such as Low Power Double Data Rate SDRAM (LPDDR), LPDDR2, LPDDR3, LPDDR4, and LPDDR5, without any limitation herein.

[0118] In the embodiment of the present disclosure, the semiconductor device 20 mainly relates to the structure of the storage unit in the semiconductor device 20 (see Figure 2 and Figure 3 ). Specifically, the semiconductor device 20 includes a memory array stacked in sequence along a third direction, the memory array including a plurality of memory cells arranged in an array along a first direction and a second direction, and a control transistor connected to each memory cell; wherein the control terminal of the control transistor is connected to a word line, the first terminal of the control transistor is connected to a bit line, and the second terminal of the control transistor is connected to the memory cell; the control transistor is at least used to control the memory cell to store data. The memory cell includes: a first transistor, a second transistor, and a third transistor; wherein the control terminal of the first transistor is connected to the control terminal of the second transistor, and the first terminal of the first transistor is connected to the first terminal of the second transistor; the second terminal of the first transistor is connected to a first voltage, and the second terminal of the second transistor is connected to a second voltage; the control terminal of the third transistor is connected to the first terminal of the first transistor and the second transistor, the first terminal of the third transistor is connected to the control terminal of the first transistor and the second transistor, and the second terminal of the third transistor is connected to a second voltage; the memory cell stores data based on the parasitic capacitance of the first transistor or the second transistor, and the first transistor or the second transistor and the third transistor are used together to latch the data written into the memory cell.

[0119] In some embodiments, the second transistor and the third transistor are PMOS transistors, and the first transistor is an NMOS transistor; the first voltage is less than the second voltage; the parasitic capacitance of the first transistor is greater than the parasitic capacitance of the second transistor, and the width-to-length ratio of the second transistor is more than twice the width-to-length ratio of the first transistor.

[0120] In some embodiments, the second transistor and the third transistor are NMOS transistors, and the first transistor is a PMOS transistor; the first voltage is greater than the second voltage; the parasitic capacitance of the second transistor is greater than the parasitic capacitance of the first transistor, and the width-to-length ratio of the first transistor is greater than or equal to twice the width-to-length ratio of the second transistor.

[0121] In some embodiments, a driving capability of the control transistor is greater than a driving capability of the third transistor.

[0122] In some embodiments, the control transistor is an NMOS transistor, and a width-to-length ratio of the control transistor is greater than a width-to-length ratio of the third transistor.

[0123] It should be noted that the semiconductor device in the memory of the embodiment of the present disclosure is similar to the semiconductor device in the above embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0124] The memory provided by the embodiment of the present disclosure includes the semiconductor device and memory unit in the above-mentioned embodiment. Since the memory unit only includes a first transistor and a second transistor, and stores data based on the parasitic capacitance of the first transistor or the second transistor, there is no need to manufacture additional capacitors. When storing data, the other end of the parasitic capacitance can be set to the first voltage or the second voltage, which is conducive to storing more charges compared to setting it to a fixed intermediate potential. Compared with the memory cell in the related art, it has a smaller integration area, less difficulty in preparation, higher performance, and lower power consumption. Therefore, the embodiment of the present disclosure can provide a memory with a small area, easy preparation, and excellent performance.

[0125] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0126] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0127] The above are only some implementations of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present disclosure should be included in the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A memory array stacked sequentially along a third direction, the memory array comprising a plurality of memory cells arranged in an array along a first direction and a second direction, and a control transistor connected to each of the memory cells; the memory cells being composed of a first transistor, a second transistor, and a third transistor, wherein the control terminal of the first transistor is connected to the control terminal of the second transistor, and the first terminal of the first transistor is connected to the first terminal of the second transistor; the second terminal of the first transistor is connected to a first voltage, and the second terminal of the second transistor is connected to a second voltage; the control terminal of the third transistor is connected to the first terminals of the first and second transistors, the first terminal of the third transistor is connected to the control terminals of the first and second transistors, and the second terminal of the third transistor is connected to the second voltage; The storage unit stores data based on the parasitic capacitance of the first transistor or the second transistor; the first transistor and the third transistor are used together to latch the data written into the storage unit, or the second transistor and the third transistor are used together to latch the data written into the storage unit; The control end of the control transistor is connected to the word line, the first end of the control transistor is connected to the bit line, and the second end of the control transistor is connected to the control ends of the first transistor and the second transistor in the memory cell; The control transistor is at least used to control the storage unit to store data; The first transistor, the second transistor, and the third transistor constituting each of the memory cells and the corresponding control transistor serve as endpoints, forming a rectangular arrangement.

2. The semiconductor device according to claim 1, wherein The driving capability of the control transistor is greater than the driving capability of the third transistor.

3. The semiconductor device according to claim 2, wherein The control transistor is an NMOS transistor, and the width-to-length ratio of the control transistor is greater than the width-to-length ratio of the third transistor.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The memory cells located in the same column along the first direction are connected to the same bit line through the control transistor; the memory cells located in the same row along the second direction are connected to the same word line through the control transistor.

5. The semiconductor device according to claim 4, wherein Some of the memory cells located in the same column along the third direction are connected to the same bit line via the control transistor; or, All the memory cells located in the same column along the third direction are connected to the same bit line via the control transistor. The storage unit according to claim 1 , wherein: The second transistor and the third transistor are PMOS transistors, and the first transistor is an NMOS transistor; the first voltage is less than the second voltage; The parasitic capacitance of the first transistor is greater than the parasitic capacitance of the second transistor, and the width-to-length ratio of the second transistor is greater than or equal to twice the width-to-length ratio of the first transistor.

7. The storage unit according to claim 1, wherein: The second transistor and the third transistor are NMOS transistors, and the first transistor is a PMOS transistor; the first voltage is greater than the second voltage; The parasitic capacitance of the first transistor is greater than the parasitic capacitance of the second transistor, and the width-to-length ratio of the first transistor is greater than or equal to twice the width-to-length ratio of the second transistor.

8. A memory, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 7.

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