Base Chip, Memory System, and Semiconductor Structure

Abstract

An embodiment of the present application provides a basic chip, a storage system, and a semiconductor structure. The basic chip includes: The basic chip is configured to receive first data in a write stage and perform error correction code encoding processing to generate encoded data, transmit second data to a storage chip in the write stage, the second data including the first data and the encoded data, receive the second data from the storage chip in a read stage and perform error detection and correction processing, and transmit third data in the read stage, the third data being the first data after the error detection and correction processing. The embodiments of the present application are beneficial to improving the storage performance of the storage system.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a basic chip, a storage system, and a semiconductor structure. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. As a volatile storage, Dynamic Random Access Memory (DRAM) has the advantages of high storage density, fast read and write speed, etc., and is widely used in various electronic systems.

[0003] As the manufacturing process of DRAM becomes more and more advanced and the storage density becomes higher and higher, the stored data in DRAM may be incorrect, seriously affecting the performance of DRAM. Therefore, Error Checking and Correction (ECC) technology is usually adopted in DRAM to detect or correct the errors of the stored data. Summary of the Invention

[0004] Embodiments of the present application provide a basic chip, a storage system, and a semiconductor structure, which are at least beneficial to solving the problem of tight area of the controller or the storage chip.

[0005] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a basic chip applied to a storage system, including: the basic chip is configured to receive first data and perform error correction code encoding processing to generate encoded data in a write stage, transmit second data to a storage chip in the write stage, the second data including the first data and the encoded data, receive the second data from the storage chip and perform error detection and correction processing in a read stage, and transmit third data in the read stage, the third data being the first data after the error detection and correction processing.

[0006] In addition, the basic chip includes: an encoding module configured to receive the first data and perform the error correction code encoding processing to generate the encoded data in the write stage; an error detection and correction module configured to receive the second data and perform the error detection and correction processing in the read stage.

[0007] In addition, the base chip further includes: a first serial-to-parallel conversion module configured to receive the first data during the write phase, perform a first serial-to-parallel conversion process on the first data, and transmit the first data after the first serial-to-parallel conversion process to the encoding module; a first parallel-to-serial conversion module configured to receive the third data during the read phase, perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

[0008] In addition, the base chip further includes: a second parallel-to-serial conversion module configured to receive the second data from the encoding module during the write phase, perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module configured to receive the second data from the storage chip during the read phase, perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the error detection and correction module.

[0009] In addition, the base chip is further configured to generate an error detection flag signal during the error detection and correction process, and record the error situation of the first data during transmission based on the error detection flag signal.

[0010] In addition, the base chip further includes: a storage buffer module configured to store the error situation of the first data during transmission; a command module that receives a polling instruction and generates a command signal and a clock signal; the storage buffer module is further configured to output a characterization signal based on the command signal and the clock signal, and the characterization signal characterizes the error situation of the first data during transmission.

[0011] In addition, the storage buffer module includes a first-in, first-out register.

[0012] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a storage system, including a controller, a base chip, and a storage chip; the controller is configured to transmit first data to the base chip during a write phase; the base chip is configured to receive the first data during the write phase and perform error correction code encoding processing to generate encoded data, transmit second data to the storage chip during the write phase, the second data including the first data and the encoded data, receive the second data from the storage chip during a read phase and perform error detection and correction processing, and transmit third data to the controller during the read phase, the third data being the first data after the error detection and correction processing; the storage chip is configured to receive the second data from the base chip during the write phase and store the second data, and transmit the second data to the base chip during the read phase.

[0013] In addition, the base chip includes: an encoding module configured to receive the first data during the write phase and perform the error correction code encoding processing to generate the encoded data; an error detection and correction module configured to receive the second data during the read phase and perform the error detection and correction processing.

[0014] In addition, the base chip further includes: a first serial-to-parallel conversion module configured to receive the first data during the write phase and perform a first serial-to-parallel conversion process on the first data, and transmit the first data after the first serial-to-parallel conversion process to the encoding module; a first parallel-to-serial conversion module configured to receive the third data during the read phase and perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

[0015] In addition, the base chip further includes: a second parallel-to-serial conversion module configured to receive the second data from the encoding module during the write phase and perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module configured to receive the second data from the storage chip during the read phase and perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the error detection and correction module.

[0016] In addition, the number of data transmission channels between the controller and the base chip is M, and the number of data transmission channels between the base chip and the storage chip is N; where M and N are both positive integers greater than 1, and N is greater than M.

[0017] In addition, the base chip is further configured to generate an error detection flag signal during the error detection and correction process, and record the error condition of the first data during transmission based on the error detection flag signal; the storage system further includes: a register configured to store the error condition of the first data during transmission.

[0018] In addition, the base chip includes: a storage buffer module configured to store the error condition of the first data during transmission; a command module that receives a polling instruction and generates a command signal and a clock signal; the storage buffer module is further configured to output a characterization signal to the register based on the command signal and the clock signal, where the characterization signal characterizes the error condition of the first data during transmission.

[0019] In addition, the controller is further configured to issue the polling instruction to the command module.

[0020] According to some embodiments of the present application, yet another aspect of the embodiments of the present application further provides a semiconductor structure, including: a carrier substrate; the above storage system, where the controller and the base chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

[0021] The technical solutions provided by the embodiments of the present application have the following advantages:

[0022] In the technical solution of the base chip provided by the embodiments of the present application, the base chip performs error correction code encoding processing on the first data in the writing stage to generate encoded data, and the parallel storage chip transmits the second data including the first data and the encoded data; and the base chip receives the second data from the storage chip in the reading stage and performs error detection basic processing, and transmits the third data, where the third data is the first data after error detection and correction processing. Therefore, the base chip has an encoding processing function and an error detection and correction function, such that neither the controller nor the storage chip in the storage system needs to have an encoding processing function and an error detection and correction function, which is beneficial to improving the performance of the controller and the storage chip, and rationally utilizing the chip area of the base chip, and thus is beneficial to improving the storage performance of the storage system. Description of the Drawings

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the drawings do not constitute a scale limitation.

[0024] Figure 1 It is a schematic structural diagram of a semiconductor structure;

[0025] Figure 2 For Figure 1 Schematic diagram of data transmission in the provided semiconductor structure;

[0026] Figure 3 Schematic diagram of the first structure of the basic chip provided by an embodiment of the present application;

[0027] Figure 4 Schematic diagram of the second structure of the basic chip provided by an embodiment of the present application;

[0028] Figure 5 Schematic diagram of the third structure of the basic chip provided by an embodiment of the present application;

[0029] Figure 6 Schematic diagram of the fourth structure of the basic chip provided by an embodiment of the present application;

[0030] Figure 7 Schematic diagram of the fifth structure of the basic chip provided by an embodiment of the present application;

[0031] Figure 8 Schematic diagram of the first structure of the storage system provided by an embodiment of the present application;

[0032] Figure 9 Schematic diagram of the second structure of the storage system provided by an embodiment of the present application;

[0033] Figure 10 Schematic diagram of the third structure of the storage system provided by an embodiment of the present application;

[0034] Figure 11 Schematic diagram of the fourth structure of the storage system provided by an embodiment of the present application;

[0035] Figure 12 Schematic diagram of the fifth structure of the storage system provided by an embodiment of the present application;

[0036] Figure 13 Schematic diagram of the cross-sectional structure of the semiconductor structure provided by an embodiment of the present application. Detailed implementation manners

[0037] Figure 1 Schematic diagram of the structure of a semiconductor structure, Figure 2 For Figure 1 Schematic diagram of data transmission in the provided semiconductor structure.

[0038] Refer to Figure 1, a semiconductor structure may include: a substrate 11; a base die 12 and a processor 13 respectively located on the surface of the substrate 11; a plurality of core dies 14 are stacked on the base die 12, and the core die 14 may be a DRAM chip. Refer to Figure 2 , during the data transmission process in the semiconductor structure, it includes: in the write stage, the controller 13 transmits data to the base die 12, and the base die 12 transmits the data into the core die 14. Before transmitting the data, the controller 13 may first perform error correction code encoding processing on the data; in the read stage, the core die 14 transmits the data to the base die 12, and then the base die 12 transmits the data to the controller 13. The controller 13 receives the data and performs error correction code decoding processing to detect and correct errors in the data.

[0039] It is not difficult to find that in the above semiconductor structure, the base die 12 does not participate in the error detection and correction process, that is, there is no error correction code encoding function and corresponding error detection and correction function in the base die 12. It is necessary for the controller 13 or the core die 14 to complete the error detection, which makes the chip area of the controller 13 and the core die 14, where the chip area is already tight, even more tense. Therefore, the performance of the controller 13 and the core die 14 is affected, and further the storage performance of the entire semiconductor structure needs to be improved.

[0040] The present application provides a base die, a storage system, and a semiconductor structure, and the base die has an error detection and correction function. Figure 3 It is the first structural schematic diagram of the base die provided by the embodiment of the present application. Figure 4 It is the second structural schematic diagram of the base die provided by the embodiment of the present application. Figure 5 It is the third structural schematic diagram of the base die provided by the embodiment of the present application. Figure 6 It is the fourth structural schematic diagram of the base die provided by the embodiment of the present application. Figure 7 It is the fifth structural schematic diagram of the base die provided by the embodiment of the present application.

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0042] Refer to Figure 3, the basic chip 100 is applied to a storage system. Among them, the basic chip 100 is configured to receive the first data data1 during the write phase and perform error correction code (ECC, Error Correction Code) encoding processing to generate encoded data, transmit the second data data2 to the storage chip during the write phase, and the second data data2 includes the first data data1 and the encoded data. During the read phase, receive the second data from the storage chip and perform error detection and correction processing, and transmit the third data data3 during the read phase. The third data data3 is the first data data1 after error detection and correction.

[0043] In the embodiments of the present application, the basic chip 100 participates in error correction code encoding processing and error detection and correction processing during data transmission.

[0044] In some embodiments, the basic chip 100 can be connected between the first port A and the second port B. Among them, the first port A is connected to the data transmission port of the controller of the storage system, and the second port B is connected to the data transmission port of the storage chip of the storage system. It can be understood that the first port A and the second port B are general terms. The first port A includes multiple data transmission ports, and the second port B includes multiple data transmission ports. Among them, the number of data transmission ports is related to the number of data to be transmitted by the basic chip 100. For example, the number of data transmission ports can be the same as the number of data to be transmitted by the basic chip 100, and one data can be transmitted via one data transmission port.

[0045] Both the error correction code encoding processing and the error detection and correction processing are used to implement ECC error detection and correction, so as to discover and locate the errors that occur during the transmission of the first data and correct the errors. In some embodiments, the ECC error detection and correction can adopt the error correction mechanism of Reed Solomon Code (RS), and correspondingly, the error correction code encoding processing can adopt the RS encoding algorithm to generate encoded data, and the decoding processing in the error detection and correction processing can adopt the RS decoding algorithm. In other embodiments, the ECC error detection and correction can adopt the error correction mechanism of Hamming Code, and correspondingly, the error correction code encoding processing can adopt the Hamming code encoding algorithm to generate encoded data, and the decoding processing in the error detection and correction processing can adopt the Hamming code decoding algorithm.

[0046] In some embodiments, the first data data1 can be 256-bit (bit) data. Correspondingly, the encoded data can be 16-bit data. It can be understood that in other embodiments, due to the different specific algorithms adopted in the error correction code encoding processing, the number of bits of the encoded data can also be correspondingly different. In addition, the number of bits of the first data data1 can also be other quantities, such as 128, 512, etc.

[0047] In addition, in some embodiments, the basic chip 100 may also be configured to generate an error detection flag signal during error detection and correction processing, and record the error condition of the first data data1 during transmission based on the error detection flag signal. Specifically, if an error occurs in the first data data1 during transmission, an error detection flag signal is generated; if no error occurs in the first data data1 during transmission, no error detection flag signal is generated. In addition, in some embodiments, the error detection flag signal may be defined as: if an error occurs in the first data data1 during transmission, the error detection flag signal is 1; if no error occurs in the first data data1 during transmission, the error detection flag signal is 0. In other embodiments, the error detection flag signal may also be defined as: if an error occurs in the first data data1 during transmission, the error detection flag signal is 0; if no error occurs in the first data data1 during transmission, the error detection flag signal is 1.

[0048] As Figure 4 shown, in some embodiments, the basic chip 100 may further include: a storage buffer module 101, which is configured to store the error condition of the first data data1 during transmission; a command module 102, which receives a polling instruction PS and generates a command signal CMD and a clock signal CLK; the storage buffer module is further configured to output a characterization signal flag based on the command signal CMD and the clock signal CLK, and the characterization signal flag characterizes the error condition of the first data data1 during transmission.

[0049] It can be understood that in the case where the polling instruction PS is not received, the storage buffer module 101 only stores the error condition of the first data data1 during transmission; after the command module 102 receives the polling instruction PS, it controls the storage buffer module 102 to output a characterization signal flag characterizing the error condition of the first data data1 during transmission. Based on this characterization signal flag, the error condition of the first data data1 can be obtained.

[0050] In some embodiments, the characterization signal flag may be a binary string. For example, if it is detected that an error occurs in the first data data1 during transmission, 1 is recorded; if it is not detected that an error occurs in the first data data1 during transmission, 0 is recorded. Thus, after a period of time, the characterization signal flag is a binary string composed of 0 and 1. In other embodiments, the characterization signal flag may also be a decimal value. For example, the storage buffer module 101 may be a counter, and if it is detected that an error occurs in the first data data1 during transmission, it is incremented by 1. Thus, after a period of time, the characterization signal flag is a decimal value related to the number of errors.

[0051] In some embodiments, the storage cache module 101 may be a first-in, first-out (FIFO) register. Using a first-in, first-out register as the storage cache module 101 can cache continuous data streams to prevent data loss during storage operations. In addition, error conditions of the first data data1 during transmission are aggregated for stacking and storage, which can avoid frequent bus operations and is beneficial to improving data transmission speed.

[0052] In addition, in some embodiments, the clock signal CLK may be independently generated by the command module 102; in other embodiments, the clock signal CLK may also be externally provided, such as being generated by the controller that generates the polling instruction PS.

[0053] Figure 5 This is the third structural schematic diagram of the base chip provided by the embodiments of the present application. Refer to Figure 5 , in some embodiments, the base chip 100 may include: an encoding module 110, which is configured to receive the first data data1 and perform error correction code encoding processing during the writing stage to generate encoded data; an error detection and correction module 120, which is configured to receive the second data data2 and perform error detection and correction processing during the reading stage.

[0054] Since the encoding module 110 and the error detection and correction module 120 are separate modules respectively, it is beneficial to further improve the independence between encoding operations and decoding operations and avoid data crosstalk problems.

[0055] Among them, the encoding module 110 may perform Hamming code encoding operations or RS code encoding operations. Correspondingly, the error detection and correction module 120 may perform Hamming code decoding operations or RS code decoding operations. In some embodiments, the encoding module 110 may receive the first data data1 from the controller and transmit the second data data2 to the storage chip; the error detection and correction module 120 may receive the second data data2 from the storage chip and transmit the first data data1 after error detection and correction processing to the controller.

[0056] Figure 6 This is the fourth structural schematic diagram of the base chip provided by the embodiments of the present application. Refer to Figure 6, in some embodiments, in addition to the encoding module 110 and the error detection and correction module 120, the basic chip 100 may further include: a first serial-to-parallel conversion (DES, DESerializer) module 130, which is configured to receive the first data data1 and perform a first serial-to-parallel conversion process on the first data data1 during the write phase, and transmit the first data data1 after the first serial-to-parallel conversion process to the encoding module 110; a first parallel-to-serial conversion (SER, SERlializer) module 140, which is configured to receive the third data data3 and perform a first parallel-to-serial conversion process on the third data data3 during the read phase, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller.

[0057] The settings of the first serial-to-parallel conversion module 130 and the second parallel-to-serial conversion module 140 can reduce the number of transmission channels between the basic chip 100 and the controller, and increase the number of bits transmitted by each transmission channel; in addition, since the number of transmission channels is reduced, the number of data transmission ports required to be set on the basic chip 100 and the controller can be saved, thereby saving the chip area of the basic chip 100 and the chip area of the controller. The first data data1 is transmitted to the first serial-to-parallel conversion module 130 in a serial manner. The first serial-to-parallel conversion module 130 can also be called a deserialization unit, that is, deserializing the serial first data data1. The first parallel-to-serial conversion module 140 serializes the third data data3 and transmits the serialized third data data3. The first parallel-to-serial conversion module 140 can also be called a serializer.

[0058] For example, if the first data data1 is 256 bits, the first data data1 is transmitted to the first serial-to-parallel conversion module 130 through 32 transmission channels. After being deserialized by the first serial-to-parallel conversion module 130, the first data data1 is transmitted to the encoding module 110 in parallel through 256 transmission channels. The third data is 256 bits. After being serialized by the first parallel-to-serial conversion module 140, the third data datat3 can become 32 strings of data, and the 32 strings of data can be transmitted through 32 transmission channels accordingly.

[0059] Figure 7 This is the fifth structural schematic diagram of the basic chip provided in the embodiments of the present application. Refer to Figure 7, in some embodiments, in addition to including an encoding module 110, an error detection and correction module 120, a first serial-to-parallel conversion module 130, and a first parallel-to-serial conversion module 140, the base chip 100 may further include: a second parallel-to-serial conversion module 150, which is configured to receive the second data data2 from the encoding module 110 during the writing phase and perform a second parallel-to-serial conversion process, and transmit the second data data2 after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module 160, which is configured to receive the second data data2 from the storage chip during the reading phase and perform a second serial-to-parallel conversion process, and transmit the second data data2 after the second serial-to-parallel conversion process to the error detection and correction module 120.

[0060] The second parallel-to-serial conversion module 150 performs serial processing on the second data data2 after error correction code encoding, which is beneficial to reducing the transmission channels between the base chip 100 and the storage chip, thereby saving the number of data transmission ports required to be provided on the base chip 100 and the storage chip, and further saving the chip area of the base chip 100 and the chip area of the storage chip. For example, the second data data2 may include 256-bit first data data1 and 16-bit encoded data. After the parallel-to-serial conversion process by the second parallel-to-serial conversion module 150, the second data data2 can be transmitted to the storage chip using 128 + 8 transmission channels. Among them, each of the 128 transmission channels transmits 2 bits of the 256-bit data, and each of the 8 transmission channels transmits 2 bits of the 16-bit data.

[0061] The second serial-to-parallel conversion module 160 performs parallel processing on the second data data2 transmitted from the storage chip, that is, performs a serial-to-parallel conversion process on the second data data2, and the second data data2 after the serial-to-parallel conversion process is transmitted to the error detection and correction module 120. For example, the second serial-to-parallel conversion module 160 can convert the second data data2 of 128 strings + 8 strings into parallel 256-bit + 16-bit data.

[0062] In addition, in some embodiments, the error detection and correction module 120 may further generate an error detection flag signal during the error detection and correction process. Continue to refer to Figures 4 to 7, in some embodiments, the base chip 100 may further include: a storage buffer module 101 configured to store the error condition of the first data data1 during transmission; a command module 102 that receives a polling instruction PS and generates a command signal CMD and a clock signal CLK; the storage buffer module 101 is further configured to output a characterization signal flag based on the command signal CMD and the clock signal CLK, and the characterization signal flag characterizes the error condition of the first data data1 during transmission.

[0063] For a detailed description of the storage buffer module 101 and the command module 102, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated herein.

[0064] The base chip 100 provided in the foregoing embodiments not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. In this way, the chip area of the base chip 100 can be effectively utilized, reducing the chip area pressure on the controller and the storage chip, and saving the chip area of the controller and the storage chip.

[0065] In addition, the base chip 100 may also have the functions of data serial processing and deserialization processing, which is conducive to reducing the transmission channels between the controller and the base chip 100 and between the storage chip and the base chip 100, thereby saving the number of data transmission ports required on the controller, the base chip 100, and the storage chip, and further saving the chip area of the controller, the base chip 100, and the storage chip.

[0066] Another embodiment of the present application further provides a storage system, which includes a controller, a storage chip, and a base chip as provided in the foregoing embodiments. The storage system provided in another embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed descriptions in the foregoing embodiments, which will not be repeated hereinafter.

[0067] Figure 8 It is a schematic diagram of the first structure of the storage system provided in the embodiments of the present application.

[0068] Refer to Figure 8, the storage system includes: a base chip 200, a controller 300, and a storage chip 400; the controller 300 is configured to transmit first data data1 to the base chip 200 during the write phase; the base chip 200 is configured to receive the first data data1 during the write phase and perform error correction code encoding processing to generate encoded data, transmit second data data2 to the storage chip 400 during the write phase, the second data data2 including the first data data1 and the encoded data, receive the second data data2 from the storage chip 400 during the read phase and perform error detection and correction processing, and transmit third data data3 to the controller 300 during the read phase, the third data data3 being the first data data1 after error detection and correction processing; the storage chip 400 is configured to receive the second data data2 from the base chip 200 during the write phase and store the second data data2, and transmit the second data data2 to the base chip 200 during the read phase.

[0069] In the above storage system, the error correction code encoding processing and error detection and correction processing of data are both implemented by the base chip 200. Thus, neither the controller 300 nor the storage chip 400 needs to perform encoding processing and error detection and correction processing, which reduces the functions required for the controller 300 and the storage chip 400. Therefore, the pressure on the chip area of the controller 300 and the storage chip 400 can be alleviated, so as to better improve the performance of the controller 300 and the storage chip 400. For example, the reliability of the storage chip 400 can be improved, thereby enhancing the storage performance of the storage system.

[0070] In some embodiments, the storage system can be a DRAM storage system, such as a DDR (double data rate) 4 DRAM storage system or a DDR5 DRAM storage system. In other embodiments, the storage system can also be an SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PcRAM storage system.

[0071] The base chip 200 can provide a high-speed interface for data transmission in the storage system. In addition, the base chip 200 is also used to manage and control the storage chip 400. In some embodiments, the base chip 200 can be used to monitor and manage the temperature of the storage chip 400, and can also be used to perform Memory Build-In-Self Test (MBIST) and self-repair on the storage chip 400. In addition, the base chip 200 is also used to perform error detection and correction on the transmitted data.

[0072] Figure 9This is the second structural schematic diagram of the storage system provided by the embodiments of the present application. Refer to Figure 9 In some embodiments, the base chip 200 may include: an encoding module 210, which is configured to receive the first data data1 during the writing stage and perform error correction code encoding processing to generate encoded data; an error detection and correction module 220, which is configured to receive the second data data2 during the reading stage and perform error detection and correction processing.

[0073] Specifically, the encoding module 210 is connected between the data transmission port of the controller 300 and the data transmission port of the storage chip 400, and the error detection and correction module 220 is connected between the data transmission port of the controller 300 and the data transmission port of the storage chip 400. The storage chip 400 may include a first storage module and a second storage module. The first storage module stores the first data data1, and the second storage module stores the encoded data.

[0074] The following will take the first data data1 as 256 bits and the encoded data as 16 bits as an example to Figure 9 illustrate the working principle of the storage system shown:

[0075] During the writing stage, the controller 300 transmits 256-bit first data data1 to the encoding module 210; the encoding module 210 receives the 256-bit data and performs ECC encoding processing to generate 16-bit encoded data. The 16-bit encoded data and the first data data1 constitute the second data data2; then, the encoding module 210 transmits the second data data2 to the storage chip 400. The first storage module stores the 256-bit first data data1, and the second storage module stores the 16-bit encoded data.

[0076] During the reading stage, the storage chip 400 transmits the second data data2 to the error detection and correction module 220, and the error detection and correction module 220 performs error detection and correction. If the 256-bit first data data1 has no error, the 256-bit first data data1 is transmitted to the controller 300; if an error occurs in the 256-bit first data data1, the error bit is corrected, and the corrected 256-bit first data data1 is transmitted to the controller 300.

[0077] Figure 10 This is the third structural schematic diagram of the storage system provided by the embodiments of the present application. Refer to Figure 10, in some embodiments, in addition to the encoding module 210 and the decoding module 220, the base chip 200 may further include: a first serial-to-parallel conversion module 230, which is configured to receive the first data data1 during the writing phase and perform a first serial-to-parallel conversion process on the first data data1, and transmit the first data data1 after the first serial-to-parallel conversion process to the encoding module 210; a first parallel-to-serial conversion module 240, which is configured to receive the third data data3 during the reading phase and perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller 300.

[0078] Specifically, the first serial-to-parallel conversion module 230 is connected between the data transmission port of the controller 300 and the data transmission port of the encoding module 210, and the first parallel-to-serial conversion module 240 is connected between the data transmission port of the controller 300 and the data transmission port of the encoding module 210. In this way, the number of transmission channels between the controller 300 and the base chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the controller 300 and the base chip 200, and the number of data transmission ports required to be set on the base chip 200 and the controller 300 can be saved, which is beneficial to reducing the complexity of the electrical connection structure between the controller 300 and the base chip 200 and saving the chip areas of the controller 300 and the base chip 200. The working principle of the storage system shown below will be described by taking the first data data1 as 256 bits and the encoded data as 16 bits as an example. It should be noted that the encoding module 210 and the error detection and correction module 220 will not be described in detail below: Figure 10 In the writing phase, there may be 32 transmission channels between the controller 300 and the encoding module 210. The 256-bit first data data1 is transmitted to the first serial-to-parallel conversion module 230 through 32 transmission channels for serial-to-parallel processing. The first serial-to-parallel conversion module 230 outputs the 256-bit first data data1 for parallel transmission. This first data data1 is transmitted to the encoding module 210 for encoding and then continues to be transmitted to the storage chip 400. In the reading phase, the 256-bit data after error detection and correction output by the error detection and correction module 220 is transmitted to the first parallel-to-serial conversion module 240 for parallel-to-serial processing. The 256-bit first data data1 after the parallel-to-serial processing can be transmitted to the controller 300 through 32 transmission channels.

[0079] It can be understood that in other embodiments, the number of transmission channels between the controller 300 and the encoding module 210 may also be other appropriate numbers, such as 128, 64, or 16, etc.

[0080] It can be understood that in other embodiments, the number of transmission channels between the controller 300 and the encoding module 210 may also be other appropriate numbers, such as 128, 64, or 16, etc.

[0081] Figure 11 This is the fourth structural schematic diagram of the storage system provided by the embodiments of the present application. Refer to Figure 11 , in some embodiments, in addition to the encoding module 210, decoding module 220, first serial-parallel conversion module 230, and first parallel-serial conversion module 240, the basic chip 200 may further include: a second parallel-serial conversion module 250, which is configured to receive the second data data2 from the encoding module 210 and perform a second parallel-serial conversion process during the writing stage, and transmit the second data data2 after the second parallel-serial conversion process to the storage chip 400; a second serial-parallel conversion module 260, which is configured to receive the second data data2 from the storage chip 400 and perform a second serial-parallel conversion process during the reading stage, and transmit the second data data2 after the second serial-parallel conversion process to the error detection and correction module 220.

[0082] Specifically, the second parallel-serial conversion module 250 is connected between the data transmission port of the encoding module 210 and the data transmission port of the storage chip 400, and the second serial-parallel conversion module 260 is connected between the data transmission port of the storage chip 400 and the data transmission port of the error detection and correction module 220. In this way, the number of transmission channels between the storage chip 400 and the basic chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the storage chip 400 and the basic chip 200, facilitating reducing the number of data transmission ports required to be provided on the basic chip 200 and the storage chip 400, facilitating reducing the complexity of the electrical connection structure between the storage chip 400 and the basic chip 200, and saving the chip areas of the storage chip 400 and the basic chip 200. The working principle of the storage system shown in Figure 11 will be described below by taking the first data data1 as 256 bits and the encoded data as 16 bits as an example. It should be noted that the encoding module 210, error detection and correction module 220, first serial-parallel conversion module 230, and first parallel-serial conversion module 240 will not be elaborated in detail below:

[0083] In the writing stage, the controller 300 transmits 256-bit first data data1 to the first serial-parallel conversion module 230 via 32 transmission channels. The first data data1 is subjected to ECC encoding processing by the encoding module 210 to obtain 16-bit encoded data. Then, the 256-bit first data data1 and the 16-bit encoded data are transmitted to the second parallel-serial conversion module 250. The second parallel-serial conversion module 250 serially processes the 256-bit first data data1 and transmits it to the storage chip 400 via 128 transmission channels. The second parallel-serial conversion module 250 serially processes the 16-bit encoded data and transmits it to the storage chip 400 via 8 transmission channels.

[0084] In the reading stage, the 256-bit first data data1 is transmitted to the second serial-parallel conversion module 260 via 128 transmission channels for deserialization, and the 16-bit encoded data is transmitted to the second serial-parallel conversion module 260 via 8 transmission channels for deserialization. Then, the 256-bit first data data1 and the 16 encoded data are transmitted to the error detection and correction module 220. The 256-bit first data data1 output by the error detection and correction module 220 is sequentially transmitted to the first parallel-serial conversion module 240 and the controller 300.

[0085] It can be understood that the number of data transmission channels between the controller 300 and the base chip 200 is M, and the number of data transmission channels between the base chip 200 and the storage chip 400 is N. Among them, both M and N are positive integers greater than 1, and N is greater than M. The above is described by taking M as 32 and N as 128 + 8 as an example. In other embodiments, M and N can be any positive integers. For example, N can be 32 + 2, where 32 data transmission channels are used to transmit the first data, and 2 data transmission channels are used to transmit the encoded data. It can be understood that since the N data transmission channels need to transmit both the first data and the encoded data, N is greater than M.

[0086] In some embodiments, such as Figures 10 to 12 , Figure 12 FIG. 5 is a schematic structural diagram of a fifth storage system provided by an embodiment of the present application. The base chip 200 can also be configured to generate an error detection flag signal during error detection and correction processing, and record the error situation of the first data data1 during transmission based on the error detection flag signal. The storage system may further include: a register 500, and the register 500 is configured to store the error situation of the first data data1 during transmission.

[0087] Specifically, the base chip 200 may include: a storage buffer module 201 configured to store the error condition of the first data data1 during transmission; a command module 202 that receives a polling instruction PS and generates a command signal CMD and a clock signal CLK; the storage buffer module 201 is further configured to output a characterization signal flag to the register 500 based on the command signal CMD and the clock signal CLK, and the characterization signal flag characterizes the error condition of the first data data1 during transmission.

[0088] In some embodiments, the controller 300 may also be configured to issue a polling instruction PS to the command module 202, that is, the controller 300 periodically issues an inquiry to control the storage buffer module 201 to output the characterization signal flag to the register 500. It can be understood that in other embodiments, the polling instruction may also be provided by an external circuit.

[0089] For the above description of the base chip 200, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated here.

[0090] In the storage system provided by the above embodiments, the base chip 200 can implement an error detection and correction function. Correspondingly, neither the controller 300 nor the storage chip 400 needs to have an error detection and correction function. Therefore, it is beneficial to save the space area of the controller 300 and the storage chip 400, improve the storage performance of the storage chip 400, and thus improve the storage performance of the storage system.

[0091] Correspondingly, the embodiment of the present application also provides a semiconductor structure, which may include the storage system provided by the above embodiments. The semiconductor structure provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated below.

[0092] Figure 13 It is a schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiment of the present application.

[0093] Reference Figure 13 , the semiconductor structure includes: a carrier substrate 600; the storage system provided by the foregoing embodiments, and both the controller 300 and the base chip 200 are located on the surface of the carrier substrate 600, and the storage chip 400 is located on the surface of the base chip 200 away from the carrier substrate 600.

[0094] Among them, the semiconductor structure may include a plurality of storage chips 400 stacked in sequence. The semiconductor structure may be a memory such as a DARM device or an SRAM device.

[0095] In some embodiments, the carrier substrate 600 may be a Printed Circuit Board (PCB). For a detailed description of the storage system, reference may be made to the foregoing embodiments, which will not be elaborated herein.

[0096] The semiconductor structure may be a 2.5D (dimensions) device, that is, the semiconductor structure is a stacked structure, which is beneficial to saving the size in the horizontal direction, and the basic chip 200 in the semiconductor structure is used to implement the ECC error detection and correction function, which is beneficial to improving the performance of the semiconductor structure.

[0097] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A basic chip is applied to a storage system, Characterized in that, Comprising: The basic chip is configured to receive first data and perform error correction code encoding processing to generate encoded data during a write phase, transmit second data to a storage chip during the write phase, the second data including the first data and the encoded data, receive the second data from the storage chip and perform error detection and correction processing during a read phase, and transmit third data during the read phase, the third data being the first data after the error detection and correction processing; An encoding module configured to receive the first data and perform the error correction code encoding processing to generate the encoded data during the write phase; An error detection and correction module configured to receive the second data and perform the error detection and correction processing during the read phase; A first serial-to-parallel conversion module configured to receive the first data and perform a first serial-to-parallel conversion process on the first data during the write phase, and transmit the first data after the first serial-to-parallel conversion process to the encoding module; A first parallel-to-serial conversion module configured to receive the third data and perform a first parallel-to-serial conversion process on the third data during the read phase, and transmit the third data after the first parallel-to-serial conversion process to a controller.

2. The basic chip according to claim 1, Characterized in that, The basic chip further comprises: A second parallel-to-serial conversion module configured to receive the second data from the encoding module and perform a second parallel-to-serial conversion process during the write phase, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; A second serial-to-parallel conversion module configured to receive the second data from the storage chip and perform a second serial-to-parallel conversion process during the read phase, and transmit the second data after the second serial-to-parallel conversion process to the error detection and correction module.

3. The basic chip according to claim 1, Characterized in that, The basic chip is further configured to generate an error detection flag signal during the error detection and correction processing, and record the error condition of the first data during transmission based on the error detection flag signal.

4. The basic chip according to claim 3, Characterized in that, The basic chip further comprises: A storage buffer module configured to store the error condition of the first data during transmission; A command module that receives a polling instruction and generates a command signal and a clock signal; The storage buffer module is further configured to output a characterization signal based on the command signal and the clock signal, the characterization signal characterizing the error condition of the first data during transmission.

5. The basic chip according to claim 4, Characterized in that, The storage buffer module includes a first-in first-out register.

6. A storage system, Characterized in that, Comprising a controller, a basic chip and a storage chip, further comprising: The controller is configured to transmit first data to the base chip during a write phase; The base chip is configured to receive the first data during the write phase and perform error correction code encoding processing to generate encoded data, transmit second data to the storage chip during the write phase, the second data including the first data and the encoded data, receive the second data from the storage chip during a read phase and perform error detection and correction processing, and transmit third data to the controller during the read phase, the third data being the first data after the error detection and correction processing; The storage chip is configured to receive the second data from the base chip during the write phase and store the second data, and transmit the second data to the base chip during the read phase; The base chip includes: An encoding module configured to receive the first data during the write phase and perform the error correction code encoding processing to generate the encoded data; An error detection and correction module configured to receive the second data during the read phase and perform the error detection and correction processing; A first serial-to-parallel conversion module configured to receive the first data during the write phase and perform a first serial-to-parallel conversion process on the first data, and transmit the first data after the first serial-to-parallel conversion process to the encoding module; A first parallel-to-serial conversion module configured to receive the third data during the read phase and perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

7. The storage system according to claim 6, wherein, The base chip further includes: A second parallel-to-serial conversion module configured to receive the second data from the encoding module during the write phase and perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; A second serial-to-parallel conversion module configured to receive the second data from the storage chip during the read phase and perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the error detection and correction module.

8. The storage system according to claim 7, wherein, The number of data transmission channels between the controller and the base chip is M, and the number of data transmission channels between the base chip and the storage chip is N; wherein, both M and N are positive integers greater than 1, and N is greater than M.

9. The storage system according to claim 6, wherein, The base chip is further configured to generate an error detection flag signal during the error detection and correction processing, and record the error condition of the first data during transmission based on the error detection flag signal; The storage system further includes: A register configured to store the error condition of the first data during transmission.

10. The storage system according to claim 9, wherein: the basic chip includes: a storage cache module configured to store the error condition of the first data during transmission; a command module that receives a polling instruction and generates a command signal and a clock signal; the storage cache module is further configured to output a characterization signal to the register based on the command signal and the clock signal, the characterization signal characterizing the error condition of the first data during transmission.

11. The storage system according to claim 10, wherein: the controller is further configured to issue the polling instruction to the command module.

12. A semiconductor structure, wherein: it includes: a carrier substrate; the storage system according to any one of claims 6-11, and the controller and the basic chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the basic chip away from the carrier substrate.

Images