A Threshold Voltage-Controlled Multi-Heterojunction GaN HEMT Fabrication Method

Abstract

The application discloses a kind of based on threshold voltage regulation Multi-heterojunction GaN HEMT preparation method, comprising: growing GaN buffer layer and multiple periodic arrangement, including GaN channel layer and InAlN barrier layer channel barrier structure on SiC substrate;Surface preparation source drain and realize device active area isolation on side face;Surface deposition passivation layer and etching on the aperture of gate position;Etching channel barrier structure downward at the aperture of gate position, until etching period number makes threshold voltage regulation to pre-set requirement obtains recess;Gate preparation is completed in recess, and obtains threshold voltage regulation after Multi-heterojunction GaN HEMT.The application is designed by the thickness of GaN channel layer and InAlN barrier layer or the doping concentration design of additional InAlN barrier layer, and is designed in combination with etching formula of each material in channel barrier structure, so that etching depth and threshold voltage present linear variation, can realize threshold voltage accurate regulation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, specifically relating to a method for fabricating GaN HEMTs based on threshold voltage regulation. Background Technology

[0002] With the rapid development of wireless communication technology, traditional Si-based and GaAs-based semiconductor devices are increasingly unable to meet the market demands for high-frequency and high-power applications. GaN-based HEMTs (High Electron Mobility Transistors) have significant advantages in high-frequency and high-power applications due to their wide bandgap, high voltage resistance, and high mobility. Currently, GaN HEMTs have been successfully applied in fields such as 5G base stations, satellite communications, and electric vehicles, and are impacting all aspects of people's lives.

[0003] To further explore the application potential of GaN HEMTs in power electronics and radio frequency power, dual / multi-heterojunction GaN HEMT devices have attracted widespread attention in recent years. Multi-heterojunction GaN HEMT devices, due to their ability to form multiple two-dimensional electron gas (2DEG) channels, possess more charge carriers compared to single-channel devices, thus improving the device's saturation current density and output power density. Furthermore, multi-heterojunction GaN HEMT devices offer numerous advantages, including moduloability of the rs-Id (source resistance-drain current) relationship and widening of the gate voltage swing to improve linearity.

[0004] To further increase the carrier concentration of the device, InAlN (indium aluminum nitride) strongly polarized material can be used as the barrier layer; and multi-heterojunction GaN HEMT can distribute carriers to multiple channels, reduce the carrier concentration of a single channel, thereby increasing the overall saturated electron mobility of the device and improving the frequency characteristics of the device.

[0005] However, multi-heterojunction GaN HEMT devices can cause severe negative threshold voltage drift. Existing gate etching techniques have difficulty controlling the etching depth. Furthermore, due to the coupling effect between channels, conventional multi-heterojunction devices have difficulty achieving precise control of the etching depth and threshold voltage to change linearly in tandem. Summary of the Invention

[0006] To address the problem of inaccurate threshold voltage control in existing multi-heterojunction GaN HEMT devices, this invention provides a method for fabricating multi-heterojunction GaN HEMTs based on threshold voltage control. The technical problem solved by this invention is achieved through the following technical solution:

[0007] A method for fabricating GaN HEMTs based on threshold voltage regulation includes:

[0008] A GaN buffer layer and multiple periodically arranged channel barrier structures are sequentially grown on a SiC substrate to obtain a Ga-plane GaN HEMT device structure. Each channel barrier structure consists of a GaN channel layer and an InAlN barrier layer above it. The multiple channel barrier structures adopt a first structural parameter or a second structural parameter. In the first structural parameter, the thicknesses of the GaN channel layer and the InAlN barrier layer are the first channel thickness and the first barrier thickness, respectively. In the second structural parameter, the thicknesses of the GaN channel layer and the InAlN barrier layer are the second channel thickness and the second barrier thickness, respectively. Each InAlN barrier layer is obtained by n-type doping with different concentrations.

[0009] Source and drain electrodes are fabricated on the surface of the device structure, and active region isolation is achieved on the side of the device structure;

[0010] A passivation layer is deposited on the surface of the device structure between the source and drain, and the corresponding passivation layer is etched through openings at the gate locations.

[0011] Based on a predetermined linear relationship between the number of etching cycles and the threshold voltage of the channel barrier structure, the channel barrier structure is etched downwards at the opening at the gate location until the threshold voltage is adjusted to the preset requirement by the number of etching cycles, resulting in a vertical groove. Specifically, for the etching of the channel barrier structure in each cycle, the InAlN barrier layer is etched using a first etching formula that is only effective for etching itself; the GaN channel layer is etched using a second etching formula that is only effective for etching itself. Each etching formula contains multiple parameters related to the etching process. The linear relationship is experimentally determined based on any one of the structural parameters used for multiple channel barrier structures and the two etching formulas used for etching the channel barrier structure.

[0012] The gate is fabricated within the groove to obtain a multi-heterojunction GaN HEMT with threshold voltage control.

[0013] In one embodiment of the present invention, the SiC substrate has a thickness of 0.375 mm; the GaN buffer layer has a thickness of 1 μm; and the In content in each InAlN barrier layer is 17%.

[0014] In one embodiment of the present invention, the thickness of the first channel and the thickness of the first barrier are both 10 nm in the first structural parameters.

[0015] In one embodiment of the present invention, in the second structural parameters, the second channel thickness is 8 nm; the first barrier thickness is 12 nm; and the doping concentration of the remaining InAlN barrier layers, except for the topmost InAlN barrier layer, is 1 × 10⁻⁶. 16 cm -3 .

[0016] In one embodiment of the present invention, the fabrication of the source and drain on the surface of the device structure includes:

[0017] The source and drain electrodes are fabricated by performing corresponding metal evaporation at the source and drain positions on the surface of the device structure using step-by-step lithography and electron beam evaporation techniques.

[0018] In one embodiment of the present invention, the method of implementing active region isolation on the side of the device structure includes:

[0019] Argon ions are injected into the region on the side of the device structure above the GaN buffer layer after the source and drain electrodes have been fabricated to obtain the active isolation region of the device.

[0020] In one embodiment of the present invention, the deposition of a passivation layer on the surface of the device structure between the source and drain, and the etching of the corresponding passivation layer for the gate location via, includes:

[0021] A SiN passivation layer is deposited on the surface of the device structure between the source and drain using PECVD technology;

[0022] Electron beam lithography is used to align and mark the gate positions, and F-based dry etching technology is used to perform hole etching at the gate positions to remove the corresponding SiN passivation layer.

[0023] In one embodiment of the present invention, the etching process of the channel barrier structure in each cycle includes:

[0024] For this cycle, the InAlN barrier layer in this cycle is removed using the Oxford etching equipment and the first etching recipe, so as to achieve self-stop when etching to the GaN channel layer of this cycle; wherein, the first etching recipe includes: the etching gas is BCl3, the flow rate is 50 sccm, the pressure is 5 mTorr, the on-power is 80W, and the radio frequency power is 10W.

[0025] For this cycle, the Oxford etching equipment is used, and the second etching formula is employed to remove the GaN channel layer in this cycle, achieving self-stop when etching reaches the InAlN barrier layer of this cycle; wherein, the second etching formula includes: etching gas is SF6 / BCl3, flow rate is 50 / 20 sccm, pressure is 5 mTorr, on-power is 100W, and RF power is 10W.

[0026] In one embodiment of the present invention, the step of completing the gate fabrication within the groove includes:

[0027] The gate metal is deposited in the groove using step-by-step lithography and electron beam evaporation techniques to complete the gate fabrication.

[0028] In one embodiment of the present invention, the linear relationship includes:

[0029] For each additional etching cycle of the channel barrier structure, the threshold voltage increases by 5V.

[0030] In the threshold voltage-controlled multi-heterojunction GaN HEMT fabrication method provided in this invention, a first structural parameter and a second structural parameter are designed for the channel barrier structure. Both the first and second structural parameters define specific thicknesses for the GaN channel layer and the InAlN barrier layer. The second structural parameter also specifies different doping concentrations for each InAlN barrier layer. Furthermore, this invention employs a self-terminating etching technique. For each cycle of the channel barrier structure, different etching selectivity ratios are determined for GaN and InAlN, resulting in different etching formulations. This ensures that etching is effective only for the corresponding material without affecting other materials, thus enabling precise control of the etching depth. The embodiments of the present invention achieve a linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage by periodically arranging a "channel layer + barrier layer" of a specific thickness, or by further doping the barrier layer with a specific concentration, and by using different self-terminating etching formulations with different etching selectivity ratios for different materials. Therefore, by utilizing this linear relationship in the actual fabrication of multi-heterojunction GaN HEMTs, the threshold voltage can be adjusted to a preset requirement by controlling the number of etching cycles of the channel barrier structure, thereby achieving the goal of precise control of the threshold voltage of multi-heterojunction GaN HEMT devices and thus enabling digital alloying threshold control. Attached Figure Description

[0031] Figure 1 This is a schematic flowchart of a method for fabricating GaN HEMTs based on threshold voltage regulation, provided in an embodiment of the present invention.

[0032] Figures 2(a) to 2(j) This is a schematic diagram of the process for fabricating GaNHEMT based on threshold voltage regulation according to an embodiment of the present invention.

[0033] Figure 3 This is a schematic diagram of the device band structure when the second design scheme is used in an embodiment of the present invention;

[0034] Figures 4(a) to 4(e) This is a schematic diagram showing the change of threshold voltage under different number of etching cycles for different channel barrier structures when the second design scheme is adopted in an embodiment of the present invention.

[0035] Figures 5(a) to 5(j) This is a schematic diagram of the process for fabricating GaN HEMTs based on threshold voltage regulation, corresponding to Example 1.

[0036] Figures 6(a) to 6(j)This is a schematic diagram of the process for fabricating GaN HEMTs based on threshold voltage regulation, corresponding to Example 2. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] like Figure 1 As shown in the embodiment of the present invention, a method for fabricating GaN HEMTs based on threshold voltage control may include the following steps:

[0039] S1, GaN buffer layer and multiple periodically arranged channel barrier structures are sequentially grown on SiC substrate to obtain GaN HEMT device structure.

[0040] Each channel barrier structure consists of a GaN channel layer and an InAlN barrier layer above it; multiple channel barrier structures adopt a first structural parameter or a second structural parameter; in the first structural parameter, the thicknesses of the GaN channel layer and the InAlN barrier layer are the first channel thickness and the first barrier thickness, respectively; in the second structural parameter, the thicknesses of the GaN channel layer and the InAlN barrier layer are the second channel thickness and the second barrier thickness, respectively, and each InAlN barrier layer is obtained by n-type doping with different concentrations.

[0041] Specifically, the GaN buffer layer and multiple periodically arranged channel barrier structures are sequentially grown on the SiC substrate using MOCVD (Metal-organic Chemical Vapor Deposition) technology.

[0042] In one optional embodiment, the SiC substrate has a thickness of 0.375 mm; the GaN buffer layer has a thickness of 1 μm; and the In (i.e., indium) content in each InAlN barrier layer is 17%. The reason for determining the In AlN barrier layer to have an In content of 17% is that InAlN with a 17% In content exhibits no lattice mismatch with GaN, resulting in higher quality epitaxial material, lower dislocation and defect density, and thus improved device quality.

[0043] In this embodiment of the invention, a channel barrier structure includes a GaN channel layer and an InAlN barrier layer from bottom to top. Multiple channel barrier structures are arranged periodically. For the sake of simplicity, the multiple channel barrier structures from top to bottom are defined as corresponding to period 1, period 2, etc.

[0044] This invention, through pre-designing the structural parameters of the channel barrier structure, determines two types of structural parameters: a first structural parameter and a second structural parameter. Both the first and second structural parameters specifically design the thicknesses of the GaN channel layer and the InAlN barrier layer. Furthermore, the second structural parameter also designs the n-type doping concentration of each InAlN barrier layer. Specifically:

[0045] In one optional implementation, the thickness of the first channel and the thickness of the first barrier are both 10 nm in the first structural parameters.

[0046] In one optional embodiment, the second structural parameters include a second channel thickness of 8 nm, a first barrier thickness of 12 nm, and a doping concentration of 1 × 10⁻⁶ for all InAlN barrier layers except the topmost InAlN barrier layer. 16 cm -3 In other words, in the second structural parameter, the InAlN barrier layer in the channel barrier structure of period 1 is not doped with donor elements. From period 2 downwards, the doping concentration of donor elements in the InAlN barrier layer of all channel barrier structures is 1×10⁻⁶. 16 cm -3 The donor element for doping can be phosphorus, etc.

[0047] The GaN HEMT device structure obtained by S1 can be understood by referring to Figure 2(a). For simplicity, a two-cycle channel barrier structure is used as an example, and the structural parameters of the channel barrier structure can be either the first structural parameter or the second structural parameter.

[0048] S2, source and drain electrodes are fabricated on the surface of the device structure, and active region isolation is achieved on the side of the device structure;

[0049] Fabricating the source and drain on the surface of the device structure can include:

[0050] The source and drain electrodes are fabricated by performing corresponding metal evaporation at the source and drain positions on the surface of the device structure using step-by-step lithography and electron beam evaporation techniques.

[0051] Specifically, a photoresist layer is first deposited on the surface of the device structure; step-by-step photolithography is used to align the source and drain positions and etch the corresponding photoresist layers, as shown in Figure 2(b).

[0052] Then, electron beam evaporation deposition of ohmic metals for the source and drain electrodes was performed using electron beam evaporation technology; the ohmic metals for the source and drain electrodes could be titanium (Ti), aluminum (A), nickel (Ni), gold (Au), etc.; subsequently, high-temperature rapid annealing was performed at 880℃ for 50 seconds under a nitrogen atmosphere to form ohmic contacts between the source and drain electrodes, thus completing the fabrication of the source and drain electrodes, as shown in Figure 2(c); where the source and drain electrodes are represented by S and D, respectively.

[0053] Implementing active region isolation on the side of the device structure can include:

[0054] Argon ions are injected into the region on the side of the device structure above the GaN buffer layer after the source and drain electrodes have been fabricated to obtain the active isolation region of the device.

[0055] Specifically, for the device structure in Figure 2(c), argon ions were injected into the region on its side above the GaN buffer layer to form an active isolation region on both sides of the source and drain, as shown in Figure 2(d).

[0056] S3, deposit a passivation layer on the surface of the device structure between the source and drain, and etch the corresponding passivation layer for the gate location through the opening;

[0057] S3 may include:

[0058] S31, using PECVD process to deposit a SiN passivation layer on the surface of the device structure between the source and drain;

[0059] PECVD is a plasma-enhanced chemical vapor deposition method; the thickness of the SiN passivation layer can be 120 nm. The results are shown in Figure 2(e).

[0060] S32 uses electron beam lithography to align and mark the gate position, and uses F-based dry etching technology to perform hole etching at the gate position to remove the corresponding SiN passivation layer.

[0061] The process parameters used in the F-based dry etching technique are as follows: carbon tetrafluoride (CF4) flow rate of 25 sccm; oxygen (O2) flow rate of 5 sccm; pressure of 5 mT; upper electrode power of 80 W; and lower electrode power of 10 W. The result of this step is shown in Figure 2(f), which shows that an opening at the gate position was formed on the SiN passivation layer.

[0062] S4. Based on the predetermined linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage, the channel barrier structure is etched downward at the opening at the gate position until the number of etching cycles adjusts the threshold voltage to the preset requirement, thus obtaining a vertical groove.

[0063] Specifically, for the etching of the channel barrier structure in each cycle, the InAlN barrier layer is etched using a first etching formula that is only effective for etching itself; the GaN channel layer is etched using a second etching formula that is only effective for etching itself; each etching formula contains multiple parameters related to the etching process; the linear relationship is determined experimentally based on any one of the structural parameters used for multiple channel barrier structures and the two etching formulas used for etching the channel barrier structure.

[0064] The embodiments of the present invention can determine the linear relationship between the number of etching cycles and the threshold voltage of the channel barrier structure through prior experiments. For example, in one optional embodiment, the linear relationship includes:

[0065] For each additional etching cycle of the channel barrier structure, the threshold voltage increases by 5V.

[0066] Therefore, during the threshold voltage adjustment process, based on this linear relationship, it can be determined whether the change in threshold voltage reaches the preset requirement after each additional etching cycle of the channel barrier structure. If it does, the adjustment can be stopped. Alternatively, this embodiment of the invention can also pre-establish a mapping relationship between the number of etching cycles of the channel barrier structure and the adjusted threshold voltage value based on this linear relationship, such as a mapping table, where each etching cycle of the channel barrier structure corresponds to an adjusted threshold voltage value. Then, during the actual adjustment of the threshold voltage, the target threshold voltage value can be determined by querying this mapping relationship to determine how many etching cycles of the channel barrier structure to etch, thereby completing the etching and adjusting the threshold voltage to the target threshold voltage value, thus meeting the preset requirement. Both of these methods are reasonable. The experimental analysis of the linear relationship is described later.

[0067] In practice, the etching process of the channel barrier structure is the same for each cycle. The following explanation uses the etching process of the channel barrier structure for one cycle as an example. The process can be repeated for the remaining cycles.

[0068] In one optional implementation, the etching process of the channel barrier structure in each cycle includes:

[0069] (1) For this cycle, the Oxford etching equipment is used to remove the InAlN barrier layer in this cycle using the first etching formula, so as to achieve self-stop when etching to the GaN channel layer of this cycle; wherein, the first etching formula includes: the etching gas is boron trichloride (BCl3), the flow rate is 50 sccm, the pressure is 5 mTorr, the on-grid power is 80 W, and the RF power is 10 W; in the above process, a slow etching rate can be used, and the etching rate can be reasonably set as needed.

[0070] Since the gas composition in the first etching formulation can only etch InAlN and not GaN, it can remove the InAlN barrier layer, achieving self-stopping etching when reaching the GaN channel layer. The result of this step is shown in Figure 2(g), where the dashed rectangle represents the portion of the InAlN barrier layer that has been etched away.

[0071] (2) For this cycle, the Oxford etching equipment is used to remove the GaN channel layer in this cycle using a second etching formula to achieve self-stop when etching to the InAlN barrier layer of this cycle; wherein, the second etching formula includes: the etching gas is SF6 / BCl3 (i.e., sulfur hexafluoride / boron trichloride), the flow rate is 50 / 20 sccm, the pressure is 5 mTorr, the on-power is 100W, and the radio frequency power is 10W.

[0072] Similarly, since the gas ratio in the second etching formula can only etch GaN and not InAlN, it can remove the GaN channel layer and achieve self-stop when etching to the InAlN barrier layer.

[0073] The result of this step is shown in Figure 2(h), where the solid rectangles represent the portions of the GaN channel layer that have been etched away. It can be understood that etching the channel barrier structure ultimately forms a vertical groove, as shown by the two rectangles.

[0074] As can be seen, by combining self-terminating etching techniques with different etching selectivity ratios, the embodiments of the present invention can achieve precise etching of different material layers, and thus can precisely control the etching depth under the gate.

[0075] For the sake of simplicity, this embodiment of the invention uses the etching of a channel barrier structure for one cycle to complete threshold voltage regulation as an example. If multiple cycles need to be etched, please refer to Figures 2(g) and 2(h) for understanding. The groove depth will continue to extend downward.

[0076] S5, complete the gate fabrication in the groove to obtain a multi-heterojunction GaN HEMT with threshold voltage control.

[0077] S5 may include:

[0078] The gate is fabricated by evaporating gate metal in the groove using step-by-step lithography and electron beam evaporation technology.

[0079] Specifically, a photoresist layer is deposited on the SiN passivation layer on the surface of the device structure, and the photoresist corresponding to the opening at the gate position is removed by step-by-step photolithography, as shown in Figure 2(i).

[0080] Then, electron beam evaporation deposition of gate metal is performed in the groove using electron beam evaporation technology; wherein the gate metal can be Ni / Au, thereby completing the gate fabrication. Finally, the excess photoresist layer on the surface of the device structure is removed, and the result is shown in Figure 2(j), where the gate is represented by G.

[0081] Thus, the multi-heterojunction GaN HEMT with threshold voltage regulation was obtained, completing the entire device fabrication process.

[0082] In the threshold voltage-controlled multi-heterojunction GaN HEMT fabrication method provided in this invention, a first structural parameter and a second structural parameter are designed for the channel barrier structure. Both the first and second structural parameters define specific thicknesses for the GaN channel layer and the InAlN barrier layer. The second structural parameter also specifies different doping concentrations for each InAlN barrier layer. Furthermore, this invention employs a self-terminating etching technique. For each cycle of the channel barrier structure, different etching selectivity ratios are determined for GaN and InAlN, resulting in different etching formulations. This ensures that etching is effective only for the corresponding material without affecting other materials, thus enabling precise control of the etching depth. The embodiments of the present invention achieve a linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage by periodically arranging a "channel layer + barrier layer" of a specific thickness, or by further doping the barrier layer with a specific concentration, and by using different self-terminating etching formulations with different etching selectivity ratios for different materials. Therefore, by utilizing this linear relationship in the actual fabrication of multi-heterojunction GaN HEMTs, the threshold voltage can be adjusted to a preset requirement by controlling the number of etching cycles of the channel barrier structure, thereby achieving the goal of precise control of the threshold voltage of multi-heterojunction GaN HEMT devices and thus enabling digital alloying threshold control.

[0083] In summary, the multi-heterojunction GaN HEMT fabrication method based on threshold voltage regulation provided in this invention actually proposes two design schemes. The first scheme uses a first structural parameter for the channel barrier structure, combined with an intra-cycle etching formula. The second scheme uses a second structural parameter for the channel barrier structure, combined with an intra-cycle etching formula.

[0084] To facilitate understanding of the linear relationship between the number of etching cycles and the threshold voltage of the channel barrier structure in the embodiments of the present invention, the relevant experimental results are given below.

[0085] Please see Figure 3 , Figure 3 This is a schematic diagram of the energy band structure of the device using the second design scheme in an embodiment of the present invention. As can be seen from the diagram, by doping channels 2 to 4, the quantum well depth and barrier height formed at the conduction band bottom and Fermi level can be successfully achieved to be the same. Therefore, after etching to the same depth, the threshold voltage change of the device is the same.

[0086] Figures 4(a) to 4(e) This is a schematic diagram showing the change of threshold voltage under different number of etching cycles for different channel barrier structures when the second design scheme is adopted in an embodiment of the present invention; where the horizontal axis Vg represents the threshold voltage and the vertical axis Id,max represents the saturation current.

[0087] In Figure 4(a), the channel barrier structure has 0 etching cycles, meaning no etching was performed, and the corresponding threshold voltage is -24V. Figure 4(b) shows the channel barrier structure with 1 etching cycle, and the corresponding threshold voltage is -19V. Figure 4(c) shows the channel barrier structure with 2 etching cycles, and the corresponding threshold voltage is -14V. Figure 4(d) shows the channel barrier structure with 3 etching cycles, and the corresponding threshold voltage is -9V. Figure 4(e) shows the channel barrier structure with 4 etching cycles, and the corresponding threshold voltage is -4V. Figures 4(a) to 4(e) It can be seen that the number of etching cycles for the channel barrier structure is linearly related to the threshold voltage. For each additional etching cycle for the channel barrier structure, the threshold voltage increases by 5V.

[0088] To simplify the present invention, only the second design scheme is used as an example to give the experimental analysis results. Of course, for the first design scheme, the number of etching cycles of the channel barrier structure and the threshold voltage are also linearly related, and the experimental results and data graphs will not be given here.

[0089] The following describes the method for fabricating GaN HEMTs based on threshold voltage regulation provided by the present invention, using specific embodiments for each of the two design schemes described above.

[0090] (i) Example 1:

[0091] Corresponding to the first design scheme, the method for fabricating GaNHEMT based on threshold voltage control provided in this embodiment of the invention may include the following steps:

[0092] S101, fabrication of a GaN HEMT device structure with a Ga surface; from bottom to top, it includes: a 0.375 mm thick SiC substrate, a 1 μm thick GaN buffer layer, and multiple periodically arranged channel barrier structures. The channel barrier structure, from bottom to top, includes a 10 nm thick GaN channel layer and a 10 nm thick InAlN barrier layer, with the In component of the InAlN barrier layer being 17%. See Figure 5(a) for the results, which shows an example of a two-period channel barrier structure. Here, 0.375 mm SiC represents a 0.375 mm thick SiC substrate; 1 μm GaN represents a 1 μm thick GaN buffer layer; 10 nm GaN represents a 10 nm thick GaN channel layer; and 10 nm InAlN represents a 10 nm thick InAlN barrier layer. 0.17GaN represents an InAlN barrier layer with a thickness of 10 nm.

[0093] S102, source and drain electrodes are fabricated on the surface of the device structure, and active region isolation is achieved on the side of the device structure;

[0094] Please see details. Figures 5(b) to 5(d) This should be understood in conjunction with the relevant content in S2 above.

[0095] S103, deposit a passivation layer on the surface of the device structure between the source and drain, and etch the corresponding passivation layer for the gate location through the opening;

[0096] Please see details. Figures 5(e) to 5(f) This should be understood in conjunction with the relevant content in S3 above.

[0097] S104, based on the predetermined linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage, the channel barrier structure is etched downward at the opening at the gate position until the number of etching cycles adjusts the threshold voltage to the preset requirement, thus obtaining a longitudinal groove.

[0098] Taking the etching of a channel barrier structure for one cycle as an example, the results are shown in Figures 5(g) and 5(h) and can be understood in conjunction with the relevant content in S4 above.

[0099] S105, gate fabrication is completed in the groove to obtain a multi-heterojunction GaN HEMT with threshold voltage control.

[0100] Please refer to Figures 5(i) and 5(j) for the results and understand them in conjunction with the relevant content in S5 above.

[0101] As can be seen, this embodiment employs self-terminating etching technology with different etching selectivity ratios, which can precisely control the etching depth under the gate. Combined with GaN channel layer and InAlN barrier layer of specific thickness, the cyclic etching of the channel barrier structure of "barrier layer + channel layer" can achieve a linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage. That is, the threshold voltage changes by a constant value for each "barrier layer + channel layer" etching cycle, thus enabling digital alloying threshold control.

[0102] (ii) Example 2:

[0103] Corresponding to the second design scheme, the method for fabricating GaNHEMT based on threshold voltage control provided in this embodiment of the invention may include the following steps:

[0104] S201, fabricating a GaN HEMT device structure with a Ga surface; from bottom to top, it includes: a 0.375 mm thick SiC substrate, a 1 μm thick GaN buffer layer, and multiple periodically arranged channel barrier structures. The channel barrier structures, from bottom to top, include an 8 nm thick GaN channel layer and a 12 nm thick InAlN barrier layer, with the In content of the InAlN barrier layer being 17%. Furthermore, except for the InAlN barrier layer corresponding to period 1, the donor element doping concentration of the InAlN barrier layers corresponding to the other periods is 1 × 10⁻⁶. 16 cm -3 The results are shown in Figure 6(a), which illustrates a two-cycle channel barrier structure. 0.375mmSiC represents a 0.375mm thick SiC substrate; 1μm GaN represents a 1μm thick GaN buffer layer; 8nmGaN represents an 8nm thick GaN channel layer; 12nmIn 0.17 GaN represents a 12 nm thick InAlN barrier layer. The donor element doping concentration in the InAlN barrier layer of period 2 is 1 × 10⁻⁶. 16 cm -3 .

[0105] S202, source and drain electrodes are fabricated on the surface of the device structure, and active region isolation is achieved on the side of the device structure;

[0106] Please see details. Figures 6(b) to 6(d) This should be understood in conjunction with the relevant content in S2 above.

[0107] S203, deposit a passivation layer on the surface of the device structure between the source and drain, and etch the corresponding passivation layer by opening holes for the gate position;

[0108] Please see details. Figures 6(e) to 6(f) This should be understood in conjunction with the relevant content in S3 above.

[0109] S204, based on the predetermined linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage, the channel barrier structure is etched downward at the opening at the gate position until the number of etching cycles adjusts the threshold voltage to the preset requirement, thus obtaining a vertical groove.

[0110] Taking the etching of a channel barrier structure for one cycle as an example, the results are shown in Figures 6(g) and 6(h) and can be understood in conjunction with the relevant content in S4 above.

[0111] S205, the gate is fabricated in the groove to obtain a multi-heterojunction GaN HEMT with threshold voltage regulation.

[0112] Please refer to Figures 6(i) and 6(j) for the results and understand them in conjunction with the relevant content in S5 above.

[0113] As can be seen, this embodiment employs a self-terminating etching technique with different etching selectivity ratios, which can precisely control the etching depth under the gate. Combined with a GaN channel layer and an InAlN barrier layer of specific thickness and an InAlN barrier layer with a specific doping concentration, the periodic etching of the "barrier layer + channel layer" channel barrier structure can make the quantum well depth of different channels the same. This enables a linear relationship between the number of etching cycles of the channel barrier structure and the threshold voltage. In other words, the threshold voltage changes by a constant value for each "barrier layer + channel layer" etching cycle, thus enabling digital alloying threshold control.

[0114] It should be noted that in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0115] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0116] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating GaN HEMTs based on threshold voltage regulation, characterized in that, include: A GaN buffer layer and multiple periodically arranged channel barrier structures are sequentially grown on a SiC substrate to obtain a Ga-plane GaNHEMT device structure. Each channel barrier structure consists of a GaN channel layer and an InAlN barrier layer above it. The multiple channel barrier structures adopt a first structural parameter or a second structural parameter. In the first structural parameter, the thicknesses of the GaN channel layer and the InAlN barrier layer are the first channel thickness and the first barrier thickness, respectively. In the second structural parameter, the thicknesses of the GaN channel layer and the InAlN barrier layer are the second channel thickness and the second barrier thickness, respectively. Each InAlN barrier layer is obtained by n-type doping with different concentrations. Source and drain electrodes are fabricated on the surface of the device structure, and active region isolation is achieved on the side of the device structure; A passivation layer is deposited on the surface of the device structure between the source and drain, and the corresponding passivation layer is etched through openings at the gate locations. Based on a predetermined linear relationship between the number of etching cycles and the threshold voltage of the channel barrier structure, the channel barrier structure is etched downwards at the opening at the gate location until the threshold voltage is adjusted to the preset requirement by the number of etching cycles, resulting in a vertical groove. Specifically, for the etching of the channel barrier structure in each cycle, the InAlN barrier layer is etched using a first etching formula that is only effective for etching itself; the GaN channel layer is etched using a second etching formula that is only effective for etching itself. Each etching formula contains multiple parameters related to the etching process. The linear relationship is experimentally determined based on any one of the structural parameters used for multiple channel barrier structures and the two etching formulas used for etching the channel barrier structure. The gate is fabricated within the groove to obtain a multi-heterojunction GaN HEMT with threshold voltage control.

2. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 1, characterized in that, The SiC substrate has a thickness of 0.375 mm; the GaN buffer layer has a thickness of 1 μm; and the In content in each InAlN barrier layer is 17%.

3. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 2, characterized in that, In the first structural parameters, the thickness of the first channel and the thickness of the first barrier are both 10 nm.

4. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 2, characterized in that, In the second structural parameters, the second channel thickness is 8 nm; the first barrier thickness is 12 nm; and except for the topmost InAlN barrier layer, the doping concentration of the remaining InAlN barrier layers is 1 × 10⁻⁶. 16 cm -3 .

5. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 3 or 4, characterized in that, The fabrication of source and drain electrodes on the surface of the device structure includes: The source and drain electrodes are fabricated by performing corresponding metal evaporation at the source and drain positions on the surface of the device structure using step-by-step lithography and electron beam evaporation techniques.

6. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 5, characterized in that, The method of achieving active region isolation on the side of the device structure includes: Argon ions are injected into the region on the side of the device structure above the GaN buffer layer after the source and drain electrodes have been fabricated to obtain the active isolation region of the device.

7. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 6, characterized in that, The deposition of a passivation layer on the surface of the device structure between the source and drain, and the etching of the corresponding passivation layer for the gate location via, includes: A SiN passivation layer is deposited on the surface of the device structure between the source and drain using PECVD technology; Electron beam lithography is used to align and mark the gate positions, and F-based dry etching technology is used to perform hole etching at the gate positions to remove the corresponding SiN passivation layer.

8. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 1 or 7, characterized in that, The etching process of the channel barrier structure in each cycle includes: For this cycle, the InAlN barrier layer in this cycle is removed using the Oxford etching equipment and the first etching recipe, so as to achieve self-stop when etching to the GaN channel layer of this cycle; wherein, the first etching recipe includes: the etching gas is BCl3, the flow rate is 50 sccm, the pressure is 5 mTorr, the on-power is 80W, and the radio frequency power is 10W. For this cycle, the Oxford etching equipment is used, and the second etching formula is employed to remove the GaN channel layer in this cycle, achieving self-stop when etching reaches the InAlN barrier layer of this cycle; wherein, the second etching formula includes: etching gas is SF6 / BCl3, flow rate is 50 / 20 sccm, pressure is 5 mTorr, on-power is 100W, and RF power is 10W.

9. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 8, characterized in that, The process of fabricating the gate within the groove includes: The gate metal is deposited in the groove using step-by-step lithography and electron beam evaporation techniques to complete the gate fabrication.

10. The method for fabricating GaN HEMTs based on threshold voltage regulation according to claim 1 or 9, characterized in that, The linear relationship includes: For each additional etching cycle of the channel barrier structure, the threshold voltage increases by 5V.

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