Semiconductor structure and forming method thereof, and wafer bonding method

Abstract

An embodiment of the present application provides a semiconductor structure, a method for forming the same, and a wafer bonding method, wherein the method for forming the semiconductor structure includes: providing a wafer on which a semiconductor device is formed; forming a blind hole in the wafer; depositing a first metal material in the blind hole to form a through-silicon via; removing the first metal material deposited on the surface of the wafer, and flattening the surface of the wafer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and is related to, but not limited to, a semiconductor structure and a method for forming the same, and a wafer bonding method. Background Art

[0002] In the via-in-the-middle (VM) process, wafer bonding is performed after the through-silicon via (TSV) structure is completed. During the wafer bonding process, uneven wafer surfaces can lead to bonding deviations, affecting the electrical and thermal performance of the bonded wafer, and thus the reliability of the entire stacked chip. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a semiconductor structure, a method for forming the same, and a wafer bonding method.

[0004] In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, the method comprising:

[0005] providing a wafer having semiconductor devices formed thereon;

[0006] forming a blind via in the wafer;

[0007] Depositing a first metal material in the blind hole to form a through silicon via;

[0008] The first metal material deposited on the surface of the wafer is removed, and the surface of the wafer is planarized.

[0009] In a second aspect, an embodiment of the present application provides a wafer bonding method, comprising:

[0010] providing a first wafer and a second wafer;

[0011] The first wafer and the second wafer are hybrid-bonded.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor structure, including:

[0013] a wafer having semiconductor devices formed thereon;

[0014] through-silicon vias formed in the wafer;

[0015] A bonding pad electrically connected to the through silicon via.

[0016] The embodiments of the present application provide a semiconductor structure, a method for forming the same, and a wafer bonding method, wherein a blind hole is first formed in the wafer; then a first metal material is deposited in the blind hole to form a through-silicon via; then the first metal material deposited on the surface of the wafer is removed, and the surface of the wafer is flattened; finally, a bonding pad is formed on the flattened surface of the wafer; it can be seen that flattening is performed after the through-silicon via is formed, and a bonding pad is formed on the flattened surface of the wafer; compared with related technologies, flattening only needs to be performed once after the through-silicon via is formed, and the wafer surface is flat when the bonding pad is finally formed, which not only simplifies the wafer manufacturing process, but also reduces the deviation of the wafer surface during the wafer bonding process due to unevenness, thereby effectively improving the reliability of the stacked chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A A schematic diagram of a process flow for implementing a method for forming a semiconductor structure provided in an embodiment of the present application;

[0018] Figures 1B to 1C A top view of the positional relationship between a blind via and a semiconductor device provided in an embodiment of the present application;

[0019] Figures 2A to 2D A schematic diagram of the formation process of the semiconductor structure provided in an embodiment of the present application;

[0020] Figure 2E A schematic structural diagram of a wafer provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a process flow for implementing another method for forming a semiconductor structure provided in an embodiment of the present application;

[0022] Figures 4A to 4D A schematic diagram of the formation process of the semiconductor structure provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a process flow for implementing a third method for forming a semiconductor structure provided in an embodiment of the present application;

[0024] 6A to 6D A schematic diagram of the formation process of the bonding pad provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the implementation process of the wafer bonding method provided in an embodiment of the present application;

[0026] Figure 8 A schematic structural diagram of the hybrid bonding area formed by wafer bonding provided in an embodiment of the present application.

[0027] The following are the descriptions of the reference numerals:

[0028] 10—wafer; 11—substrate; 12 / 14—semiconductor device; 121—memory device; 122 / M1 / M2 / M3—metal interconnect layer; CT—contact hole; V1 / V2—through hole; 124—interlayer dielectric layer; 125—barrier layer; 13—blind hole; 15—through silicon via; 15a—isolation layer; 151—insulating layer; 152—barrier layer; 153—seed layer; 15b—conductive layer; 16—hard mask layer; 17a / 17b / 17c—through hole; 18a / 18b / 18c—bonding pad; 81—first wafer; 82—second wafer; 83—hybrid bonding area. DETAILED DESCRIPTION

[0029] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0031] In the drawings, the sizes of layers and devices as well as their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, devices and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, devices, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] High Bandwidth Memory (HBM) technology is designed to provide system ICs with greater capacity and wider bandwidth. Its development is inseparable from the use of TSV technology. Based on the differences in the front-end of line (FEOL) and back-end of line (BEOL) processes corresponding to the TSV manufacturing sequence, TSV technology is divided into via-first, via-middle, and via-last processes. Via-middle technology manufactures TSVs after transistor fabrication is complete. This technology produces smaller apertures and higher density, significantly increasing the transmission bandwidth between chip layers, and has therefore been widely used.

[0034] In the through-silicon via (TSV) manufacturing process, wafer thinning and wafer bonding are performed after the TSV structure is fabricated. During the wafer bonding process, uneven wafer surfaces can lead to bonding deviations, affecting the electrical and thermal properties of the bonded wafer, and thus the reliability of the entire stacked chip.

[0035] Based on the above-mentioned problems existing in the related art, the embodiments of the present application provide a semiconductor structure and a method for forming the same, and a wafer bonding method, first forming a blind hole in the wafer; then depositing a first metal material in the blind hole to form a through-silicon via; then removing the first metal material deposited on the surface of the wafer, and flattening the surface of the wafer; finally forming a bonding pad on the flattened surface of the wafer; it can be seen that flattening is performed after the through-silicon via is formed, and a bonding pad is formed on the flattened surface of the wafer; compared with the related art, flattening only needs to be performed once after the through-silicon via is formed, and the wafer surface is flat when the bonding pad is finally formed, which not only simplifies the wafer manufacturing process, but also reduces the deviation caused by the uneven wafer surface during the wafer bonding process, thereby effectively improving the reliability of the stacked chip.

[0036] The following is a detailed description of the specific implementation of the present application in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present application.

[0037] Figure 1A A schematic diagram of a process flow for implementing a method for forming a semiconductor structure provided in an embodiment of the present application is shown in FIG. Figure 1A As shown, the method includes:

[0038] Step S101: providing a wafer with semiconductor devices formed thereon.

[0039] In some embodiments, a wafer refers to a wafer used to manufacture semiconductor circuits, such as a silicon wafer. The silicon wafer production process involves first dissolving high-purity polycrystalline silicon and then doping it with silicon crystal seeds; then slowly pulling the polycrystalline silicon out to form cylindrical single crystal silicon; and finally, grinding, polishing, and slicing the silicon ingot to form wafers. The main wafer processing methods are sheet processing and batch processing.

[0040] In some embodiments, a semiconductor device is an electronic device with a conductivity between that of a good conductor and an insulator, utilizing the unique electrical properties of semiconductor materials to perform specific functions. Such devices can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. For example, a semiconductor device can be a crystal diode or a transistor (e.g., a bipolar transistor or a field-effect transistor). The semiconductor device can also be a multilayer metal structure composed of two or more independent metal layers.

[0041] Step S102: forming a blind hole in the wafer.

[0042] During implementation, step S102 may involve forming a blind hole of a preset depth at a preset location on the surface of the wafer. The preset depth may be determined based on factors such as the thickness of the wafer or the thickness of the wafer to be bonded. The blind hole will undergo wafer thinning in subsequent processes. Therefore, in other embodiments, step S102 may also form a through hole in the wafer.

[0043] In some embodiments, the preset position may be determined based on factors such as the number and position of semiconductor devices. For example, the preset position may be determined based on the number of semiconductor devices:

[0044] Case 1: When the number of semiconductor devices is one, the blind holes are arranged on any side of the semiconductor device, such as the front side, the back side, the left side and the right side. Figure 1B As shown, the blind via 13 is arranged on the left side of the semiconductor device 12 .

[0045] Case 2: When there are two or more semiconductor devices, the blind vias are arranged on the left or right side of the semiconductor device. Figure 1C , the blind hole 13 is located on the right side of the semiconductor device 12 and the semiconductor device 14 .

[0046] Here, the blind hole may be formed by etching. For example, the etching process may adopt at least one of a dry etching process, a wet etching process or an assisted electrochemical etching process to form the blind hole in the wafer.

[0047] Step S103: depositing a first metal material in the blind hole to form a through silicon via;

[0048] Here, in addition to the chemical vapor deposition (CVD) process and the physical vapor deposition (PVD) process, the "deposition" step can also use the chemical plating (CP) process, so that the first metal material can be filled on the surface of the wafer and the inner wall of the blind hole to form a conductive layer.

[0049] Through-silicon-via (TSV) technology is a solution for interconnecting stacked chips in three-dimensional (3D) integrated circuits. TSV technology maximizes chip stacking density in three dimensions, minimizes interconnect lines between chips, and minimizes overall dimensions. This effectively enables 3D chip stacking, resulting in more complex, higher-performance, and more cost-effective chips.

[0050] Here, the first metal material is used to fill the blind hole to form a conductive layer of the through-silicon via. The conductive layer is used to achieve electrical connection between the two wafers after wafer bonding. Therefore, the first metal material can be any conductive metal material, such as tungsten (W), aluminum (Al) and copper (Cu). Generally speaking, different conductive materials use different deposition processes. When tungsten is used as the conductive material, the CVD method is used; when aluminum is used as the conductive material, the CVD method and the PVD method are used; when copper is used as the conductive material, the CP method is used.

[0051] Step S104 , removing the first metal material deposited on the surface of the wafer and planarizing the surface of the wafer.

[0052] In actual applications, after the TSV is formed, excess first metal material will be deposited on the upper surface of the wafer, resulting in some bumps and grooves on the upper surface of the wafer. Therefore, it is necessary to remove the excess first metal material deposited on the surface of the wafer. The removal process used is etching, grinding, polishing, etc.

[0053] In some embodiments, the planarization is a technique for flattening the wafer surface, which can improve the performance of the wafer or chip. The planarization of the wafer surface includes: planarizing the wafer surface through a chemical mechanical polishing process.

[0054] In an embodiment of the present application, after the through silicon via is formed, planarization is performed through a chemical mechanical polishing process. Compared with related technologies, planarization only needs to be performed once after the through silicon via is formed. When the bonding pad is subsequently formed, the wafer surface is flat, which not only simplifies the wafer manufacturing process, but also reduces the deviation of the wafer surface during the subsequent wafer bonding process due to unevenness, thereby effectively improving the reliability of the stacked chip.

[0055] Please refer to the following Figures 2A to 2DSteps S101 to S104 are described in further detail.

[0056] First reference Figure 2A , the wafer 10 includes a semiconductor device 12; then refer to Figure 2B , a blind hole 13 is formed at a preset position on the wafer surface by etching process; then referring to Figure 2C , a first metal material is deposited in the blind hole 13 using a CP process, such as copper (Cu), to form a through silicon via 15; after the through silicon via is formed, excess first metal material is also attached to the surface of the wafer, which may form defects such as pits or protrusions on the surface of the wafer. Therefore, Figure 2D In the process, etching, grinding, polishing and other processes are used to remove the first metal material deposited on the surface of the wafer 10 and flatten the surface of the wafer 10.

[0057] Figures 2A to 2E In the figure, the semiconductor device 12 includes a memory device, metal interconnection layers M1, M2, and M3, as well as contact holes CT, through holes (vias) V1 and V2. The contact hole CT is a connection channel between the memory device, such as a transistor, and M1. The through hole V1 is a connection channel between the metal interconnection layer M1 formed on the intermetallic dielectric (IMD) layer 1 and the metal interconnection layer M2. The through hole V2 is a connection channel between the metal interconnection layer M2 formed on the IMD2 and the metal interconnection layer M3.

[0058] In some embodiments, the process of forming the through silicon via 15 can adopt a via last process, that is, the through silicon via 15 is formed after the device structure is formed, so as to avoid the contamination problem of the through silicon via caused by metal deposition during the device structure formation process.

[0059] In the embodiment of the present application, a memory device is used as an example for description. The semiconductor device includes a memory device, such as a transistor. Thus, the formation of step S101 includes:

[0060] Step S111, providing a substrate;

[0061] Here, the substrate may be a silicon substrate. In other embodiments, the substrate may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0062] Step S112: forming the semiconductor device on the substrate; wherein the semiconductor device includes a memory device and a metal interconnection layer.

[0063] In some embodiments, the memory device in the semiconductor device may be a transistor, and the metal interconnect layer may form a connection through a metal conductive material to connect different memory devices to form a circuit. When forming the metal interconnect layer in the embodiment of the present application, it is necessary to consider the resistivity of the interconnect material, the step coverage and surface flatness of the deposition process, electromigration and stress, etc. The use of low-resistivity materials for interconnection can reduce the loss and RC delay of the chip and increase the speed of the chip, wherein the RC delay refers to the signal delay caused by resistance (R) and capacitance (C) during the charging and discharging process. The materials that can be used as interconnect metals in the metal interconnect layer include tungsten (W), copper (Cu), aluminum (Al), etc.

[0064] Reference below Figure 2E Further understanding of step S111 and step S112 is provided.

[0065] exist Figure 2E In the embodiment, wafer 10 includes a substrate 11 and a semiconductor device 12. Semiconductor device 12 is located on the upper surface of substrate 11, wherein substrate 11 includes a shallow trench isolation (STI). Semiconductor device 12 in the embodiment of the present application includes a memory device 121 and a metal interconnect layer 122, wherein metal interconnect layer 122 includes metal interconnect layers M1, M2, and M3. Contact hole CT is used to achieve electrical connection between memory device 121 and metal interconnect layer M1, through hole V1 is used to achieve electrical connection between metal interconnect layer M1 and metal interconnect layer M2, and through hole V2 is used to achieve electrical connection between metal interconnect layer M2 and metal interconnect layer M3.

[0066] During the through-silicon via (TSV) manufacturing process and wafer-on-wafer bonding in the packaging process, wafer-on-wafer hybrid bonding (WHB) cannot be performed due to unevenness in the wafer's surface passivation layer. Some of these unevenness is caused by the electroplating process during wafer bonding. After the electroplating process, the interlayer dielectric layer and passivation layer formed sequentially also exhibit unevenness.

[0067] The present application also provides a method for forming a semiconductor structure, wherein a through silicon via is formed in a through silicon via process stage, referring to Figure 3 ,include:

[0068] Step S301: providing a wafer having a semiconductor device formed thereon;

[0069] Here, in the embodiment of the present application, after the interlayer dielectric layer is formed, the passivation layer may not be formed, so that the surface of the wafer can be the interlayer dielectric layer.

[0070] Step S302: etching the wafer with a preset position on the surface of the wafer as an etching starting point to form a blind hole in the wafer;

[0071] In some embodiments, the blind vias can be fabricated using deep reactive ion etching (DRIE) or laser drilling. DRIE combines the deposition of a polymer passivation layer with the etching of single-crystal silicon, alternating these two processes. This prevents interaction between deposition and etching, ensuring a stable and reliable passivation layer and ultimately forming a high-aspect-ratio structure with steep sidewalls.

[0072] Step S303: depositing a first metal material in the blind hole to form a through silicon via;

[0073] In the embodiment of the present application, the through silicon via may be prepared after the FEOL and middle of line (MOL) processes and before the BEOL process.

[0074] In some embodiments, the implementation of step S303 includes:

[0075] Step S331: depositing an insulating layer covering the inner wall of the blind hole on the inner wall of the blind hole;

[0076] Here, the insulating layer is used to prevent the first metal material (forming a conductive layer) filled in the subsequent process from conducting electricity and the substrate, and to protect the substrate from being damaged. The materials of the insulating layer in this embodiment include silicon oxide (such as SiO2), silicon nitride (such as Si3N4), etc. The deposition of the insulating layer is usually carried out by PECVD method, thermal oxidation technology (Thermal Oxidation) or vacuum vapor deposition technology. Among them, the PECVD method has a high deposition rate, low process temperature and strong film coverage ability, and is widely used to deposit insulating layer materials such as SiO2 and Si3N4; thermal oxidation technology is used to deposit silicon dioxide; vacuum vapor deposition technology is used to deposit paraxylene materials.

[0077] In some embodiments, after depositing an insulating layer covering the inner wall of the blind hole, a barrier layer and a seed layer are deposited in sequence, that is, on the inner wall of the blind hole, the deposition order is: first deposit an insulating layer on the inner wall of the blind hole; then deposit a barrier layer on the insulating layer; and finally deposit a seed layer on the barrier layer.

[0078] The barrier layer is used to prevent the diffusion of the first metal material in subsequent processes and to improve the adhesion strength of the seed layer. Common materials for the barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium, vanadium nitride, niobium, or niobium nitride. The barrier layer can be deposited using PVD, CVD, or plasma enhanced magnetron sputtering (PEMS).

[0079] The seed layer serves as a bridge for the subsequent formation of the conductive layer in the TSV. The seed layer can be made of any conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or any combination thereof. The seed layer can be fabricated using one or more of the same deposition methods as the barrier layer.

[0080] Step S332 : After forming the insulating layer, depositing a first metal material to form a conductive layer of a through silicon via.

[0081] In some embodiments, the conductive layer is used for conducting electricity. The conductive material in the conductive layer can be the same as or different from the conductive material in the seed layer. Generally, the conductive layer is made of copper (Cu).

[0082] Step S304 , removing the first metal material deposited on the surface of the wafer and planarizing the surface of the wafer.

[0083] The planarization process here uses chemical mechanical polishing (CMP). During implementation, the material on the wafer surface first undergoes a chemical reaction with the oxidant and catalyst in the polishing liquid, forming a relatively easy-to-remove soft layer. The abrasive in the polishing liquid and the polishing pad then mechanically remove the soft layer, exposing the workpiece surface. The chemical reaction and mechanical action continue, and this cycle repeats, completing the workpiece surface polishing.

[0084] Please refer to the following Figures 4A to 4D Steps S301 to S304 are further described in detail.

[0085] refer to Figure 4A The wafer 10 includes a substrate 11, a semiconductor device 12, and an interlayer dielectric layer 124, wherein the surface of the wafer 10 is the interlayer dielectric layer 124. Figure 4B In the embodiment, at a preset position on the upper surface of the wafer 10, the interlayer dielectric layer 124 and the substrate 11 are sequentially etched by DRIE technology to form a blind hole 13 in the wafer 10; then, referring to Figure 4CAs shown in the left figure, an isolation layer 15a and a conductive layer 15b are sequentially deposited in the blind hole 13 by one or more deposition processes, such as CVD or PVD, thereby forming a through silicon via 15.

[0086] In addition, steps S331 to S332 can refer to Figure 4C Understand. Figure 4C In the right figure, the formation of the silicon through via includes: depositing an insulating layer 151, a barrier layer 152, a seed layer 153 and a conductive layer 15b on the inner wall of the blind hole 13 to cover the inner wall of the blind hole 13, wherein the insulating layer 151, the barrier layer 152 and the seed layer 153 form an isolation layer 15a.

[0087] During the TSV formation process, a variety of redundant materials are deposited on the wafer surface, such as the materials in the insulating layer, barrier layer, seed layer and conductive layer, so the wafer surface needs to be further processed. Figure 4D In the process, the CMP process can remove excess material from the surface of the wafer 10 and flatten the surface of the wafer 10. After the removal and flattening processes are completed, a through silicon via 15 with a flat surface is obtained.

[0088] The present application also includes a third method for forming a semiconductor structure, referring to Figure 5 , the method comprising:

[0089] Step S501: providing a wafer with semiconductor devices formed thereon.

[0090] Step S502: forming a blind hole in the wafer.

[0091] Step S503: depositing a first metal material in the blind hole to form a through silicon via.

[0092] Step S504 , removing the first metal material deposited on the surface of the wafer and planarizing the surface of the wafer.

[0093] Step S505 : forming bonding pads on the planarized wafer surface.

[0094] In practical applications, wafer bonding refers to the process of tightly combining two mirror-polished homogeneous or heterogeneous wafers through chemical and physical effects. After the wafers are bonded, the atoms at the wafer interface react under the action of external forces to form covalent bonds that combine them into one, and the bonding interface reaches a specific bonding strength.

[0095] In an embodiment of the present application, a CMP process is used to flatten the wafer surface after forming the TSV through hole, and then a bonding pad is formed on the flattened wafer surface. In this way, compared with related technologies, only one flattening treatment is required, and the wafer surface is flat after forming the bonding pad, which simplifies the process flow.

[0096] In some embodiments, the implementation of step S505 includes:

[0097] Step S551, depositing a barrier layer on the planarized wafer surface;

[0098] Here, the barrier layer is an isolation layer formed between the upper and lower materials, preventing mutual diffusion between the upper and lower materials and improving the adhesion between the upper and lower materials and the barrier layer material. The barrier layer metal requirements are low contact resistance, good sidewall and step coverage, and high barrier properties. In the embodiments of this application, the barrier layer uses materials such as silicon dioxide, silicon nitride, and silicon oxynitride. The barrier layer is deposited using either CVD or PVD methods.

[0099] Step S552, depositing a hard mask layer on the surface of the barrier layer;

[0100] Hard mask process technology refers to the technology of using very thin photoresist to transfer the pattern to the hard mask layer (also known as the intermediate layer), and then transferring the pattern to the underlying thin film material through the intermediate layer.

[0101] In some embodiments, the material of the hard mask layer may be silicon dioxide, silicon nitride, silicon carbide, or tantalum oxide, etc. The hard mask layer may be prepared by plasma enhanced chemical vapor deposition (PECVD) or CVD.

[0102] Step S553: ​​patterning the hard mask layer, and etching the surface of the barrier layer using the mask pattern to form through holes exposing the metal interconnect layer and the blind vias;

[0103] Here, patterning refers to the process of transferring the pattern from the photoresist layer to the hard mask layer. Common patterning processes are dry etching, including plasma etching (PE), plasma sputtering etching (PSE), or reactive ion etching (RIE).

[0104] In some embodiments, the process of etching the mask pattern may be dry etching, and one or more etching processes that are the same as the patterning process may be used.

[0105] In some embodiments, the through hole preparation technology may be the same as the blind hole preparation technology in S102, including etching the upper surface of the metal interconnect layer and the upper surface of the through silicon via by dry etching or wet etching to form the through hole.

[0106] Step S554 : depositing a second metal material in the through hole to form a bonding pad.

[0107] In some embodiments, the second metal material is the same as the first metal material. The “deposition” process may be the same as one or more processes used to deposit the first metal material.

[0108] Please refer to the following 6A to 6D Steps S551 to S553 are described in further detail.

[0109] refer to Figure 6A First, a barrier layer 125 is deposited on the upper surface of the interlayer dielectric layer 124 by a CVD method or a PVD method; then, Figure 6B In the embodiment, a hard mask layer 16 is deposited on the upper surface of the barrier layer 125 by a PECVD method or a CVD method; then, the hard mask layer 16 is patterned by dry etching; and the upper surface of the barrier layer 125 is further etched using the mask pattern to form a Figure 6C The metal interconnection layer 122 and the through-silicon via 15 are exposed in the through-holes 17a, 17b and 17c; finally, the through-holes 17a, 17b and 17c are filled with a second metal material to form Figure 6D The bonding pads 18a, 18b and 18c in FIG.

[0110] In some embodiments, when the second metal material used for filling is different, the filling process used is different. For example, when tungsten is used as the conductive material, CVD method is used; when aluminum is used as the conductive material, CVD method and PVD method are used; when copper is used as the conductive material, CP method is used.

[0111] In addition, reference Figure 6C It can be seen that the through hole 17a can expose the silicon through hole 15, and the through holes 17b and 17c can expose the metal interconnection layer 122; Figure 6D It can be seen that the bonding pad 17 a is electrically connected to the through silicon via 15 , and the bonding pads 17 b and 17 c are electrically connected to the metal interconnection layer 122 .

[0112] In an embodiment of the present application, first, a barrier layer is deposited on the planarized surface of the wafer; secondly, the surface of the barrier layer is etched to form a through hole exposing the metal interconnection layer and the blind hole; then, a second metal material is deposited in the through hole, and finally, a CMP process is performed on the wafer surface again to remove excess second metal material, thereby forming a bonding pad with a smooth surface.

[0113] In some embodiments, assuming that the surface where the bonding pad is located is the first surface, after step S505, the method further includes:

[0114] Step S506 : starting from a second surface opposite to the first surface, thinning the wafer with the bonding pads formed thereon to a predetermined thickness.

[0115] Here, the preset thickness refers to the wafer thickness required for later packaging. This preset thickness varies depending on the later packaging process. Wafer thinning is used for 3D packaging. After wafer thinning, the aperture-to-thickness ratio of the formed through-holes is within a reasonable range, and the thickness of the final package is acceptable.

[0116] In some embodiments, wafer thinning can be performed using mechanical grinding, dry etching, or wet etching. To prevent warping, sagging, extended surface damage, and chip cracking after thinning, a layer of glass (or silicon) support material is applied to the wafer surface before thinning to serve as a support to secure and strengthen the ultra-thin wafer. Furthermore, a sheet of material with an area and thickness comparable to the wafer's is placed around the periphery of the wafer to ensure uniform force on the wafer during thinning. This results in a wafer with flawless edges, no cracks, and consistent thickness.

[0117] In the embodiment of the present application, after forming the through silicon via and the bonding pad, the wafer needs to be thinned to a preset thickness. The wafer thinning process can improve the heat dissipation effect of the chip.

[0118] based on Figure 6D , an embodiment of the present application provides a semiconductor structure, including:

[0119] a wafer 10 having semiconductor devices 12 formed thereon;

[0120] Through silicon vias 15 formed in the wafer;

[0121] Bond pads 18a, 18b, and 18c electrically connected to the through silicon vias.

[0122] In some embodiments, see Figure 6D The wafer 10 includes a substrate 11 and a semiconductor device 12 formed on the substrate 11 ; wherein the semiconductor device includes a memory device 121 and a metal interconnection layer 122 .

[0123] Continue to see Figure 6D The semiconductor device 12 is formed in the interlayer dielectric layer 124 , and the through silicon via 15 penetrates the substrate 11 and the interlayer dielectric layer 124 .

[0124] In some embodiments, see Figure 6CThe through silicon via 15 includes an isolation layer 15 a and a conductive layer 15 b , wherein the isolation layer 15 a includes an insulating layer 151 , a barrier layer 152 and a seed layer 153 .

[0125] In some embodiments, the bonding pad is formed of a second metal material.

[0126] In the embodiment of the present application, a method for wafer bonding is also provided, referring to Figure 7 , the method comprising:

[0127] Step S701: providing a first wafer and a second wafer, wherein the first wafer and the second wafer can be manufactured using the method provided in the above embodiment;

[0128] Here, the first wafer and the second wafer may be the same wafer or different wafers. The conductive materials in the bonding pads formed in the first wafer and the second wafer may be the same or different.

[0129] Step S702 : hybrid bonding the first wafer and the second wafer to form a hybrid bonding area.

[0130] Here, the hybrid bonding region is formed by welding corresponding bonding pads in the first wafer and the second wafer. Common welding processes include reflow soldering (RS) and thermal compression bonding (TCB).

[0131] Reference below Figure 8 A detailed description of the wafer bonding method is given.

[0132] exist Figure 8 The wafers in the embodiment include two, including a first wafer 81 and a second wafer 82; the first wafer 81 and the second wafer 82 can be manufactured by the method provided in the above embodiment, and the first wafer 81 and the second wafer 82 can be the same or different; the first wafer 81 and the second wafer 82 both include a bonding pad structure, and the structure of the bonding pad can be seen in Figure 6D The conductive materials of the bonding pads formed in the first wafer 81 and the second wafer 82 can be the same or different. Using an RS welding process or a TCB welding process, the corresponding bonding pads on the first surface of the wafer 81 and the first surface of the wafer 82 can be welded together to form a hybrid bonding area 83.

[0133] In the embodiment of the present application, after forming the TSV through silicon via, the CMP process is used to flatten the wafer surface to form a flat wafer surface, and then a bonding pad with a flat surface is prepared, so that wafer bonding can be achieved in one step, simplifying the process flow.

[0134] The semiconductor structures in the embodiments of this application are similar to the methods for forming the semiconductor structures in the aforementioned embodiments. For technical features not fully disclosed in the embodiments of this application, please refer to the aforementioned embodiments for understanding. The features disclosed in the various method or device embodiments provided herein may be combined arbitrarily to form new method or device embodiments, provided that they do not conflict.

[0135] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a wafer having a semiconductor device formed thereon; said providing a wafer having a semiconductor device formed thereon, comprising: providing a substrate; forming the semiconductor device and an interlayer dielectric layer on the substrate; wherein the semiconductor device comprises a memory device and a metal interconnect layer; the metal interconnect layer is located in the interlayer dielectric layer; forming a blind hole in the wafer, wherein the blind hole extends from a surface of the interlayer dielectric layer into the substrate; Depositing a first metal material in the blind hole to form a through silicon via; The first metal material deposited on the surface of the wafer is removed, and the surface of the wafer is planarized.

2. The method according to claim 1, characterized in that Also includes: A bonding pad is formed on the planarized wafer surface.

3. The method according to claim 2, characterized in that The method of forming a bonding pad on the planarized wafer surface includes: depositing a hard mask layer on the planarized wafer surface; patterning the hard mask layer to form a through hole of the blind hole; and depositing a second metal material in the through hole to form a bonding pad.

4. The method according to claim 3, characterized in that The hard mask layer material includes silicon nitride.

5. The method according to claim 3, characterized in that The first metal material is the same as the second metal material.

6. The method according to any one of claims 1 to 5, characterized in that At least one of a dry etching process and a wet etching process is used to form a blind hole in the wafer.

7. The method according to any one of claims 1 to 5, characterized in that Depositing a first metal material in the blind hole to form a through silicon via includes: depositing an insulating layer covering the inner wall of the blind hole; and after forming the insulating layer, depositing the first metal material to form a conductive layer of the through silicon via.

8. The method according to any one of claims 1 to 5, characterized in that The planarizing the wafer surface includes planarizing the wafer surface through a chemical mechanical polishing process.

9. The method according to any one of claims 2 to 4, characterized in that The surface where the bonding pad is located is a first surface, and the method further includes: starting from a second surface opposite to the first surface, thinning the wafer on which the bonding pad is formed to a preset thickness.

10. A wafer bonding method, characterized in that: include: A first wafer and a second wafer are provided, wherein the first wafer and the second wafer are manufactured by the method according to any one of claims 1 to 9; and the first wafer and the second wafer are hybrid-bonded.

11. A semiconductor structure, characterized in that include: A wafer having a semiconductor device formed thereon; the wafer comprising: a substrate; a semiconductor device and an interlayer dielectric layer on the substrate; wherein the semiconductor device comprises a memory device and a metal interconnect layer; the metal interconnect layer is located in the interlayer dielectric layer; through-silicon vias formed in the wafer; a bonding pad electrically connected to the through silicon via; The through silicon via passes through the substrate and the interlayer dielectric layer.

12. The semiconductor structure according to claim 11, wherein: The through silicon via includes an insulating layer and a conductive layer formed of a first metal material; the bonding pad is formed of a second metal material.

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